JP2000353949A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high speed operation by intervening a source follower type logic circuit between an input logic circuit which outputs a logical signal with an upper limit value as a potential higher than a power source potential and a lower limit value as a potential higher than a ground potential and an output driver which outputs a logical signal with an upper limit value as the power source potential and a lower limit value as the ground potential. SOLUTION: Since a source follower type logic circuit 18 is intervened between a pseudo-nMOS circuit 11 and a CMOS inverter 22, it is possible to shift a center potential of an output logical signal of the pseudo-nMOS circuit 11 in a ground potential direction even if a lower limit value of the output signal of the pseudo-nMOS circuit 11 is raised and an amplitude of the output logical signal of the pseudo-nMOS circuit 11 is made smaller. Therefore, even if a circuit threshold of a CMOS inverter 22 is lower than the central potential of the output logical signal of the pseudo-nMOS circuit 11, it is possible to have the CMOS inverter 22 operate so that a rising time and a lowering time becomes equal to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logic circuit mounted on a semiconductor integrated circuit requiring high-speed operation such as an MPU.

[0002]

2. Description of the Related Art Conventionally, as this kind of logic circuit, for example, a four-input OR circuit as shown in FIG. 7 has been proposed. In FIG. 7, A, B, C, and D are input logic signals,
The level is the ground potential VSS, and the H level is the power supply potential VDD.

Further, 1 is a pseudo nMO which forms an input logic circuit.
S circuits, and 2, 3, 4, and 5 are nMOSs whose on and off are controlled by input logic signals A, B, C, and D, respectively.
A transistor 6 has a gate grounded, and is a pull-up pMOS transistor which is always turned on during operation. A transistor 7 is an output terminal of the pseudo nMOS circuit 1.

Reference numeral 8 denotes a CMOS inverter serving as an output driver; 9, a pMOS transistor for pull-up; 10, an nMOS transistor for pull-down;
Is an output logic signal obtained by ORing the input logic signals A, B, C and D.

FIG. 8 is a waveform diagram for explaining the operation of the pseudo nMOS circuit 1, and shows the relationship between the potentials of the input logic signals A to D and the potential of the output terminal 7 of the pseudo nMOS circuit 1. Here, input logic signals A to D are all at ground potential VSS.
In this case, the nMOS transistors 2 to 5 are all turned off, and the output terminal 7 of the pseudo nMOS circuit 1 is charged by the pMOS transistor 6 to become the power supply potential VDD.

From this state, for example, the input logic signal A
Changes to the power supply potential VDD, the nMOS transistor 2 is turned on, and a drain current flows through the nMOS transistor 2, so that the potential of the output terminal 7 of the pseudo nMOS circuit 1 decreases.

However, since the pMOS transistor 6 is always turned on during operation, the pseudo nM
The potential of the output terminal 7 of the OS circuit 1 does not decrease to the ground potential VSS, but settles to a potential VA determined by a current driving capability ratio between the nMOS transistor 2 and the pMOS transistor 6, that is, a so-called β ratio.

Here, the nMOS transistor 2 and the pMO
The β ratio with the S transistor 6 is β2 / β6, where β2 is the current driving capability of the nMOS transistor 2 and β6 is the current driving capability of the pMOS transistor 6.

Here, the current driving capability β is defined as β = (με / tox) (W / L), μ is the mobility of electrons or holes, ε is the relative dielectric constant of the gate oxide film, and tox is the gate. The thickness of the oxide film, W is the gate width, and L is the gate length.

As described above, the amplitude value of the output logic signal of the pseudo nMOS circuit 1 is (VDD-VA),
Since the amplitude value of the output logic signal of the MOS circuit is VDD, it can be said that the pseudo nMOS circuit 1 is a small-amplitude circuit in which the amplitude of the output logic signal is smaller by VA than a normal CMOS circuit. In general, a small-amplitude circuit has a feature that the delay time of the circuit is short and high-speed.

FIG. 9 shows that the pseudo nMOS circuit 1 has a normal CMO.
FIG. 7 is a waveform diagram for explaining that the delay time of the circuit is shorter and faster than that of the S circuit. For example, when the amplitude of the output logic signal of the pseudo nMOS circuit 1 is の of the output logic signal of the CMOS circuit. Is shown.

Here, when the potential of the output logic signal of the pseudo nMOS circuit 1 and the potential of the output logic signal of the ordinary CMOS circuit simultaneously decrease from the H level to the L level, the output logic of the pseudo nMOS circuit 1 Although the potential of the signal and the potential of the output logic signal of the normal CMOS circuit decrease at almost the same rate, the output logic signal of the pseudo nMOS circuit 1 reaches the final potential VDD / 2 earlier by the small amplitude. The output logic signal of a normal CMOS circuit is a pseudo nMO
The output logic signal of the S circuit 1 reaches the ground potential VSS after reaching the final potential VDD / 2.

Therefore, comparing the delay time at the time when the amplitude of the output logic signal is 50%, it is found that the ordinary CMOS
As compared with the output logic signal of the circuit, the output logic signal of the pseudo nMOS circuit 1 has a delay time shorter by ΔT, and the normal CMOS
The output logic signal of the circuit reaches the ground potential with a delay of 2ΔT from the time when the output logic signal of the pseudo nMOS circuit 1 reaches the final potential VDD / 2.

[0014]

By the way, pseudo nMO
The L level value VA of the output logic signal of the S circuit 1 is further increased, and the amplitude value (VD
When D-VA) is further reduced, the speed of the pseudo nMOS circuit 1 can be further increased, but in this case, the rise time and the fall time of the CMOS inverter 8 become equal. As described above, it is necessary to adjust the β ratio of the CMOS inverter 8 so that the circuit threshold value of the CMOS inverter 8 becomes [VA + (VDD−VA) / 2] which is the center potential of the output logic signal of the pseudo nMOS circuit 1. .

The β ratio of the CMOS inverter 8 is pM
Assuming that the current driving capability of the OS transistor 9 is β9 and the current driving capability of the nMOS transistor 10 is β10, β10 / β9, where β is defined by β = (με / tox) (W / L) as described above. However, since the physical constants that can be easily controlled by the designer are generally the gate width W and the gate length L, the designer must determine the gate width W and the gate length L and adjust the β ratio. become.

FIG. 10 is a diagram showing the relationship between the 1 / β ratio and the circuit threshold in the CMOS inverter 8. As is apparent from FIG. 10, when the 1 / β ratio increases, the circuit The threshold value increases, but as the 1 / β ratio increases, the CMO
The circuit threshold of the S inverter 8 will saturate to a constant value VT.

That is, even if the L level value VA of the output logic signal of the pseudo nMOS circuit 1 is further increased to reduce the amplitude (VDD-VA) of the output logic signal of the pseudo nMOS circuit 1, the circuit threshold value of the CMOS inverter 8 is Cannot be set to a fixed value VT or more.
There is a problem that the amplitude of the output logic signal of the S circuit 1 cannot be reduced to a certain degree or more, and further higher speed cannot be achieved.

In view of the foregoing, the present invention provides an input logic circuit that outputs a logic signal whose upper limit is set to a power supply potential and whose lower limit is set to a potential higher than the ground potential, an upper limit is set to a power supply potential, and the lower limit is set to a ground potential. A logic circuit having an output driver that outputs a logic signal to be output, wherein the lower limit value of the output logic signal of the input logic circuit is increased to increase the speed of the output logic signal of the input logic circuit by reducing the amplitude. It is a first object of the present invention to provide a logic circuit capable of performing the following.

Further, the present invention operates in synchronization with a clock signal. When the clock signal has one logical value, the output is determined, and a logical signal having an upper limit value as a power supply potential and a lower limit value as a ground potential is provided. Input logic circuit to output, upper limit to power supply potential,
It is a second object of the present invention to provide a logic circuit having an output driver for outputting a logic signal whose lower limit is set to the ground potential, which can achieve high speed.

[0020]

According to the present invention, a logic circuit according to a first aspect of the present invention includes an input logic circuit for outputting a logic signal whose upper limit is set to a power supply potential and whose lower limit is set to a potential higher than the ground potential, A source-follower type logic circuit having an output logic signal of a logic circuit as an input logic signal, and a logic signal having an output logic signal of the source follower-type logic circuit as an input logic signal, an upper limit value being a power supply potential and a lower limit value being a ground potential. Is provided.

According to the first aspect of the present invention, even if the lower limit value of the output logic signal of the input logic circuit is increased and the amplitude of the output logic signal of the input logic circuit is reduced, the source follower type logic circuit can be used. The potential of the output logic signal of the input logic circuit can be shifted in the direction of the ground potential.

Therefore, without adjusting the β ratio of the output driver so that the circuit threshold value of the output driver matches the center potential of the output logic signal of the input logic circuit,
Even when the circuit threshold value of the output driver is lower than the center potential of the output logic signal of the input logic circuit, the output driver can be operated so that the rise time and the fall time are equal.

In the logic circuit according to the second aspect of the present invention, the logic circuit operates in synchronization with the clock signal, the output is determined when the clock signal has one logic value, the upper limit is set to the power supply potential, and the lower limit is set to the ground. An input logic circuit that outputs a logic signal having a potential, a source follower logic circuit that has an output logic signal of the input logic circuit as an input logic signal, and an output logic signal of the source follower logic circuit has an input logic signal; It has an output driver that outputs a logic signal with the upper limit being the power supply potential and the lower limit being the ground potential.

According to the second aspect of the present invention, the upper limit value of the output logic signal of the source follower type logic circuit is lower than the upper limit value of the output logic signal of the input follower type logic circuit. The amplitude of the output logic signal is smaller than the amplitude of the output logic signal of the input logic circuit.

Therefore, by selecting the circuit threshold value of the output driver so as to be about the center potential of the output logic signal of the source follower type logic circuit, the operation speed can be improved,
Higher speed can be achieved.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, referring to FIGS. 1 to 6, a first embodiment to a third embodiment of the present invention will be described.
An example in which the invention is applied to an R circuit will be described.

First Embodiment FIG. 1, FIG. 2 FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG.
Reference numeral 11 denotes a pseudo nMOS circuit that forms an input logic signal, and 12, 13, 14, and 15 denote nMOSs whose on and off are controlled by input logic signals A, B, C, and D, respectively.
A transistor 16 is a pull-up pMOS transistor which is always turned on during operation, and 17 is an output terminal of the pseudo nMOS circuit 11.

Here, the nMOS transistors 12, 1
3, 14, and 15, the drains are connected to the output terminal 17 of the pseudo nMOS circuit 11, the sources are grounded, and the input logic signals A, B, C, and D are applied to the gates, respectively. The pMOS transistor 16 has a source connected to the power supply, a drain connected to the output terminal 17 of the pseudo nMOS circuit 11, and a gate grounded.

Reference numeral 18 denotes a source follower type logic circuit; 19, an nMOS transistor as an input transistor; 20, an nMOS transistor as a load element;
1 is an output terminal of the source follower type logic circuit 18.

Here, the nMOS transistor 19 has a drain connected to a power supply and a gate connected to the pseudo nMOS circuit 1.
1, the source is connected to the output terminal 21 of the source follower type logic circuit 18, and the nMOS
The transistor 20 has a drain connected to the source of the nMOS transistor 19, a source grounded, and a gate connected to a power supply.

Reference numeral 22 denotes a CMOS as an output driver
An inverter 23 is a pull-up pMOS transistor and 24 is a pull-down nMOS transistor.

Here, the pMOS transistors 23 and n
The MOS transistor 24 has its gates connected to each other, and the connection point is connected to the output terminal 21 of the source follower type logic circuit 18.
, The source of the pMOS transistor 23 is connected to the power supply, the drain of the nMOS transistor 24 is connected to the drain of the pMOS transistor 23, and the source is grounded.

FIG. 2 is a waveform diagram for explaining the operation of the first embodiment of the present invention, in which the potentials of the input logic signals A to D, the potential of the output terminal 17 of the pseudo nMOS circuit 11, the source follower type The potential of the output terminal 21 of the logic circuit 18 is shown.

If the input logic signals A to D are all at the ground potential VSS, the nMOS transistors 12 to 15
Are all turned off, and the output terminal 17 of the pseudo nMOS circuit 11 is turned off.
Is charged by the pMOS transistor 16, the potential of the output terminal 17 of the pseudo nMOS circuit 11 becomes the power supply potential VDD.

At this time, the nMOS transistor 1
9 and 20 are both on, and the output terminal 21 of the source follower type logic circuit 18 is connected to the nMOS transistors 19 and 20.
[= Β20 (current driving capability of nMOS transistor 20) / β19 (current driving capability of nMOS transistor 19)].

From this state, for example, the input logic signal A
Changes to the power supply potential VDD, the nMOS transistor 12 is turned on, and a drain current flows through the nMOS transistor 12, so that the output terminal 1 of the pseudo nMOS circuit 11
The potential of 7 decreases.

However, since the pMOS transistor 16 is configured to be always turned on during operation, the potential of the output terminal 17 of the pseudo nMOS circuit 11 does not drop to the ground potential, and the nMOS transistor 12 and the pMOS transistor The potential VA is settled to the potential VA determined by the β ratio [= β12 (current driving capability of the nMOS transistor 12) / β16 (current driving capability of the nMOS transistor 16)] with the ratio 16.

In this case, in the source follower type logic circuit 18, the gate potential of the nMOS transistor 19 decreases, and as a result, the drain current of the nMOS transistor 19 decreases and becomes equal to the drain current of the nMOS transistor 20. It will be stable. At this time, the potential of the output terminal 21 of the source follower type logic circuit 18 becomes VL (<VH).

As described above, the potential of the output terminal 17 of the pseudo nMOS circuit 11 is a potential whose upper limit is VDD and its lower limit is VA, but the potential of the output terminal 21 of the source follower type logic circuit 18 is a pseudo potential. The upper limit value obtained by shifting the potential of the output terminal 17 of the nMOS circuit 11 in the direction of the ground potential is VH, and the lower limit value is VL.

That is, the output logic signal of the pseudo nMOS circuit 11 is a logic signal having an upper limit value of VDD and a lower limit value of VA, and the output logic signal of the source follower type logic circuit 18 is Are shifted to the ground potential direction, the upper limit value is VH, and the lower limit value is VL.

As a result, the circuit threshold of the CMOS inverter 22 does not need to be the center potential [VA + (VDD−VA) / 2] of the output logic signal of the pseudo nMOS circuit 11,
It is sufficient if the center potential of the output logic signal of the source follower type logic circuit 18 is [VL + (VH-VL) / 2].

As described above, according to the first embodiment of the present invention, since the source follower type logic circuit 18 is interposed between the pseudo nMOS circuit 11 and the CMOS inverter 22, the output of the pseudo nMOS circuit 11 Even if the lower limit of the logic signal is increased and the amplitude of the output logic signal of the pseudo nMOS circuit 11 is reduced, the center potential of the output logic signal of the pseudo nMOS circuit 11 can be shifted toward the ground potential.

Therefore, it is not necessary to adjust the β ratio of the CMOS inverter 22 so that the circuit threshold value of the CMOS inverter 22 matches the center potential of the output logic signal of the pseudo nMOS circuit 11, that is, the CMOS inverter 22
Is lower than the center potential of the output logic signal of the pseudo nMOS circuit 11, the CMOS inverter 2 is set so that the rise time and the fall time are equal.
2 can be operated, so that the pseudo nMOS circuit 1
By increasing the lower limit of the output logic signal of No. 1 and making the output logic signal of the pseudo nMOS circuit 11 have a small amplitude, it is possible to increase the speed.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. The second embodiment of the present invention is provided in the first embodiment of the present invention shown in FIG. A source follower type logic circuit 25 having a circuit configuration different from that of the source follower type logic circuit 18 is provided, and the other components are configured in the same manner as the first embodiment of the present invention shown in FIG.

The source follower type logic circuit 25 is provided with a resistor 26 in place of the nMOS transistor 20 included in the source follower type logic circuit 18 shown in FIG. 1, and the others are provided with the source follower type logic circuit 18 shown in FIG. It is configured similarly to.

As described above, according to the second embodiment of the present invention, the source follower type logic circuit 25 is interposed between the pseudo nMOS circuit 11 and the CMOS inverter 22, so that the present invention shown in FIG. The same operation and effect as in the first embodiment can be obtained.

Third Embodiment FIG. 4 to FIG. 6 FIG. 4 is a circuit diagram showing a third embodiment of the present invention. In the third embodiment of the present invention, the pseudo nMOS circuit 11 shown in FIG.
Instead, a dynamic logic circuit 27 is provided, and the other configuration is the same as that of the first embodiment of the present invention shown in FIG.

The dynamic logic circuit 27 is a pMOS
The gate of the transistor 16 is not grounded, and the clock signal CLK is applied to the gate of the pMOS transistor 16.
15 are not directly grounded, the sources of these nMOS transistors 12-15 are connected to the gates of the clock CL
It is configured to be grounded via an nMOS transistor 28 to which K is applied, and the other configuration is the same as the pseudo nMOS circuit 11 shown in FIG.

FIG. 5 is a waveform diagram for explaining the operation of the dynamic logic circuit 27. The dynamic logic circuit 27 has two operation periods, namely, a precharge period and an evaluation period (input logic signals A to A). D OR processing period)
And exists.

Here, clock signal CLK = ground potential V
At SS, the precharge period starts, the pMOS transistor 16 is turned on, the nMOS transistor 28 is turned off, and the potential of the output terminal 17 is precharged to the power supply potential VDD regardless of the logic values of the input logic signals A to D. Charged.

On the other hand, when the clock signal CLK becomes equal to the power supply potential VDD, the evaluation period starts, the pMOS transistor 16 is turned off, and the nMOS transistor 28 is turned on, so that the input logic signals A to D can be ORed.

At this time, for example, the input logic signal A = H
When the level and the input logic signal BD are equal to the ground potential VSS, the nMOS transistor 12 is turned on and the output terminal 1
The potential of 7 drops through the nMOS transistor 12 to reach the ground potential VSS.

On the other hand, when the input logic signals A to D = ground potential VSS, the nMOS transistors 12 to 15
= Off, and there is no line from the output terminal 17 to the ground. Therefore, the output terminal 17 becomes a floating node (dynamic node), and the potential of the output terminal 17 becomes the power supply potential V.
DD is maintained.

As described above, the dynamic logic circuit 27
Operates in synchronization with the clock signal CLK, and valid logic is output during the evaluation period when the clock signal CLK becomes the power supply potential VDD.

FIG. 6 is a waveform diagram for explaining the operation of the third embodiment of the present invention, where the input logic signal A = power supply potential V
DD, when the input logic signals BD are equal to the ground potential VSS and the clock signal CLK changes from the ground potential VSS to the power supply potential VDD, the potential change of the output terminal 17 of the dynamic logic circuit 27 and the source follower logic 3 shows a potential change at an output terminal 21 of the circuit 18.

That is, in the third embodiment of the present invention, input logic signal A = power supply potential VDD, input logic signal B
When D is the ground potential VSS and the clock signal CLK is at the ground potential VSS, the pMOS transistor 16 is turned on and the nMOS transistor 28 is turned off.
7 becomes the power supply potential VDD, and the potential of the output terminal 21 of the source follower type logic circuit 18 becomes lower than the power supply potential VDD by the effect of the nMOS transistor 19.
H.

From this state, if the clock signal CLK changes to the power supply potential VDD while the input logic signals A to D maintain their logical values, the pMOS transistor 16 is turned off and the nMOS transistor 28 is turned on. The potential of the output terminal 17 of the logic circuit 27 decreases from the power supply potential VDD to the ground potential VSS with the rise of the clock signal CLK, and the potential of the output terminal 21 of the source follower logic circuit 18 changes from the potential VH to the ground potential VSS. Will be reduced to

As described above, according to the third embodiment of the present invention, the upper limit value of the output logic signal output from the source follower type logic circuit 18 is larger than the upper limit value of the output logic signal of the dynamic type logic circuit 27. Therefore, the amplitude of the output logic signal of the source follower logic circuit 18 becomes smaller than the amplitude of the output logic signal of the dynamic logic circuit 27. Therefore, the circuit threshold value of the CMOS inverter 22 is set to the output logic of the source follower logic circuit 18. VH which is the central potential of the signal
By selecting so as to be about / 2, the operation speed can be improved and the speed can be increased.

In the third embodiment of the present invention,
The source follower type logic circuit 18 has nM
Although the OS transistor 20 is provided, instead of this,
A resistor may be provided.

[0060]

As described above, according to the first aspect of the present invention, even if the lower limit value of the output logic signal of the input logic circuit is increased and the amplitude of the output logic signal of the input logic circuit is reduced, ,
The source follower-type logic circuit can shift the potential of the output logic signal of the input logic circuit toward the ground potential, so that the circuit threshold of the output driver is adjusted to the central potential of the output logic signal of the input logic circuit. Without adjusting the β ratio of the output driver,
Even when the circuit threshold of the output driver is lower than the central potential of the output logic signal of the input logic circuit, the output driver can be operated so that the rise time and the fall time are equal, By increasing the lower limit value of the output logic signal and making the output logic signal of the input logic circuit a small amplitude, it is possible to increase the speed.

According to the second aspect, the upper limit value of the output logic signal of the source follower type logic circuit becomes lower than the upper limit value of the output logic signal of the input follower type logic circuit. Since the amplitude of the signal is smaller than the amplitude of the output logic signal of the input logic circuit, the operation speed is selected by selecting the circuit threshold of the output driver so as to be about the center potential of the output logic signal of the source follower type logic circuit. And speeding up can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a waveform chart for explaining an operation of a dynamic logic circuit provided in a third embodiment of the present invention.

FIG. 6 is a waveform chart for explaining the operation of the third embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an example of a conventional logic circuit.

8 shows a pseudo nMO included in the conventional logic circuit shown in FIG.
FIG. 4 is a waveform chart for explaining the operation of the S circuit.

FIG. 9 is a waveform diagram for explaining that a pseudo nMOS circuit has a shorter circuit delay time and a higher speed than a normal CMOS circuit.

FIG. 10 is a diagram showing a relationship between a 1 / β ratio and a circuit threshold in a CMOS inverter.

[Explanation of symbols]

 A, B, C, D Input logic signal X Output logic signal

Claims (2)

[Claims] 1. An input logic circuit for outputting a logic signal having an upper limit value equal to a power supply potential and a lower limit value higher than a ground potential, and a source follower type logic circuit using an output logic signal of the input logic circuit as an input logic signal. And an output driver that outputs a logic signal having an output logic signal of the source follower type logic circuit as an input logic signal, an upper limit value being the power supply potential, and a lower limit value being the ground potential. Logic circuit. 2. An input logic circuit which operates in synchronization with a clock signal, outputs when the clock signal has one logic value, and outputs a logic signal having an upper limit value as a power supply potential and a lower limit value as a ground potential. A source follower-type logic circuit having an output logic signal of the input logic circuit as an input logic signal; an output logic signal of the source follower-type logic circuit being an input logic signal; an upper limit value being the power supply potential; and a lower limit value being the lower limit value. A logic circuit, comprising: an output driver that outputs a logic signal having a ground potential.