JP2000353788A - Integrated semiconductor circuit - Google Patents

Abstract

(57) [Problem] To provide a circuit device having a differential amplifier in which disadvantageous switching characteristics are reduced. An integrated semiconductor circuit includes a differential amplifier (10) including two input transistors (T1, T2), one current source (10), and one load element (20). The NMOS transistors (T1, T2) are arranged in a p-conductivity type well (Wp).
p) is arranged on a substrate (Sp) of p conductivity type. The well (Wp) is electrically separated from the substrate (Sp). The well (Wp) has one well terminal (B), and this terminal is connected to the source terminal (S). By preventing the potential difference between the well terminal (B) and the source terminal (S) from occurring, the switching characteristics of the transistors (T1, T2) are not adversely affected, whereby the differential amplifier The switching state is not adversely affected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated semiconductor circuit having a differential amplifier having two input transistors, one current source, and one load element.

[0002]

2. Description of the Related Art Differential amplifiers can generally be used in integrated circuits in various ways. In particular, new generations of semiconductor memory components have new technology and do not require much internal supply voltage. An input signal amplifier conventionally used in the form of an inverter, which is also called an input receiver, cannot operate perfectly in the region where the supply voltage is low. This is because the signal transition cannot be reliably detected in part. A differential amplifier having a basic structure has a high input resistance like an inverter. Since the differential amplifier operates as specified even when the internal supply voltage is low, it can be used as an input receiver. The role of this differential amplifier is to detect the variable input signal and amplify it.

[0003] The various configurations of the differential amplifier basically have the same basic circuit known in the art. This circuit has two input transistors, one current source, and one active or passive load. The potential difference between the input signals applied to the two input transistors causes a potential change at the output of the differential amplifier. Input transistor is usually N
Manufactured in MOS technology. It generally has a higher amplification factor than a PMOS transistor and does not require much space.

[0004] Particularly in a DRAM type semiconductor memory, a differential amplifier has hitherto been used especially as a signal generator. In most cases, this differential amplifier exhibits little change in the potential of the input signal during operation. However, during the operation of the input receiver, a large potential fluctuation of the input signal is often observed.

An NMOS transistor is usually mounted on a substrate having a basic doping of the p-type. Therefore, there is a region having a drain or source terminal doped with n-type conductivity and a channel having a gate terminal. Often the fourth terminal of the transistor is on the substrate below the channel,
This terminal is also called a bulk. This electrode (bulk terminal) has a control action like a gate. In general, the control action is not used and this (bulk terminal) electrode is connected to the same potential as the source electrode.

The substrate on which the NMOS transistors are mounted is usually connected to a fixed reference potential of the integrated circuit. If the transistor is not electrically isolated from other substrates of the integrated circuit, the bulk terminals are similarly connected to a reference potential. In order to avoid a control effect, the terminal of the source electrode must likewise be connected to a reference potential, corresponding to the above-described embodiment. If the input signal of the differential amplifier connected to the gate terminal of the input transistor shows a relatively high potential change, the gate electrode and the source electrode of the transistor connected to the current source of the differential amplifier A similarly enhanced potential difference is seen as a result of the capacitive coupling between. Then, since the bulk terminal is connected to the fixed reference potential, the potential difference between the bulk terminal and the source terminal increases. This effect is also called a bulk source effect (body effect). This bulk-source action changes the threshold voltage of the transistor. This has a detrimental effect on the switching characteristics of the differential amplifier, for example, due to transient changes in the characteristics of the input transistors.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide the following circuit device having a differential amplifier. That is, an object is to provide a circuit device in which the disadvantageous switching characteristics of the differential amplifier described above are reduced.

[0008]

This object is achieved by a semiconductor circuit having the features of claim 1. Advantageous embodiments are set out in the dependent claims.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor circuit has a differential amplifier in the form of the aforementioned basic circuit. At least one NMOS
An input transistor of the type is mounted on a p-conducting well, which is also located on a p-conducting substrate. A region having a drain terminal or a source terminal, respectively, and a channel between the two regions are arranged in a well. The well, which is electrically insulated from the substrate, has a well terminal, which is connected to the source terminal. This ensures that the potential at the bulk terminal is the same as the potential at the source terminal.
This prevents bulk source effects.

In the basic circuit of the differential amplifier, since the source terminal of the input transistor is connected to the current source, the source terminal is not connected to a fixed reference potential of the integrated circuit. In contrast, the substrate of an integrated circuit is usually connected to a reference potential. Therefore, it is necessary to electrically insulate the relevant input transistor, together with its bulk terminal, from the substrate. Thus, the bulk terminal of the transistor can be connected to the source terminal.

The present invention is suitable for any semiconductor circuit in which a differential amplifier is used. NMOS transistors separated from the substrate in this manner can generally be used to advantage in circuits where large potential variations are seen at the source terminals of the transistors. This circuit also includes a differential amplifier used as an input receiver as described above. Even if the potential fluctuates greatly at the input signal terminal, no bulk source effect occurs, and as a result, the switching characteristics of the differential amplifier are not adversely affected.

[0012]

FIG. 1 shows the basic circuit of a differential amplifier 10, which comprises input transistors T1 and T2, a current source 3
0 and the load element 20 in the form of a current mirror. The load element 20 of the differential amplifier 10 is connected to the internal supply potential V1, and the current source 30 is connected to the reference potential GND of the integrated circuit. The input signal 1 of the differential amplifier 10 is applied to the gate terminal of the input transistor T1, and the reference potential 2 is applied to the gate terminal of the input transistor T2. The terminal of the output signal 4 of the differential amplifier 10 is connected here between the load element 20 and the transistor T1.

FIG. 2 is a sectional view of the transistor T1 or T2 used in FIG. Shown is an NMOS transistor, which is mounted on a p-type substrate Sp. The regions n1 and n2 are connected to the drain terminal D or the source terminal D of the transistor. A gate terminal G is attached above the channel nk. Regions n1 and n2 are of n conductivity type. The channel nk forms a so-called inversion layer. Further, the substrate S
p has one terminal, which in this embodiment corresponds to the bulk terminal of the transistor. The substrate Sp is connected to a fixed reference potential GND of the integrated circuit, in particular to avoid parasitic currents flowing through the conductive pn junction.

If the input signal 1 shows a large potential change during operation in FIG. 1, the connection point K also receives a relatively large potential change. The latter potential fluctuation is caused by capacitive coupling between the gate electrode and the source electrode of the input transistor T1. Since the bulk terminal B of the input transistor T1 is connected to the fixed reference potential GND, a voltage _UBS is seen between the bulk terminal B and the source terminal. This voltage is 0 or more. The above-described bulk-source action occurs due to the potential difference between the bulk terminal and the source terminal.

FIG. 3 shows a differential amplifier 10, which in its basic structure corresponds to the differential amplifier of FIG. On the other hand, the bulk terminals of the transistors T1 and T2 are connected to their respective source terminals.

FIG. 4 is a sectional view of the transistor T1 or T2 used in FIG. This NM
Here, the OS type transistor is not directly mounted on the substrate Sp, but is disposed in a p-conductivity type well Wp, and the well Wp is disposed on the substrate Sp.
The well Wp is electrically insulated from the substrate Sp by the insulating layer I. This insulating layer I is of n conductivity type, and an internal supply potential V1 is applied. With this, NMO
The bulk terminal B of the S-type transistor is connected to the substrate Sp of the integrated circuit.
From the substrate terminal SA. The substrate Sp is still connected to a fixed reference potential GND. Well terminal B is connected to source terminal S to ensure that the potential of well Wp is the same as the potential at source terminal S of the transistor. This effectively prevents bulk source effects.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic structure of a differential amplifier.

FIG. 2 is a cross-sectional view of the NMOS input transistor of FIG.

FIG. 3 is a diagram showing a structure of a differential amplifier having separated input transistors.

FIG. 4 is a cross-sectional view of the separated NMOS transistor of FIG.

[Explanation of symbols]

 Reference Signs List 1 input signal 2 reference potential 4 output signal 10 differential amplifier 20 load element 30 current source GND reference potential G gate terminal S source terminal D drain terminal B bulk terminal nk channel Wp well I insulating layer SA substrate terminal

Claims (3)

[Claims] 1. Two input transistors (T1, T1)
2) One current source (30) and one load element (2
0), wherein at least one of the input transistors (T1, T2) is of an NMOS type and a p-type well (p) of a p-type substrate (Sp). Wp), a first region (n1) having a drain terminal (D) and a second region (n2) having a source terminal (S) are disposed in the well (Wp). The well (Wp) has one well terminal (B) and is electrically insulated from the substrate (Sp), and the well terminal (B) is connected to the source terminal (S). Integrated semiconductor circuit. 2. The substrate (Sp) has one substrate terminal (S).
A), and the substrate terminal (SA) has a fixed reference potential (G
2. The integrated semiconductor circuit according to claim 1, wherein the integrated semiconductor circuit is connected to a terminal for ND). 3. The differential amplifier (10) is included in a circuit device of an input receiver of an integrated circuit, and a gate terminal (G) of one input transistor (T1).
3. The integrated semiconductor circuit according to claim 1, wherein the terminal is connected to a terminal for an input signal (1) of an input receiver.