JP2000353670A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device, comprising a formation method for a gate oxide film which is an affected by ion implantation conditions before forming a gate oxide film. SOLUTION: A first ion implantation process, where an ion is implanted to provide a p-well 12 and n-well 13 on a silicon substrate 2, and a second ion implantation process, where implantation ions 14 and 15 are implanted to control the threshold voltage of an FET of each well are executed, while a silicon surface is exposed in the surface of element forming regions 18 and 19. So, the change in silicon oxidation speed caused by a process before formation of the silicon oxide film 5 is suppressed, forming a gate insulating film comprising a silicon oxide film 5 having a stable film thickness and breakdown strength characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device including a plurality of field effect transistors (hereinafter, referred to as FETs), and more particularly to a method for forming a gate insulating film of an FET.

[0002]

2. Description of the Related Art In a method of manufacturing a semiconductor device, an FET
It is one of the important factors to use an ion implantation method to form a well in which elements such as the above are formed and to adjust an impurity concentration of a channel region for controlling a threshold voltage of an FET.

Conventionally, when using the ion implantation method,
Heavy metal contamination in ion implanter or CMOS
Etc., different thresholds and polarities of F on the silicon substrate.
Due to organic matter attachment from a resist used to locally ion-implant impurities when forming ET,
In order to prevent deterioration of electrical characteristics such as withstand voltage characteristics of the gate oxide film of the FET, ion implantation is performed through the sacrificial oxide film, and then the sacrificial oxide film is removed, and the silicon surface is oxidized again to form a gate oxide film. Was common.

Japanese Patent Application Laid-Open No. 10-303423 discloses an example of a method for manufacturing a semiconductor device using this sacrificial oxide film.

FIG. 4 is a sectional view in the order of steps for explaining a main part of a conventional method for manufacturing a semiconductor device using a sacrificial oxide film.

Referring to FIG. 4, an element formation region 41 defined by an element isolation oxide film 401 on a silicon substrate 402 is formed.
8, 419, a sacrificial oxide film 420 is formed on the surface.
(B)), a p-well 412 and an n-well 413 are formed, and if necessary, a p-well 412 and an n-well 413 are formed.
Threshold voltage control ion implantation is performed for each (FIG. 4
(C), (d)), the sacrificial oxide film 420 is removed (FIG. 4 (e)), and the silicon oxide film 4 serving as a gate insulating film is removed.
A method is adopted in which a gate electrode 406 is formed and a gate electrode 406 is formed to form an FET.

In the conventional method of manufacturing a semiconductor device using a sacrificial oxide film, the sacrificial oxide film 420 is removed after the ion implantation is completed (FIG. 4E), so that the ions introduced simultaneously with the impurity to be ion implanted are removed. It is possible to simultaneously remove heavy metals from the implanter and organic substances attached from the resist which are likely to be generated when ions are locally implanted into the silicon substrate 402 using the resists 416 and 417.
That is, it is possible to prevent deterioration of electrical characteristics such as the withstand voltage of the gate insulating film of T.

[0008]

However, in the conventional method of manufacturing a semiconductor device in which ions are implanted through the sacrificial oxide film 420, the silicon oxide film 40 is removed after the sacrificial oxide film is removed.
The oxidation rate when oxidizing the silicon surface to form the silicon oxide film 5 (FIG. 4 (f)) changes depending on the type of impurity to be ion-implanted and the amount of implantation.
Has brought a new problem that it is difficult to obtain.

More specifically, as shown in FIG. 5 (circles and triangles in FIG. 5), under a constant oxidizing condition, the oxide film thickness increases as the implantation amount increases with the same ion implantation species, and the oxide film thickness becomes larger than that of boron. Also, when arsenic is implanted, the oxide film thickness is larger. Furthermore, the implantation dose dependence of the oxide film thickness differs between boron and arsenic, and arsenic is much more dependent than boron.

Usually, an N-channel FET (hereinafter referred to as an N-type FET)
ET), boron and indium are ion-implanted species for threshold voltage control, and arsenic and phosphorus are ion-implanted species for threshold voltage control of P-channel FETs (hereinafter referred to as P-type FETs). FEs with different threshold voltages
Since the formation of T is controlled by changing these ion implantation amounts, the conventional method of manufacturing a semiconductor device in which ions are implanted through the sacrificial oxide film 420 requires a gate insulating film having a stable film thickness. This is a very serious problem, especially when forming an extremely thin gate insulating film required in recent miniaturized FETs.

[0011] As shown in FIG.
As the amount of ion implantation for controlling the threshold voltage increases, a new problem that the withstand voltage characteristic of the silicon oxide film 405 which is a gate insulating film formed thereafter deteriorates also arises.

The deterioration of the film thickness controllability and the breakdown voltage of the silicon oxide film 405 is caused by the fact that oxygen constituting the sacrificial oxide film 420 is introduced into the element formation regions 418 and 419 by a knock-on effect at the time of ion implantation. Is considered to be a major cause. (Hereinafter, the oxygen introduced into the silicon substrate by the knock-on effect is referred to as “knocked oxygen.”) In a conventional gate insulating film made of a silicon oxide film having a thickness of more than 2.5 nm, the knocked oxygen is formed. The thickness of the oxide film formed without the involvement of the knocked oxygen is small (usually less than 4%) relative to the thickness of the oxide film, and the oxide film formation rate is considered to be related to the knocked oxygen. The fluctuation and the influence on the breakdown voltage characteristics of the oxide film were small and did not cause any problem. However, when the thickness of the gate insulating film is smaller than 2.5 nm, the thickness of the oxide film formed by the involvement of the knocked oxygen is the thickness of the oxide film formed without the involvement of the knocked oxygen. And the influence on the thickness of the gate insulating film and the withstand voltage characteristics is becoming remarkable.

On the other hand, the deterioration of electric characteristics such as the withstand voltage characteristic of the gate insulating film of the FET due to the contamination by the heavy metal in the ion implantation apparatus or the adhesion of the organic substance from the resist, which has conventionally been a problem at the time of the ion implantation, is caused by the ion implantation. In recent years, it has become a non-problem due to improvements in the method, the process using a resist, and the cleaning process.

A main object of the present invention is to provide a method of manufacturing a semiconductor device having a method of forming a gate insulating film which is not affected by ion implantation conditions before forming a gate insulating film in consideration of the above. is there.

[0015]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a plurality of FETs, wherein an element forming region for forming an FET is formed on one main surface of a semiconductor substrate by element isolation. An element isolation step of selectively defining an insulating film, an impurity doping step of introducing a desired impurity into the element formation region by ion implantation, and a gate insulating film forming step of forming a gate insulating film of the FET. The gate insulating film forming step is performed in a state where only the impurity introduced by the impurity doping step exists in at least the element forming region.

In another method of manufacturing a semiconductor device according to the present invention, an insulating film on a surface of an element forming region selectively defined by an element isolating insulating film on one main surface of a semiconductor substrate is removed. A first substrate surface exposing step of exposing a surface of the semiconductor substrate in the region; an impurity doping step; and a gate insulating film forming step.
In the substrate surface exposing step, the semiconductor substrate surface in the element formation region is exposed, and the gate insulating film forming step is performed after the impurity doping step.

According to another method of manufacturing a semiconductor device of the present invention, there are provided a first substrate surface exposing step, a first sacrificial film forming step of forming a first thin film containing no oxygen as a constituent element, A doping step, a second substrate surface exposing step of exposing the semiconductor substrate surface in the element formation region by removing the first thin film, and a gate insulating film forming step,
The first sacrificial film forming step is performed in a state where the semiconductor substrate surface in the element formation region is exposed in the first substrate surface exposing step,
The impurity doping step is performed through the first thin film, and the gate insulating film forming step is performed after the second substrate surface exposing step.

Further, in another method of manufacturing a semiconductor device according to the present invention, there are provided a first substrate surface exposing step, a second sacrificial film forming step for forming a second thin film, an impurity doping step, A third substrate surface exposing step of exposing the semiconductor substrate surface in the element formation region by removing the thin film, a silicon film depositing step of depositing a silicon film to a desired thickness, and a gate insulating film forming step The second thin film forming step is performed in a state where the semiconductor substrate surface in the element forming region is exposed in the first substrate surface exposing step, the impurity doping step is performed through the second thin film, and the silicon film depositing step is performed. Is performed in a state where the semiconductor substrate surface in the element forming region is exposed in the third substrate surface exposing step, and the gate insulating film forming step includes a process of oxidizing all of the silicon film deposited in the silicon film depositing step. Than it is.

At this time, in the impurity doping step, a first ion implantation step of performing ion implantation for forming a well on one main surface of the semiconductor substrate and an ion implantation for controlling a threshold voltage of the FET are performed. It can be a second ion implantation step or a first ion implantation step and a second ion implantation step.

In the case where the semiconductor substrate is at least a silicon substrate or an SOI substrate, the second thin film formed in the second sacrificial film forming step may be a silicon oxide film formed by oxidizing the surface of the element formation region. good.

The silicon film deposited in the silicon film deposition step is preferably any one of an epitaxially grown silicon film, a polysilicon film, and an amorphous silicon film. The gate insulating film can have a desired thickness. Specifically, when the thickness of the desired gate insulating film is tox, the thickness tsi of the silicon film to be deposited is (tox
/ 4) <tsi <(tox / 3).

Further, the first thin film formed in the first sacrificial film forming step includes a silicon nitride film, a silicon carbide (SiC) film, a boron nitride (BN) film, a polysilicon film or an amorphous silicon film. Either one or a laminated film of these can be used. Since the first thin film does not contain oxygen as a component, a gate insulating film can be formed without depositing a silicon film after the second substrate surface exposing step.

As the high dielectric constant film, a tantalum oxide film, a titanium oxide film, a bismuth-strontium-tantalum oxide film (BST film), and an alumina film can be used.

According to the method of manufacturing a semiconductor device of the present invention,
For example, when the impurity doping step is performed by removing the insulating film in the element formation region in the first substrate surface exposing step, even if the silicon substrate is oxidized to form a gate oxide film, knocking is performed in the oxidized silicon substrate. Since the gate oxide film is formed by thermal oxidation without containing the oxygen atoms,
Stable oxide film thickness controllability and gate oxide film breakdown voltage are obtained.

Alternatively, the second thin film formed in the second sacrificial film forming step includes oxygen as a constituent element like a silicon oxide film on the element forming region, and the impurity introducing step is performed through the second thin film. Is performed, the third after ion implantation
In the substrate surface exposing step, the second thin film in the element formation region is removed, a silicon film is deposited, and the silicon film is entirely oxidized to form a gate insulating film. Since the gate oxide film is formed without knocked oxygen atoms, stable oxide film thickness controllability and gate oxide film breakdown voltage can be obtained. Also,
As a result of oxidizing the entire silicon film, a short circuit problem between elements can be suppressed.

The method of manufacturing a semiconductor device according to the present invention is particularly effective in a semiconductor device having a gate oxide film thinner than 2.5 nm, in which the effect of an oxide film involving knocked oxygen atoms in a silicon substrate to be oxidized becomes visible. The change in the oxidation rate due to the process before oxidation during thermal oxidation for forming the gate insulating film is suppressed, and a gate insulating film having stable film thickness and breakdown voltage characteristics can be obtained.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 to 3 are denoted by the same reference numerals as much as possible, and the description will be simplified.

First, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described.

FIGS. 1A to 1E are cross-sectional views in the order of steps for explaining main parts of a method of manufacturing a semiconductor device according to the present embodiment.

Referring to FIG. 1, in the method of manufacturing a semiconductor device according to the present embodiment, first, in a first substrate surface exposing step, an element selectively formed on one main surface of a silicon substrate 2 by an element isolation insulating film 1 is formed. A resist 16 serving as an ion implantation mask is applied in a state where the silicon surface is exposed on the surfaces of the formation regions 18 and 19, and a portion of the resist serving as the p-well 12 is removed and opened to perform a first ion implantation step. p well 1
An impurity (for example, boron (B)) for forming layer 2 is ion-implanted. Subsequently, a second ion implantation process corresponding to the N-type FET is performed to directly implant the implanted ions 14 (for example, boron (B)) for controlling the threshold voltage of the N-type FET.
The impurity is implanted into the well 12 to form the threshold voltage controlling impurity layer 3 (FIG. 1B).

Next, after removing the resist 16, the resist 17 is removed.
Is applied, the resist 17 in the part to be the n-well 13 is removed and opened, and the first ion implantation step is performed again, and the impurity (for example, phosphorus (P)) for forming the n-well 13 is ion-implanted. Subsequently, a second ion implantation step corresponding to the P-type FET is performed to implant the implantation ions 15 (for example, arsenic (As)) for controlling the threshold voltage of the P-type FET directly into the n-well 13. Threshold voltage control impurity layer 4
Is formed (FIG. 1C).

Next, an activation heat treatment for removing the resist 17 for the ion implantation mask and activating the impurities of the p-well 12, the n-well 13, and the impurity layers 3 and 4 for controlling the threshold voltage is performed at 900 ° C. by lamp annealing. , 30 seconds.

The activation heat treatment activates impurities, but is not limited to the above conditions as long as the conditions do not change the impurity distribution. (In particular,
For example, in the case of lamp annealing, 600 ° C. to 1100 ° C.,
In the case of furnace annealing, a combination of temperature and time in the range of 400 ° C. to 900 ° C. for 5 minutes to 120 minutes in a nitrogen atmosphere is preferable. Next, after a silicon oxide film 5 serving as a gate insulating film is formed by thermal oxidation in a gate insulating film forming step (FIG. 1D), the gate electrodes 6 and 7 are formed.
And diffusion layer regions 8, 9, 1 serving as source / drain regions
FETs are formed by forming 0 and 11 respectively (FIG. 1E).

After this, a well-known contact hole opening, wiring process, and the like are continued, but the description is omitted because it is not directly related to the present invention. (The same applies to the other embodiments.) In the manufacturing method of the present embodiment, the first ions are exposed while the silicon substrate is exposed on the surfaces of the element formation regions 18 and 19 of the p-well 12 and the n-well 13. Since the implantation step and the second ion implantation step are performed, oxygen atoms are not knocked on the element formation regions 18 and 19, and the element formation regions 18 and 19 are not knocked on.
Thermal oxidation can be performed in a state where the knocked oxygen atoms are not included in the silicon oxide film 19 to form the silicon oxide film 5 serving as a gate insulating film.

Next, a method of manufacturing the semiconductor device according to the second embodiment of the present invention will be described.

2A to 2F are cross-sectional views in the order of steps for explaining main parts of the method of manufacturing the semiconductor device according to the present embodiment.

Referring to FIG. 2, in the method of manufacturing a semiconductor device according to the present embodiment, first, in the first substrate surface exposing step, the element selectively formed on one main surface of the silicon substrate 12 by the element isolation insulating film 1 is formed. A first sacrificial film forming step is performed by exposing the silicon surface on the surfaces of the formation regions 18 and 19, and a silicon nitride film 20 which is a first thin film containing no oxygen in the constituent elements
Is formed on the entire surface (FIG. 2A).

Next, a resist 16 serving as an ion implantation mask
Is applied to remove the resist in the portion that will become the p-well 12.
An opening is formed and a first ion implantation step is performed.
(For example, boron (B)) is ion-implanted. Subsequently, a second ion implantation process corresponding to the N-type FET is performed, and implanted ions 14 for controlling the threshold voltage of the N-type FET are directly implanted into the p-well 12, thereby forming a threshold voltage controlling impurity layer. 3 is formed (FIG. 2B).

Next, the resist 16 is removed and the resist 17 is removed.
Is applied, the resist 17 in the portion to be the n-well 13 is removed and opened, and the first ion implantation step is performed again, and the impurity (for example, phosphorus (P)) forming the n-well 13 is ion-implanted. Subsequently, a second ion implantation process corresponding to the P-type FET is performed, and implanted ions 15 for controlling the threshold voltage of the P-type FET are directly implanted into the n-well 13 to thereby form a threshold voltage controlling impurity layer. 4 is formed (FIG. 2C).

Next, the resist 17 for the ion implantation mask is removed, and an activation heat treatment for activating the respective impurities of the p-well 12, the n-well 13, and the impurity layers 3 and 4 for controlling the threshold voltage is first performed. It is carried out under the same conditions as in the embodiment.

Next, in a second substrate surface exposing step, the silicon nitride film 20 is removed to expose the silicon surfaces of the element forming regions 18 and 19 (FIG. 2D), and in a gate insulating film forming step by thermal oxidation. After a silicon oxide film 5 serving as a gate insulating film is formed (FIG. 2E), diffusion layers 8, 9, 10, and 11 serving as gate electrodes 6, 7 and source / drain regions are formed, respectively (FIG. 2 (f)), an FET is formed.

In the manufacturing method of this embodiment, the first ion implantation step and the second ion implantation step are performed through the silicon nitride film 20, so that the nitrogen atoms are knocked on the element forming regions 18 and 19. When the silicon oxide film 5 serving as a gate insulating film is formed by thermal oxidation, the effect of the knocked nitrogen atoms on the oxide film thickness is small.
In other words, in the manufacturing method according to the present embodiment, the second ion implantation step is performed in a state where the surfaces of the element forming regions 18 and 19 are covered with the first thin film containing no oxygen in the components. Since oxygen is not contained in the elements knocked into the formation regions 18 and 19, the effect of reducing the variation in the gate insulating film thickness when forming the gate insulating film is achieved.

In the description of this embodiment, the silicon nitride film 20 has been described as an example of the first thin film. However, a SiC film containing no oxygen, a BN film, a polysilicon film,
The same effect can be obtained by using an amorphous silicon film or the like as the first thin film.

Next, a method of manufacturing the semiconductor device according to the third embodiment of the present invention will be described.

FIGS. 3A to 3F are cross-sectional views in the order of steps for explaining main parts of the method of manufacturing the semiconductor device according to the present embodiment.

Referring to FIG. 3, in the method of manufacturing a semiconductor device according to the present embodiment, first, in a first substrate surface exposing step, an element selectively formed on one main surface of silicon substrate 2 by element isolation insulating film 1 is formed. A second sacrificial film forming step is performed by exposing the silicon surface on the surfaces of the formation regions 18 and 19, and a silicon oxide film 30 as a second thin film is formed on the surfaces of the element formation regions 18 and 19 by thermal oxidation. (FIG. 3A).

Next, a resist 16 serving as an ion implantation mask
Is applied to remove the resist in the portion that will become the p-well 12.
An opening is formed and a first ion implantation step is performed.
(For example, boron (B)) is ion-implanted. Subsequently, a second ion implantation process corresponding to the N-type FET is performed, and implanted ions 14 for controlling the threshold voltage of the N-type FET are directly implanted into the p-well 12, thereby forming a threshold voltage controlling impurity layer. 3 (FIG. 3B).

Next, the resist 16 is removed and the resist 17 is removed.
Is applied, the resist 17 in the part to be the n-well 13 is removed and opened, and the first ion implantation step is performed again, and the impurity (for example, phosphorus (P)) for forming the n-well 13 is ion-implanted. Subsequently, a second ion implantation process corresponding to the P-type FET is performed, and implanted ions 15 for controlling the threshold voltage of the P-type FET are directly implanted into the n-well 13 to thereby form a threshold voltage controlling impurity layer. 4 is formed (FIG. 3C).

Next, the resist 17 for the ion implantation mask is removed, and activation heat treatment for activating the respective impurities of the p-well 12, the n-well 13, and the threshold voltage controlling impurity layers 3 and 4 is also performed in the first step. The operation is performed under the same conditions as in the embodiment.

Next, after the silicon oxide film 30 is removed in the second substrate surface exposing step, a silicon film depositing step is performed with the silicon surfaces exposed on the surfaces of the element forming regions 18 and 19 to perform the silicon film 31. Is deposited by epitaxial growth to a desired thickness (FIG. 3 (d)), and in the gate insulating film forming step, the silicon oxide film 32 which becomes the gate insulating film by oxidizing all the silicon film 31 deposited by the epitaxial growth by thermal oxidation. It is formed (FIG. 3E). Thereafter, gate electrodes 6, 7 and diffusion layer regions 8, 9, 10, 11 serving as source / drain regions are respectively formed (FIG. 3 (f)), and an FET is formed.

[0051] Incidentally, the silicon film deposited in the silicon film deposition process, the thickness of the silicon oxide film 32 formed in the gate insulating film formation step after the t _ox, the thickness t _si is t _ox / Deposition is performed so that 4 <t _si <t _ox / 3.

In the manufacturing method according to the present invention, the epitaxially grown silicon film 31 is formed in the element forming regions 18 and 19.
To remove oxygen atoms from a region to be oxidized to form a gate insulating film. Furthermore, as a result of oxidizing the entire silicon film 31 epitaxially grown, an effect of suppressing a short circuit between elements, which is likely to occur when the selectivity of silicon growth on the silicon substrate and the silicon oxide film is not sufficiently obtained. Is obtained. Further, even if a polysilicon film or an amorphous silicon film is used in place of the epitaxially grown silicon film 31, the same effect can be obtained because the polysilicon film or the amorphous silicon film is also entirely oxidized.

In the description of each of the above embodiments,
A first ion implantation step of implanting an impurity for forming a well, which is an impurity doping step, and a second ion implantation step of implanting an impurity for controlling a threshold voltage of the FET are performed on the p-well 12, Although the description has been given of the case where the process is continuously performed in each of the n-wells 13, the resist process is performed again after the first ion implantation process, and the second ion for implanting impurities for controlling the threshold voltage is ion-implanted. The opening in the injection step may be defined separately.

Next, the effect of the method of manufacturing a semiconductor device according to the present invention will be specifically described.

FIGS. 5 and 6 respectively show a semiconductor device according to the present invention.
N-type FET and P-type FET were manufactured using the manufacturing method of
Gate oxide film thickness and breakdown voltage near the silicon substrate surface
Dependence on impurity concentration for threshold voltage control in the vicinity
FIG. The specific condition is the threshold voltage of N-type FET.
Boron and accelerated ion species for controlled ion implantation conditions
The energy is 30 keV, and the threshold voltage
1 × 10¹²cm ^-2~ 5 × 10¹³cm^-2, Injection angle
Is performed at 7 degrees to control the threshold voltage of the P-type FET.
In the implantation conditions, the implantation ion species is arsenic and the acceleration energy is 1
00 keV, dose for threshold voltage control is 1 × 1
0¹²cm^-2~ 3 × 10¹³cm^-2At an injection angle of 7 degrees
No impurities after dry oxidation at 800 ° C
A 1.5 nm oxide film is formed on a silicon substrate
A gate oxide film was formed under the conditions. In the figure, boron is injected
The result when arsenic is implanted is indicated by ▲, and the result when arsenic is implanted is indicated by ●.
Indicated.

In one embodiment of the conventional method shown for comparison, a thermal oxide film having a thickness of 20 nm is used as a sacrificial oxide film, and the ion implantation conditions and the gate oxide film forming conditions are the same as those of the present invention described above. The conditions are the same as in the case of the manufacturing method. Incidentally, in the example of the conventional method, the results are indicated by Δ and ○, respectively, corresponding to the implanted ion species of boron and arsenic.

Referring to FIG. 5, when the method of manufacturing a semiconductor device according to the present invention is used, as shown by ● and ▲, the change in oxidation rate due to the type of impurity ions to be implanted and the amount of implantation is suppressed, and the gate oxide film is formed. Occasionally, an oxide film having a remarkably stable film thickness can be obtained.

Referring to FIG. 6, as shown by ● and ▲, the knocking of oxygen from the sacrificial oxide film into the silicon substrate is suppressed, so that the withstand voltage of the gate oxide film is significantly improved. I understand.

That is, according to the method of manufacturing a semiconductor device of the present invention, when a silicon oxide film is formed by, for example, thermally oxidizing a silicon substrate as a gate insulating film, the knocked oxygen atoms are oxidized in the silicon substrate. Since the thermal oxidation is performed in a state where it is not included, a change in the oxidation rate due to the process before the oxidation during the thermal oxidation is suppressed, and an effect of obtaining a stable oxide film thickness and a stable breakdown voltage characteristic of the oxide film is brought about.

The effect of the present invention is that the thinner the gate oxide film (specifically, about 2.5 nm or less), the more the knocked oxygen formed by the knocked oxygen The proportion occupied by the gate oxide film formed without involvement becomes large, and appears remarkably.

For example, when the thickness of the gate oxide film becomes 2.5 nm or less, the impurity concentration for controlling the threshold voltage is usually 5 ×.
When the impurity ions for controlling the threshold voltage are implanted through the conventional sacrificial oxide film up to the concentration of 10 ¹⁷ cm ^-3, the oxide film formed due to the knocked oxygen increases by 0%. 0.1 nm or more, which accounts for as much as 4% or more of the total thickness of the gate oxide film, and the electrical characteristics of the FET become more apparent.

In the above embodiments, a silicon oxide film formed by thermal oxidation has been described as an example of a gate insulating film. However, a silicon oxynitride film and a silicon oxide film are formed on the silicon substrate side as a gate insulating film. The same effect is obtained when a laminated structure of a formed high dielectric constant film and a silicon oxide film and a laminated structure of a high dielectric constant film and a silicon oxynitride film in which a silicon oxynitride film is formed on a silicon substrate side are used.

Examples of the high dielectric constant film include, but are not limited to, a tantalum oxide film, a titanium oxide film, a bismuth-strontium-tantalum oxide film, and an alumina film.

It should be noted that the present invention is not limited to the above embodiments, and it is obvious that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[0065]

As described above, according to the method of manufacturing a semiconductor device of the present invention, for example, when a silicon oxide film is formed by thermally oxidizing a silicon substrate as a gate insulating film, the oxidation in the silicon substrate is prevented. Thermal oxidation is performed in a state that does not include knocked oxygen atoms in the region to be oxidized, so that a change in the oxidation rate due to the process before oxidation during thermal oxidation is suppressed, and a stable oxide film thickness and withstand voltage characteristics of the oxide film are obtained. The effect is brought. In particular, as a gate insulating film,
When using a thin silicon oxide film of 2.5 nm or less,
The effect becomes remarkable.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a main part of a method for manufacturing a semiconductor device according to a first embodiment of the present invention in order of steps.

FIG. 2 is a cross-sectional view illustrating a main part of a method of manufacturing a semiconductor device according to a second embodiment of the present invention in order of steps.

FIG. 3 is a cross-sectional view illustrating a main part of a method for manufacturing a semiconductor device according to a third embodiment of the present invention in order of process.

FIG. 4 is a cross-sectional view in a process order for describing a main part of a conventional method for manufacturing a semiconductor device using a sacrificial oxide film.

FIG. 5 is a diagram showing a relationship between a gate oxide film thickness and a threshold voltage controlling impurity concentration. In the drawing, results obtained by the manufacturing method of the present invention are indicated by ● and ▲, and results obtained by the conventional manufacturing method using the sacrificial oxide film of FIG. 4 are indicated by △ and Δ.

FIG. 6 is a diagram showing a relationship between a withstand voltage of a gate oxide film and an impurity concentration for controlling a threshold voltage. In the drawing, results obtained by the manufacturing method of the present invention are indicated by ● and ▲, and results obtained by the conventional manufacturing method using the sacrificial oxide film of FIG. 4 are indicated by △ and Δ.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Element isolation insulating film 2,402 Silicon substrate 3,4,403,404 Threshold voltage control impurity layer 5,30,32,405 Silicon oxide film 6,7,406,407 Gate electrode 8,9,10, REFERENCE SIGNS LIST 11 diffusion layer region 12, 412 p-well 13, 413 n-well 14, 15, 414, 415 implanted ions 16, 17, 416, 417 resist 18, 19 device formation region 20 silicon nitride film 31 silicon film 401 device isolation oxide film 420 Sacrificial oxide film

Claims (13)

[Claims] A plurality of field effect transistors (hereinafter referred to as F
A method for manufacturing a semiconductor device including: an element isolation region for selectively defining an element formation region for forming the FET on one main surface of a semiconductor substrate by an element isolation insulating film; A gate insulating film forming step of forming a gate insulating film of the FET; and a gate insulating film forming step of forming a gate insulating film of the FET. A method for manufacturing a semiconductor device, wherein the method is performed in a state where only impurities introduced by a process are present. 2. A method for manufacturing a semiconductor device including a plurality of FETs, comprising removing an insulating film on a surface of an element forming region selectively defined by an element isolation insulating film on one main surface of a semiconductor substrate. A first substrate surface exposing step of exposing a semiconductor substrate surface in an element forming region, an impurity doping step of introducing a desired impurity into the element forming region by ion implantation, and a gate insulating film for forming a gate insulating film of the FET Forming at least the impurity doping step, wherein the impurity doping step is performed in a state where the semiconductor substrate surface in the element formation region is exposed in the first substrate surface exposing step. A method for manufacturing a semiconductor device, which is performed after a step. 3. A method of manufacturing a semiconductor device including a plurality of FETs, the method comprising removing an insulating film on a surface of an element forming region selectively defined by an element isolation insulating film on one main surface of a semiconductor substrate. A first substrate surface exposing step of exposing a semiconductor substrate surface in a formation region, a first sacrificial film forming step of forming a first thin film containing no oxygen as a component, and a step of adding a desired impurity to the element formation region. An impurity doping step introduced by ion implantation, and a second step of removing the first thin film and exposing the semiconductor substrate surface in the element formation region.
At least a substrate surface exposing step, and a gate insulating film forming step of forming a gate insulating film, wherein the first sacrificial film forming step is a step of exposing the semiconductor substrate in the element formation region in the first substrate surface exposing step. Conduct with the surface exposed,
The method of manufacturing a semiconductor device according to claim 1, wherein the impurity doping step is performed via the first thin film, and the gate insulating film forming step is performed after the second substrate surface exposing step. 4. The method according to claim 3, wherein the first thin film is any one of a silicon nitride film, a silicon carbide (SiC) film, a boron nitride (BN) film, a polysilicon film, an amorphous silicon film, or a laminated film thereof. The manufacturing method of the semiconductor device described in the above. 5. A method for manufacturing a semiconductor device including a plurality of FETs, the method comprising removing an insulating film on a surface of an element formation region selectively defined by an element isolation insulating film on one main surface of a semiconductor substrate. A first substrate surface exposing step for exposing a semiconductor substrate surface in an element forming region, a second sacrificial film forming step for forming a second thin film, and an impurity for introducing a desired impurity into the element forming region by ion implantation. A doping step, a third substrate surface exposing step of removing the second thin film to expose the semiconductor substrate surface in the element formation region, and a silicon film depositing step of depositing a silicon film to a desired thickness. A gate insulating film forming step of forming a gate insulating film, wherein the second sacrificial film forming step includes
The step of exposing the substrate surface is performed in a state where the surface of the semiconductor substrate in the element formation region is exposed in the substrate surface exposing step. The impurity doping step is performed through the second thin film. The method is performed in a state where the semiconductor substrate surface in the element forming region is exposed in the substrate surface exposing step, and the gate insulating film forming step includes a process of oxidizing all the silicon film deposited in the silicon film depositing step. A method for manufacturing a semiconductor device. 6. The method according to claim 5, wherein the semiconductor substrate is a silicon substrate or an SOI substrate, and the second thin film is a silicon oxide film formed by oxidizing the surface of the element formation region. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the silicon film deposited in the silicon film deposition step is any one of an epitaxially grown silicon film, a polysilicon film, and an amorphous silicon film. 8. A desired thickness of the silicon film deposited in the silicon film deposition step is a thickness that becomes a gate insulating film having a desired thickness when the silicon film is entirely oxidized. A method for manufacturing a semiconductor device according to claim 1. 9. The method according to claim 1, wherein the thickness of the gate insulating film is 2.5 nm or less. 10. A gate insulating film comprising a silicon oxynitride film (SiON film), a laminated film of a silicon oxide film and a high dielectric constant film laminated thereon, or a silicon oxynitride film and a high dielectric film laminated thereon. 2. The film according to claim 1, which is one of laminated films of a refractive index film.
9. The method for manufacturing a semiconductor device according to any one of claims 8 to 8. 11. An impurity doping step in which a first ion implantation for forming a well on one main surface of a semiconductor substrate is performed.
11. The method of manufacturing a semiconductor device according to claim 1, wherein the method is any one of the ion implantation step of (a) and the second ion implantation step of performing ion implantation for controlling a threshold voltage of the FET. 12. 12. An impurity doping step in which a first ion implantation for forming a well on one main surface of a semiconductor substrate is performed.
11. The method of manufacturing a semiconductor device according to claim 1, further comprising a second ion implantation step of performing an ion implantation step of controlling the threshold voltage of the FET and an ion implantation step of controlling the threshold voltage of the FET. 13. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes both an N-channel FET and a P-channel FET.