JP2000353144A - Control of register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a register controlling method allowed to be applied also to a case that an operating system itself executes the configuration of a PCI device and capable of evading dependency upon a PCI device connected to a secondary PCI bus. SOLUTION: In the case of checking a base address register resource request condition for PCI device configuration, response data to the reading of a PCI device 4 connected to a secondary PCI bus 6 to a base address register space 8 are stored in a register space 18 and data written in the space 8 are traced in a register space 16. When the bus 6 is not driven, the data stored in the space 16 are masked by the data stored in the space 18 and the masked data are outputted, so that mask processing based on software is made unnecessary and dependency upon the PCI device connected to the bus 6 can be evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a register control method, and more particularly, to a register control method for controlling a register space when confirming a base address register resource requirement at the time of PCI device configuration.

[0002]

2. Description of the Related Art In a personal computer device equipped with a PCI device conforming to the PCI local bus specification 2.1, two conditions newly defined in a default class device power management specification are satisfied.
A PCI bridge having a function of emulating the configuration register space of the CI device is required. Note that the two conditions are a condition that an extended function register for controlling the two operation states of the normal operation state and the power management state at a device driver level is implemented, and a condition that the address space used by the device is used in the power management state. Is not responded to even if an access cycle occurs.

FIG. 14 shows an example of a general register trace system, in which a P bus connected to a secondary PCI bus is used.
FIG. 10 is a block diagram of a personal computer device using a PCI bridge having a register space to emulate a configuration register space and a base address register space having the same configuration as a CI device.
When the register configuration of the base address register space 8 of the PCI device 4 is as shown in the register configuration diagram of FIG. 15, the register space 1500 inside the PCI bridge 1003 of FIG. 14 is the same as the register configuration diagram of FIG. Bit configuration, and the CPU 1001 sends the PCI device 1
Even if the data written to the register in the base address register space 1008 of the 004 is stored in the register in the register space 1500 of the PCI bridge 1003, the data of the read-only bit is not changed.

For this reason, when the CPU 1001 reads the internal registers of the base address register space 1008 of the PCI device 1004 while the secondary PCI bus 1006 is not operating, the data stored in the registers in the register space 1500 of the PCI bridge 1003 is read. Even if the data is output to the primary PCI bus 1005 as it is, the data stored in the base address register space 1008 of the PCI device 1004 can be emulated. FIG.
Now, in order to avoid the problem in FIG. 14, the base address register space 1008 of the PCI device 1004
Register space 1016 for emulating
All the bits are writable as shown in FIG.

[0005] In order to prevent rewriting of the read-only bit portion when data is written to the internal register of the base address register space 1008 of the PCI device 1004, mask processing of the read-only bit is performed by software according to the procedure shown in the flowchart of FIG. It is a method of performing. In FIG. 18, AM (RN) is AND mask data for masking the read-only bit information in the address area and the read-only bit information in the address space indicator area, and OM (RN) is AND.
This is OR mask information for adding read-only bit information of the indicator area of the address space area lost in the mask processing.

FIG. 19 is a flowchart showing a mask information detection sequence for mask processing at the time of data writing performed at the time of confirming resource requirement conditions in the base address register space 1008 of the PCI device 1004. In FIG. 19, RN is the base address register space 10
08, the register number of the register in the register 08, NM is a merge inhibit flag in the 64-bit address space address space indicator area, BAR (RN) is the register read data of the register number RN in the base address register space 1008, and AM (RN) is the AND mask data. Array, OM (R
N) is an OR mask data array, A0 is bit 0 data of the base address register, and A2 is bit 2 data of the base address register.

Further, as an application example of the conventional register control method, the one disclosed in the following gazette is known. In the register control method disclosed in Japanese Patent Application Laid-Open No. Hei 10-161965, addresses are assigned to avoid discontinuity between two IO address spaces of a PCI device. In the register control method disclosed in Japanese Patent Application Laid-Open No. H10-301657, a PCI connected to a secondary PCI bus is used.
In the device, the clock supply inside the PCI device is turned on / off by setting the configuration register space.

In the register control method disclosed in Japanese Patent Laid-Open No. 10-334032, the device number of a PCI device can be changed by a device number setting register. In the register control method disclosed in Japanese Patent Application Laid-Open No. H11-53295, the PCI register is composed of three register spaces of a register space.

[0009]

The conventional register control method described above has the following problems. FIG.
In the case of 6, in order to emulate a base address register space in which read-only bits depending on an address resource used by the PCI device are implemented,
As shown in the flowchart of FIG. 18, in addition to writing the base address register address to the normal configuration address register and writing data to the configuration data register, the bus number determination and the device number determination are performed for other PCI devices. It is also required when writing the configuration register. Also, PC
When writing to the configuration register space of the I device 1004, it is necessary to determine the register number,
Further, when writing to the base address register space 1008, it is necessary to perform an AND mask process on the write data and an OR mask process on the write data. For this reason, BIO
It is necessary to change PCI device configuration software such as S. However, some operating systems perform unique configuration of PCI devices at startup, and such operating systems can perform mask processing by software. There is no problem. In the case of FIG. 14, in a device using a plurality of PCI devices having different configurations of the base address register space 1008, the PCI bridge also needs to use a PCI bridge that matches the configuration of the register space 1500 individually. There is a point.

In the register control method disclosed in the official gazette, particularly in the register control method disclosed in Japanese Patent Laid-Open No. 11-53295, it is assumed that the configuration register space of a PCI device connected to a secondary PCI bus is emulated. Then, after issuing the reset signal, the series EE
Because of loading data stored in PROM, PC
It is necessary to provide an EEPROM outside the I-bridge, which causes a problem of increasing the number of parts.

[0011] With respect to the reconfiguration function of the state logic circuit in the PCI bus interface logic by a user instruction, it is necessary to reconfigure the PCI bus interface logic.

The present invention has been made in view of the above problems, and is applicable to a case where the configuration of a PCI device is executed by an operating system itself, and a PCI device connected to a secondary PCI bus. It is an object of the present invention to provide a register control method capable of avoiding dependency on the register.

[0013]

In order to achieve the above object, according to the first aspect of the present invention, when checking a base address register resource requirement at the time of PCI device configuration, the invention is connected to a secondary PCI bus of a PCI bridge. The response data to the reading to the base address register space of the PCI device is stored in the first register space inside the PCI bridge, and the write data to the base address register space is stored in the PCI
Trace in the second register space inside the bridge, and when the secondary PCI bus is not operating, the data stored in the second register space is replaced with the data stored in the first register space for reading to the base address register space. It is configured to output after mask processing.

That is, when confirming the base address register resource requirements at the time of PCI device configuration, response data to the reading of the PCI device connected to the secondary PCI bus of the PCI bridge to the base address register space is stored in the PCI bridge. Store in the first register space.

At this time, write data to the base address register space is traced in the second register space inside the PCI bridge. Then, when the secondary PCI bus is not operating, the data stored in the second register space is stored in the first register space for reading to the base address register space without performing mask processing and merging processing by software. Is output after mask processing.

As an example of a method for writing data to the base address register space, the invention according to claim 2 is a register control method according to claim 1, wherein when the secondary PCI bus is not operated, When writing is performed on the base address register space, the host bridge generates a configuration write cycle for the base address register space on the primary PCI bus. That is, when the CPU writes to the base address register space while the secondary PCI bus is not operating, the host bridge generates a configuration write cycle for the base address register space on the primary PCI bus.

As one example of a technique for tracing write data to the base address register space in the second register space, the invention according to claim 3 is based on claim 2.
Wherein the PCI bridge responds to the occurrence of the configuration write cycle on the primary PCI bus and stores the write data in the second register space. That is, when a configuration write cycle occurs on the primary PCI bus, the PCI bridge stores write data in the second register space in response to the occurrence of the configuration write cycle.

According to a fourth aspect of the present invention, as an example of a method for reading data from the base address register space, in the register control method according to any one of the first to third aspects, the base address is controlled by the CPU. When data is read from the register space, the host bridge generates a configuration write cycle for the base address register space on the primary PCI bus. That is, when the CPU reads data from the base address register space, the host bridge generates a configuration write cycle for the base address register space on the primary PCI bus.

As an example of a method for performing the mask processing,
According to a fifth aspect of the present invention, in the register control method according to the fourth aspect, the PCI bridge responds to the occurrence of a configuration write cycle in the primary PCI bus, and stores data stored in the second register space;
The configuration is such that mask processing is performed on the stored data stored in the first register space, and the obtained result is output to the primary PCI bus. That is, when a configuration write cycle occurs on the primary PCI bus, the PCI bridge responds to the occurrence of the configuration write cycle and stores the data stored in the second register space and the data stored in the first register space. Mask processing with the stored data, and outputs the obtained result to the primary PCI bus.

At this time, as an example of a method for handling the response data output to the primary PCI bus, the invention according to claim 6 is the register control method according to claim 5, wherein the host bridge is configured such that the PCI bridge is a primary PCI bus. Is output as read data to the CPU. That is, when the PCI bridge outputs response data to the primary PCI bus, the host bridge outputs the response data to the CPU as read data.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an application example of a register control method according to an embodiment of the present invention.

Referring to FIG. 1, a CPU 1, a primary PCI bus 5 connected to the CPU 1 via the host bridge 2, a PCI bridge 3 connecting the primary PCI bus 5 and the secondary PCI bus 6, and a PCI device 4 And are included. The PCI device 4 includes an address latch 33, a register selection circuit 38, a configuration register space 7, a base address register space 8, and a configuration register space 9. The address latch 33 holds the address of the bus cycle generated on the secondary PCI bus 6.

The register selection circuit 38 determines a selection signal 39 for the configuration register space 7, a selection signal 40 for the base address register space 8, and a selection signal 41 for the configuration register space 9 based on the register number of the address 42 held by the address latch. Is output. The configuration register space 7 is a register space of register numbers 00H to 0FH of the type 0 configuration register space defined in the PCI local bus specification 2.1. The base address register space 8 is a PC
Register numbers 10H to 2 in the type 0 configuration register space defined in I local bus specification 2.1
7H register space.

The configuration register space 9 includes:
This is a register space of register numbers 28H to 7FH in the type 0 configuration register space defined in the PCI local bus specification 2.1. The PCI bridge 3 includes register spaces 16, 18 to 20, a mask processing circuit 17, a primary bus IF circuit 21, a secondary bus IF circuit 22, a primary PCI bus control circuit 23, a secondary PCI bus control circuit 24, and a register space selection circuit. 15 are provided.

The register space 16 as the second register space according to the present invention stores write data to the base address register space 8 of the PCI device 4. Register space 18 as second register space according to the present invention
Stores base address register resource data. The register space 19 emulates the configuration register space 7 of the PCI device 4. The register space 20 stores the configuration register space 9
To emulate

The mask processing circuit 17 includes a register space 16
And a mask process is performed based on the data stored in the register space 18. The primary bus IF circuit 21 is provided with the AD of the primary PCI bus 5.
Interface with the bus. Secondary bus IF circuit 2
2 interfaces the secondary PCI bus 6 with the AD bus.

The primary PCI bus control circuit 23 includes a primary PC
Outputs a strobe signal 29 for storing a response to the PCI bus cycle of the I bus 5 and read data of the configuration register read cycle generated by the host bridge 2, and storing write data of the configuration register write cycle. Is output.

The secondary PCI bus control circuit 24 includes a secondary PC
A PCI bus cycle of the I bus 6 is generated. The register space selection circuit 15 includes an address latch 43 for holding an address of a configuration register read cycle and a configuration write cycle generated on the primary PCI bus 5 by the host bridge 2, and an address 35 held by the address latch 43. From the bus number of the secondary PCI bus 6 and the configuration register number 25, the selection signal 28 of the register space 19 and the register space 2
A selection signal 27 of 0 and a selection signal 26 of the register space 16 are generated.

Here, the base address register space 8 inside the PCI device 4, the register spaces 16, 18 inside the PCI bridge 3, and the mask processing circuit 17 will be described in detail. FIG. 2 shows the base address register space 8
3 is shown by a block diagram, and FIG. 3 shows a register configuration of the base address register space 8 by a register configuration diagram.

In FIG. 2, the address resources of the PCI device 4 use two addresses of a 16-byte address space and a 1 MB memory address space, and according to the mounting conditions of the base address register of the PCI local bus specification 2.1. A 16-byte IO address space is implemented in register number 10H, and a read-only bit is implemented so that register number 14H indicates 1 MB of memory address space. Therefore, the base address register space 8 includes a register 81 with a register number 10H, a register 82 with a register number 14H, a decoder 80, and a selector 83.

The decoder 80 is connected to the PCI device 4 shown in FIG.
The register number is decoded from the register number bus 34 held by the internal address latch 33, and the register number 10 is decoded.
An H decode signal 88 and a register number 14H decode signal 89 are output. The selector 83 has the register number 10
Register 81 when H decode signal 88 is active
Is selected, and when the decode signal 89 of the register number 14H is active, the data stored in the register 82 is selected. When both of the decode signals 88 and 89 are inactive, 00000000H is output.

As shown in the register configuration diagram of FIG. 3, the register 81 is a 32-bit wide register, and has a 28-bit read / write portion of bits 31 to 4 and a 2-bit width 0 of bits 3 and 2. It comprises an address area composed of a fixed bit part and an IO address space indicator area composed of two fixed value bits of bit 1 and bit 0. Also, the register 82 stores the bit 31
An address area consisting of a 12-bit width read / write portion from bit 20 to bit 20 and a 16-bit fixed value 0 bit portion from bit 19 to bit 4, and bit 3 to bit 0
And a 4-bit memory address space indicator area.

The register numbers 18H to 24H are not mounted in the embodiment, and the selector 83 outputs 000000 as read data at the time of reading as an unused register.
It is configured to output 00H. FIG. 4 is a block diagram showing a configuration example of the register space 16. P
The register space 16 of the CI bridge 3 has a register number 1
0H register 101, register number 14H register 102, register number 18H register 103, register number 1CH register 104, register number 20H register 105, register number 24H register 10
6, the decoder 100 and the selector 107.

The decoder 100 has a configuration register number 25 stored in the address latch 43 of FIG.
And the selection signal 26 output from the register space selection circuit 15, the decode signal 108 of the register number 10H, the decode signal 109 of the register number 14H, the register number 1
8H decode signal 110, register number 1CH decode signal 111, register number 20H decode signal 112, and register number 24H decode signal 113
Is output.

The selector 107 selects the output of the register 101 when the decode signal 108 is active, selects the output of the register 102 when the decode signal 109 is active, and selects the output of the register 103 when the decode signal 110 is active. When the decode signal 111 is active, the output of the register 104 is selected. When the decode signal 112 is active, the output of the register 105 is selected. When the decode signal 113 is active, the output of the register 106 is selected and output.

The data input to the registers 101 to 106 is
1 is connected to the write data bus 12 of FIG.
When the strobe signal 30 output from the CI bus control circuit 23 becomes active, the data on the write data bus 12 is stored in the register space 16.

FIG. 5 is a block diagram showing a configuration example of the register space 18. The register space 18 has a register number 10H to which the read data bus 13 of FIG.
Register 121, register number 14H register 12
2, register 123 with register number 18H, register 124 with register number 1CH, register 125 with register number 20H, register 126 with register number 24H, decoder 120, load enable circuit 127 for register 121, load enable circuit 12 for register 122
8, load enable circuit 129 for register 123, load enable circuit 130 for register 124, load enable circuit 131 for register 125, register 126
The load enable circuit 132 and the selector 145 are provided.

The decoder 120 has a configuration register number 25 stored in the address latch 43 of FIG.
The register number is decoded from the selection signal 26 output from the register space selection circuit 15 and the decode signal 139 of the register number 10H, the decode signal 140 of the register number 14H, and the decode signal 141 of the register number 18H.
And a decode signal 142 of register number 1CH, a decode signal 143 of register number 20H, and a decode signal 144 of register number 24H. Selector 14
5 outputs the data stored in the register 121 to the data bus 45 and outputs 000b to the 3-bit mask control signal 46 when the decode signal 139 output from the decoder 120 is active.

When the decode signal 140 is active,
The data stored in the register 122 is output to the data bus 45, and the bit 0, bit 1, and bit 2 of the data stored in the register 121 are output to the mask control signal 46 from the least significant bit side. When the decode signal 141 is active, the data stored in the register 123 is transferred to the data bus 45.
And the bit 0, bit 1 of the data stored in the register 122 from the least significant bit side to the mask control signal 46.
And bit 2 are output.

When the decode signal 142 is active,
The data stored in the register 124 is output to the data bus 45, and the bit 0, bit 1, and bit 2 of the data stored in the register 123 are output to the mask control signal 46 from the least significant bit side. When the decode signal 143 is active, the data stored in the register 125 is transferred to the data bus 45.
And bit 0 and bit 1 of the data stored in the register 124 from the least significant bit side to the mask control signal 46.
And bit 2 are output. When the decode signal 144 is active, the data stored in the register 126 is output to the data bus 45, and the bit 0, bit 1, and bit 2 of the data stored in the register 125 are output to the mask control signal 46 from the least significant bit side. .

FIG. 6 is a block diagram showing a configuration example of the mask processing circuit 17. The mask processing circuit 17
An ND processing circuit 150 and a merge processing circuit 151 are provided. The AND processing circuit 150 inputs the output signal 44 of the register space 16 and the data bus 45 of the register space 18 and outputs a logical product for each bit.

The merge processing circuit 151 derives the PC data from the lower 4-bit data 152 of the output data of the AND processing circuit 150, the lower 4-bit data of the data bus 45 of the register space 18, and the mask control signal 46 of the register space 18.
Merges the address space indicator part of the base address register specified in the I local bus specification 2.1. The output 153 of the AND processing circuit is the upper 28 bits of the result of the AND operation, and the output 154 is the output 4 bits of the merge processing circuit 151.

FIG. 7 is a circuit diagram showing an example of the configuration of the merge processing circuit 151. In the merge processing circuit 151,
By the four data selectors 165 to 168, the bit 0 output 178 of the lower 4 bit data 152 of the AND processing circuit 150, the bit 0 output 174 of the output data 45 of the register space 18, and the lower 4 bit data 152 of the AND processing circuit 150 are output. Bit 1 output 177, bit 1 output 173 of output data 45 of register space 18, bit 2 output 17 of lower 4-bit data 152 of AND processing circuit 150
6 and bit 2 output data 172 of the output data 45 of the register space 18, bit 3 output 175 of the lower 4-bit output data 152 of the AND processing circuit 150, and the register space 1
The bit 3 output 171 of the output data 45 of 8 is converted to the mask control signal 4 of 3 bits output from the register space 18.
A signal 16 obtained by processing at the NOR gate 169 three signals of a bit 0 signal 160, a bit 1 signal 161, and a signal obtained by logically inverting the bit 2 signal 162 at the inverter 183.
3 and bit 0 output 174 of register space 18 for switching.

The memory address space of the base address register of the PCI local bus specification 2.1 and the IO
Emulates read-only bits in the address space indicator section of the address space. When the signal 163 is 1, the outputs 178, 177, 17 of the AND processing circuit 150 are output.
6, 175 are output and if signal 163 is 0, bit 0 output 182 is the bit 0 output 17 of register space 18.
4 is selected and the bit 1 output 181 has the register space 1
The eight bit one output 173 is selected.

When the signal 163 is 0 and the signal 174 is 1, since the register is in the IO address space, the address space indicator section has only the lower 2 bits and the output 1
80 is the bit 2 output 176 of the AND processing circuit 150 is selected, and the output 179 is the bit 3 output of the AND processing circuit 150.
Output 175 is selected. When signal 163 is 0 and signal 17
When 4 is also 0, the register is in the memory address space, so the address space indicator section has the lower 4 bits, the output 180 selects the bit 2 output 172 of the register 18, and the output 179 selects the bit 3 output 1 of the register 18.
71 is selected.

Next, the operation of the circuit shown in FIG. 1 will be described. The base address register space 8 of the PCI device 4 and the register space 16 and the register space 18 of the PCI bridge 3 have a register space for six 32-bit registers. Reading and writing of the register will be described.

FIG. 8 is a timing chart showing a cycle that occurs on the primary PCI bus 5 in FIG. 1 when data is written to the register 81 in the base address register space 8 of the PCI device 4 shown in FIG.

In FIG. 8, a signal 400 is a CLK signal of the PCI local bus specification 2.1, a signal 401 is an AD bus signal of the PCI local bus specification 2.1, and a signal 407 is a P signal.
C / BE # signal of CI local bus specification 2.1, signal 4
02 is a FRAME # signal of the PCI local bus specification 2.1, and a signal 403 is an IR of the PCI local bus specification 2.1.
The DY # signal and the signal 404 correspond to PCI local bus specifications.
1 DEVSEL # signal, signal 405 is a TRDY # signal of the PCI local bus specification 2.1, and signal 406 is a PCI
This is a STOP # signal of the local bus specification 2.1.

The data 250 of the signal 401 is stored in the register 8 in the base address register space 8 of the PCI device 4.
1 and the data 255 is PC
The configuration register space 7 of the I device 4,
Alternatively, it is address data indicating an arbitrary register in the base address register space 8 or the configuration register space 9.

Data 252 is write data for register 81 in base address register space 8.
The data 256 is write data for the register at the address of the data 255. Data 251 of the signal 407 is command data indicating a configuration write cycle, data 253 and 257 are byte enable data, and data 254 of the configuration register number 25 is data of the register 81 in the base address register space 8. Register number. When the CPU 1 writes data to the register 81 in the base address register space 8, the host bridge 2 starts a configuration write cycle from T1 in FIG.

Since the PCI bridge 3 activates the address strobe signal 36 of the address latch 43 at T2, the address latch becomes transparent. At T3, the address strobe signal 36 becomes inactive, and the address latch 43 holds the address. When the latch enters the transparent state at T2, the register number 10H of the register 81 is output to the configuration register number 25, and the selection signal 26 of the register space 18 becomes active.

Actual data writing to the register 81 is P
After the CI device 4 generates a configuration write cycle on the secondary PCI bus 6 and does not complete until the cycle ends, the PCI device 4 activates the signals 404 and 406 at T4 and configures the host bridge 2. Request retry of the write cycle. After ending the cycle at T5, the host bridge 2 issues a configuration write cycle for the register 81 again at T6. PCI bridge 3
Since the configuration write cycle of the secondary PCI bus 6 has not been completed, the host bridge 2 is requested again to retry the configuration write cycle at T7.

After ending the cycle at T8, the host bridge 2 starts a configuration write cycle for the register 81 again at T9. Since the configuration write cycle of the secondary PCI bus 6 has been completed and the data writing to the register 81 has been completed, the signal 404 is activated at T10, the signal 405 is activated at T11, and the host bridge 2 completes the cycle normally. Request.

The PCI bridge 3 activates the strobe signal 30 at T12, and activates the strobe signal 3 at T13.
By making 0 inactive, the data of the write data bus 12 is stored in the register 101 of the register number 10H in the register space 16 shown in FIG. After the reset of the PCI bridge 3, when data is first written to the register 81 in the base address register space 8, FIG.
Register 12 shown in the block diagram of the register space 18 of FIG.
1 decode signal 133 of the load enable circuit 127
Becomes active at T13, and the host bridge 2
The cycle ends at the timing of 13. At T14, when the host bridge 2 generates a configuration write cycle for an arbitrary register, the address strobe signal 36 becomes active and the address latch 4
3 becomes transparent, the configuration register number 25 and the selection signal 26 change to a state corresponding to the address data 255 of the signal 401.

FIG. 9 is a timing chart showing a cycle that occurs on the secondary PCI bus 6 in FIG. 1 when data is written to the register 81 in the base address register space 8 of the PCI device 4 shown in FIG. . In FIG. 9, a signal 300 is a CLK signal of the PCI local bus specification 2.1, and a signal 301 is an AD bus signal of the PCI local bus specification 2.1. Signal 307
Is a C / BE # signal of the PCI local bus specification 2.1, and a signal 302 is a FRAME # signal of the PCI local bus specification 2.1.

The signal 303 is an IRDY # signal of the PCI local bus specification 2.1, and the signal 304 is a PCI local bus specification 2.1.
DEVSEL # signal of local bus specification 2.1.
The signal 305 is the TRD of the PCI local bus specification 2.1.
A Y # signal, and a signal 306 is a STOP # signal of the PCI local bus specification 2.1. Data 350 of the signal 301 is address data indicating the register 81 in the base address register space 8 of the PCI device 4,
The data 355 is stored in the configuration register space 7, the base address register space 8, or the configuration register space 9 of the PCI device 4.
Is the address data indicating the arbitrary register of FIG.

Data 252 is write data for register 81 in base address register space 8;
Data 356 is write data for the register at the address of data 355. Data 251 of signal 307
Is command data indicating a configuration write cycle, data 253 and 357 are byte enable data, and the configuration register number 3
The data 254 of 4 is the register number of the register 81 in the base address register space 8. PCI bridge 3
Starts a configuration write cycle from T1 in FIG.

Since the PCI device 4 activates the address strobe signal 37 of the address latch 33 at T2, the address latch becomes transparent. At T3, the address strobe signal 37 becomes inactive, and the address latch 33 holds the address. When the latch enters the transparent state at T2, the register number 10H of the register 81 is output to the register number bus 34, and the selection signal 40 of the base address register space 8 becomes active.

After activating the signal 304 at T4, the PCI device 4 responds to the cycle by activating the signal 305 at T5. The write data is stored in the register 81 by activating the strobe signal 90 at T6 and inactivating the strobe signal 90 at T7.

The PCI bridge 3 ends the cycle at the timing of T7. When the PCI bridge 4 generates a configuration write cycle for an arbitrary register at T8, the address strobe signal 37 becomes active and the address latch 33 becomes transparent, so that the register number bus 34 and the base address register space 8 The register space selection signal 40 changes to a state corresponding to the address data 255 of the signal 301.

FIG. 10 shows the register 8 in the base address register space 8 of the PCI device 4 of FIG. 1 shown in FIG.
The timing chart shows the cycle that occurs on the primary PCI bus 5 when data is read from the data bus 1. In FIG. 10, a signal 400 is a CLK signal, a signal 4
01 is an AD bus signal, signal 407 is a C / BE # signal, signal 402 is a FRAME # signal, and signal 403 is an IRDY #
The signal 404 is a DEVSEL # signal, the signal 405 is a TRDY # signal, and the signal 406 is a STOP # signal.

The data 250 of the signal 401 is stored in the register 8 in the base address register space 8 of the PCI device 4.
1 and the data 255 is PC
The configuration register space 7 of the I device 4,
Alternatively, it is address data indicating an arbitrary register in the base address register space 8 or the configuration register space 9. Data 260 is data stored in the register 81 in the base address register space 8, and data 262 of the signal 407 is command data indicating a configuration read cycle.

The data 253 and 257 are byte enable data, and have the configuration register number 2
The data 254 of 5 is the register number of the register 81 in the base address register space 8. When the CPU 1 reads data from the register 81 in the base address register space 8, the host bridge 2 starts a configuration read cycle at T1 in FIG. The PCI bridge 3 uses the address latch 43 at T2.
In order to activate the address strobe signal 36, the address latch is in a transparent state.

At T3, the address strobe signal 36 becomes inactive, and the address latch 43 holds the address. When the latch enters the transparent state at T2, the register number 10H of the register 81 is output to the configuration register number 25, and the selection signal 26 of the register space 18 becomes active. The actual reading of data from the register 81 is not completed until the PCI device 4 generates a configuration read cycle on the secondary PCI bus 6 and ends the cycle.
Activates signals 404 and 406 at T4,
It requests the host bridge 2 to retry the configuration read cycle.

After ending the cycle at T5, the host bridge 2 issues a configuration read cycle for the register 81 again at T6. PCI bridge 3
Requests the host bridge 2 to retry the configuration read / write cycle again at T7 because the configuration read cycle of the secondary PCI bus 6 has not been completed. After ending the cycle at T8, the host bridge 2 starts a configuration read cycle for the register 81 again at T9.

Since the configuration read cycle of the secondary PCI bus 6 has been completed, the signal 40
4 is made active, the signal 405 is made active at T11, requesting the host bridge 2 to end the cycle normally, and outputting the data of the read data bus 13 to the primary PCI bus 5. Further, the PCI bridge 3 activates the strobe signal 29 at T12, and inactivates the strobe signal 29 at T13. PCI bridge 3
Ends the data output of the read data bus 13 to the primary PCI bus 5.

At this time, the load enable circuit 1 of the register 121 shown in the block diagram of the register space 18 in FIG.
When the load enable signal 133 output from the bus 27 is active, the data of the bus 13 is stored in the register 121 of the register number 10H in the register space 18 at T13, and the load enable signal 133 becomes inactive. The host bridge 2 ends the cycle at the timing of T13. When the host bridge 2 generates a configuration access cycle for an arbitrary register at T14, the address strobe signal 36 becomes active and the address latch 43 becomes transparent at T15.
5 and the register space selection signal 26 of the register space 18 change to a state corresponding to the address data 255 of the signal 401.

FIG. 11 shows the register 8 in the base address register space 8 of the PCI device 4 of FIG. 1 shown in FIG.
1 is a timing chart showing a cycle occurring on the secondary PCI bus 6 in FIG. In FIG. 8, a signal 300 is a CLK signal,
1 is an AD bus signal, signal 307 is a C / BE # signal, signal 302 is a FRAME # signal, signal 303 is an IRDY # signal, signal 304 is a DEVSEL # signal, and signal 305 is T
The RDY # signal and the signal 306 are STOP # signals.

The data 350 of the signal 301 is stored in the register 8 in the base address register space 8 of the PCI device 4.
1 and the data 355 is PC data.
The configuration register space 7 of the I device 4,
Alternatively, it is address data indicating an arbitrary register in the base address register space 8 or the configuration register space 9. Data 260 is data stored in the register 81 in the base address register space 8, and data 356 is data stored in the register at the address specified by the data 355.

Data 262 of signal 307 is command data indicating a configuration read cycle, and data 251 is command data indicating a configuration write cycle. Data 253, 35
Reference numeral 7 denotes byte enable data, and data 254 of the configuration register number 42 is a register number of the register 81 in the base address register space 8. The PCI bridge 3 starts a configuration read cycle at T1 in FIG.

Since the PCI device 4 activates the address strobe signal 37 of the address latch 33 at T2, the address latch becomes transparent. At T3, the address strobe signal 37 becomes inactive, and the address latch 33 holds the address. When the latch enters the transparent state at T2, the register number 10H of the register 81 is output to the register number bus 34, and the selection signal 40 of the base address register space 8 becomes active.

The PCI device 4 activates the signal 304 at T4, activates the signal 305 at T5, responds to the cycle, and outputs the data stored in the register 81 onto the secondary PCI bus. The output of the read data of the register 81 ends at T6, and the PCI bridge 3 ends the cycle at T6. When the PCI bridge 3 generates a configuration write cycle for an arbitrary register at T8, the address strobe signal 3
7 becomes active and the address latch 33 becomes transparent, so that the address 42 and the register space selection signal 40 of the base address register space 8 change to a state corresponding to the data 255 of the signal 301.

FIG. 12 shows a case where data is read from the register 81 in the base address register space 8 of the PCI device 4 shown in FIG. 1 while the secondary PCI bus 6 is not operating. The operation inside the bridge 3 is shown by a timing chart. 12, a signal 400 is a CLK signal, a signal 401 is an AD bus signal, a signal 407 is a C / BE # signal, and a signal 402 is FRA.
The ME # signal and the signal 403 are the IRDY # signal and the signal 404.
Is a DEVSEL # signal, signal 405 is a TRDY # signal,
Signal 406 is a STOP # signal.

The data 250 of the signal 401 is stored in the register 8 in the base address register space 8 of the PCI device 4.
1 and the data 255 is PC
The configuration register space 7 of the I device 4,
Alternatively, it is address data indicating an arbitrary register in the base address register space 8 or the configuration register space 9. The data 350 is data stored in the register 101 of the register number 10H inside the register space 16, and the data 351 is data stored in the register 121 of the register number 10H inside the register space 18.

Data 450 is output data of the mask processing circuit 17, and data 262 of the signal 407 is command data indicating a configuration read cycle. The data 253 and 257 are byte enable data, and the data 254 of the configuration register number 25 is the register number 10H of the register 81 in the base address register space 8.

The CPU 1 sets the base address register space 8
When data is read from the register 81 in the host bridge 2, the host bridge 2 starts a configuration read cycle from T1 in FIG. PCI bridge 3
The address strobe signal 3 of the address latch 43 at T2
To activate 6, the address latch is in a transparent state. At T3, the address strobe signal 36 becomes inactive, and the address latch 43 holds the address. When the latch enters the transparent state at T2, the register number 10H of the register 81 is output to the configuration register number 25, and the selection signal 26 becomes active.

Here, the register 101 in the register space 16 and the register 121 in the register space 18 are selected, and the mask processing circuit 17 starts mask processing. The PCI bridge 3 activates the signal 404 at T4, activates the signal 405 at T5, and outputs the output 450 of the mask processing circuit 17 to the primary PCI bus 5. Further, the PCI bridge 3 makes the signal 405 inactive at T6, ends the data output to the primary PCI bus 5, and the host bridge 2 ends the cycle at the timing of T6.

When the host bridge 2 starts register access to the register at T7, the address strobe signal 36 becomes active, and the configuration register number 25 changes to a value corresponding to the address data 255. The register space 19 stores write data when writing from the CPU 1 to the configuration register space 7 of the PCI device 4 is performed.
Configuration register space 7 of CI device 4
Is read, the PCI device 4 becomes the secondary PC
The response data to be output to the I bus 6 is stored.

When the secondary PCI bus 6 is inactive, C
When the reading from the PU 1 to the configuration register space 7 of the PCI device 4 is performed, the data stored in the register space 19 is output to the primary PCI bus 5 so that the access to the configuration register space 7 of the PCI device 4 can be performed. Perform emulation. The register space 20 stores write data when writing from the CPU 1 to the configuration register space 9 of the PCI device 4 is performed, and when the CPU 1 reads from the configuration register space 9 of the PCI device 4, PCI device 4 is secondary PCI bus 6
To store the response data to be output.

When the secondary PCI bus 6 is inactive, C
When reading from the PU 1 to the configuration register space 9 of the PCI device 4 is performed, the data stored in the register space 20 is output to the primary PCI bus 5 so that access to the configuration register space 9 of the PCI device 4 can be performed. Perform emulation. The register space 16 stores write data when writing from the CPU 1 to the base address register space 8 of the PCI device 4 is performed.
When the base address register space 8 is read, the PCI device 4 stores the response data output to the secondary PCI bus 6.

In a personal computer using the PCI bus, when the power is turned on, the CPU 1, the host bridge 2, the PCI bridge 3, and the PCI device 4 are reset. Subsequently, the configuration of the PCI device is started, and after the detection of the PCI device, the resource requirement of each device is checked. At this time, as a first procedure, the register numbers 10H, 14H,
For each register of 18H, 1CH, 20H, 24H,
Writing of FFFFFFFFH is performed. For this reason,
As shown in the register configuration of FIG. 3, the inside of the base address register space 8 of the PCI device 4
FFFFFF1H, register 82 is FFF00000H
And the register space 16 inside the PCI bridge 3
Internal registers 101, 102, 103, 104, 10
FFFFFFFFH is stored in 5 and 106.

As a second procedure, reading of the internal registers of the base address register space 8 of the PCI device 4 is performed. At this time, as shown in the register configuration diagram of FIG. 4, when reading the register of the register number 10H, the CPU 1 stores the stored data FFFFFFF1H of the register 81.
Is read, and at the time of reading the register number 14H, the stored data FFF0000H of the register 82 is read. Also, register numbers 18H, 1CH, 20H, 2
At the time of reading 4H, 00000000H is read by the selector 83 shown in FIG. At this time, PC
Internal register 121 in register space 18 of I-bridge 3
Is FFFFFFF1H, and register 122 is FFF000
00H, register 123, register 124, register 1
25, the register 126 is set to 0000000000H.

As a third procedure, the CPU 1 sets the register 8
1. The address data is set in the register 82.
The read data of the register 81 is FFFFFFF1H
Since the 0th bit is set to 1, the address space of the register 81 must be arranged in the IO address space, and since the upper 28 bits are set to 1, 16 to 0 to FH are set. It is determined that an address space for bytes is necessary, resources are secured, and the start address is written to the register 81.

The read data of the register 82 is FFF0
Since the 0th bit is set to 0 at 0000H, the address space of the register 82 must be located in the memory address space, and since the upper 12 bits are set to 1, the address space from 0 to FFFFFH 1M
It is determined that an address space for bytes is necessary, resources are secured, and the start address is written to the register 82.

Further, data to be written to the register 81 is stored in the register 101 of the register space 16 inside the PCI bridge 3, and data to be written to the register 82 is stored in the register 102. At this time, if the write data to the register 81 is 0000FED0H and the write data to the register 82 is CBA00000H, the setting data of the register 81 after writing is 0000FED1H,
The setting data of the register 82 is CBA00000H, 0000FED0H is stored in the register 101 of the register space 16 inside the PCI bridge 3, and CBA0000H is stored in the register 102.

The operation in the case where the secondary PCI bus 6 becomes inactive in the above-described setting state will be described. When the secondary PCI bus 6 is inactive and the register number 10H of the base address register space 8 of the PCI device 4 is read, the selection signal 26 and the configuration register number 25 serve as output data of the register space 16. Data stored in register 101 0000FED
0H is selected, the stored data FFFFFFFF1H of the register 121 is selected as the output data of the register space 18, and the mask control signal 46 is 0 for all three bits. AND processing circuit 150 of mask processing circuit 17 shown in FIG.
Output 153 becomes 0000FEDH, and the output 152 becomes 0H.

The operation of the merge processing circuit 151 will be described. Since the bit 0 signal 160, the bit 1 signal 161, and the bit 2 signal 162 of the mask control signal 46 are all 0, the output signal 163 of the NOR gate 169 becomes 0, and the outputs of the selectors 165 and 166 are the output data of the register space 18. Bit 0 signal 174 and bit 1 signal 173 are selected. The outputs of the data selectors 167 and 168 are such that the bit 0 signal 174 of the output data of the register space 18 is 1
Therefore, the output of the OR gate 170 becomes 1, and the bit 2 signal 176 and the bit 3 signal 175 of the register space 16 are selected. Therefore, the output data of the mask processing circuit 17 is 0000FED1H, and the data stored in the register 81 of the PCI device 4 can be correctly reproduced.

In this embodiment, the mask processing circuit 17 is provided on the output side of the register space 16, but the mask processing circuit 17 can be provided on the input side of the register space 16 as shown in FIG. . That is, when data is written from the CPU 1 to the register in the base address register space 8 of the PCI device 4, the mask processing result is output from the register space 18 and the data of the write data bus 13 to the internal register of the register space 16. Is stored in

As described above, when confirming the base address register resource requirement at the time of PCI device configuration, the PCI connected to the secondary PCI bus 6
The response data to the reading of the base address register space 8 of the device 4 is stored in the register space 18, and the write data to the base address register space 8 is traced in the register space 16, and the secondary PC
When the I bus 6 is not operating, the data stored in the register space 16 is masked with the data stored in the register space 18 and output when reading into the base address register space 8, so that masking by software becomes unnecessary. , The dependency on the PCI device connected to the secondary PCI bus can be avoided.

[0090]

As described above, the present invention can be applied to the case where the configuration of the PCI device is performed by the operating system itself, so that mask processing by software at the time of writing the base address register is not required. The read data of the base address register at the time of confirming the resource requirement condition at the time of configuration of the PCI device is stored in the register,
Since the data stored in the register that traced the data written to the base address register when reading the base address register and the mask processing are performed, the secondary PCI
A register control method capable of avoiding dependence on a PCI device connected to a bus can be provided. According to the second aspect of the present invention, the configuration write cycle generated on the primary PCI bus by the host bridge can be used when data is written to the base address register space.

Further, according to the invention of claim 3,
The write data can be stored in the second register space in response to the occurrence of the configuration write cycle. Further, according to the invention of claim 4, it is possible to use a configuration write cycle generated on the primary PCI bus by the host bridge when data is read from the base address register space.

Furthermore, according to the invention of claim 5,
Mask processing is performed in response to the occurrence of the configuration write cycle, and the obtained result can be output to the primary PCI bus. Furthermore, according to the invention of claim 6, the response data output to the primary PCI bus can be output to the CPU as read data.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an application example of a register control method according to an embodiment.

FIG. 2 is a block diagram illustrating a configuration example of a base address register space.

FIG. 3 is a register configuration diagram showing a register configuration of a base address register space.

FIG. 4 is a block diagram illustrating a configuration example of a register space.

FIG. 5 is a block diagram illustrating a configuration example of a register space.

FIG. 6 is a block diagram illustrating a configuration example of a mask processing circuit.

FIG. 7 is a circuit diagram illustrating a configuration example of a merge processing circuit;

FIG. 8 is a timing chart showing a cycle occurring on the primary PCI bus.

FIG. 9 is a timing chart showing a cycle occurring on the secondary PCI bus.

FIG. 10 is a timing chart showing a cycle occurring on a primary PCI bus.

FIG. 11 is a timing chart showing a cycle occurring on the secondary PCI bus.

FIG. 12 is a timing chart showing an operation inside the PCI bridge.

FIG. 13 is a block diagram showing another application example of the register control method.

FIG. 14 is a block diagram showing an application example of a conventional register control method.

FIG. 15 is a register configuration diagram showing a register configuration of a base address register space.

FIG. 16 is a block diagram showing another application example of the conventional register control method.

FIG. 17 is a block diagram illustrating a configuration example of a register space.

FIG. 18 is a flowchart showing a procedure for masking a read-only bit.

FIG. 19 is a flowchart illustrating a mask information detection sequence for mask processing.

[Explanation of symbols]

 1 CPU 3 PCI bridge 4 PCI device 5 Primary PCI bus 6 Secondary PCI bus 7 Configuration register space 8 Base address register space 9 Configuration register space 12 Write data bus 13 Read data bus 15 Register space selection circuit 16 Register space 17 Mask Processing circuit 18 to 20 Register space 21 Primary bus IF circuit 22 Secondary bus IF circuit 23 Primary PCI bus control circuit 24 Secondary PCI bus control circuit 33 Address latch 38 Register selection circuit 43 Address latch 45 Data bus 80 Decoder 81, 82 Register 83 selector 100 decoder 101-106 register 107 selector 120 decoder 121-126 register 127-132 load enable circuit 145 select 0.99 the AND processing circuit 151 merge processing circuit 165 to 168 data selector 169 NOR gate 170 OR gates 183 inverter

Claims (6)

[Claims] When confirming a base address register resource requirement at the time of PCI device configuration, a PID connected to a secondary PCI bus of a PCI bridge is used.
Response data to the CI device for reading to the base address register space is stored in a first register space inside the PCI bridge, and write data for the base address register space is stored in a second register space inside the PCI bridge. Trace and, when the secondary PCI bus is not operating, mask the data stored in the second register space with the data stored in the first register space for reading to the base address register space and output the result. A register control method characterized by the above-mentioned. 2. The register control method according to claim 1, wherein when the secondary PCI bus is not operating, writing is performed from the CPU to the base address register space.
The host bridge executes the configuration write cycle for this base address register space by the primary PCI.
A register control method, wherein the register is generated on a bus. 3. The register control method according to claim 2, wherein the PCI bridge stores the write data in the second register space in response to an occurrence of a configuration write cycle on the primary PCI bus. A register control method characterized by the above-mentioned. 4. The register control method according to claim 1, wherein when the CPU reads out the base address register space, the configuration write for the base address register space is performed. A method according to claim 1, wherein said host bridge generates a cycle on said primary PCI bus. 5. The register control method according to claim 4, wherein said PCI bridge responds to the occurrence of a configuration write cycle in said primary PCI bus and stores said data stored in said second register space. And performing a masking process with the stored data stored in the first register space and outputting the obtained result to the primary PCI bus. 6. The register control method according to claim 5, wherein said host bridge outputs response data output from said PCI bridge to said primary PCI bus to said CPU as read data. Control method.