JP2000350439A - Boost circuit - Google Patents

Abstract

(57) [PROBLEMS] To easily optimize an output voltage and a current driving capability and reduce a circuit scale in a booster circuit having a plurality of booster cell groups. SOLUTION: A plurality of boosting cell groups P1 to P configured by at least one boosting cell for boosting and outputting an input voltage.
n, a booster circuit capable of changing each booster cell group P1 to Pn to a desired connection configuration in series, parallel, or series / parallel by providing the booster cell group switching means 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a booster circuit in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In recent years, in a nonvolatile semiconductor memory device, for example, a flash EEPROM, a booster circuit capable of supplying various high voltages at the time of writing / erasing and reading has been widely used.

This type of booster circuit can selectively supply a desired high voltage by switching the number of stages of booster cells, and greatly contributes to a single power supply operation of a nonvolatile semiconductor memory device.

As a booster circuit for internally boosting an external power supply voltage and selectively supplying a desired high voltage, for example, a charge circuit as shown in FIG. 16 disclosed in Japanese Patent Application Laid-Open No. Hei 10-304653 is disclosed. Pump type booster circuits are known.
Note that the charge pump type booster circuit in FIG. 16 is a positive booster circuit.

A conventional booster circuit, FIG. 16, will be described below. 1 is a charge pump means, 2 is an output terminal,
Reference numeral 3 denotes a clock generation unit, and reference numeral 4 denotes an output rectification unit.

The charge pump type booster circuit shown in FIG. 16 uses a charge pump means 1 comprising booster cell groups P1 to Pn connected in series and a clock supplied to each booster cell group P1 to Pn of the charge pump means. The clock generating means 3 generates an output rectifier for rectifying the output of the charge pump means.

A conventional charge pump type booster circuit receives booster clocks CLK1 to CLKn and receives booster cells P1 to Pn (in this case, at least one booster cell constituting charge pump means 1). One booster cell is called a booster cell group).
By switching the number of stages of the boosting cell groups P1 to Pn,
A voltage boosted from the power supply voltage Vdd is switched to a desired voltage, and the voltage Vpp is obtained from the output terminal 2.
The diodes Do1 to Don are connected in series, and the boosting clocks CLK1 to CLKn generated from the clock generating means 3 via the boosting capacitive elements C1 to Cn are supplied to the cathodes of the diodes D1 to Dn. Supplied. The output rectifying unit 4 is composed of rectifying diodes Do1 to Don and a capacitive element Co, and outputs of the respective boosting cell groups P1 to Pn are output to a common output terminal 2 via the rectifying diodes Do1 to Don and the capacitive element Co. It is connected to the. The clock generating means 3 supplies boosting clocks CLK1 to CLKn corresponding to the number of the boosting cell groups P1 to Pn, and the clocks CLK1 to CLKn are individually given to the boosting cell groups P1 to Pn. . Further, the boosting clocks CLK1 to CLK1 output from the clock generating means 3
Of the CLKn, odd-numbered clocks CLK1 and CLK3
.., And even-numbered clocks CLK2, CLK4,.
Is the same frequency and opposite phase relationship. When all clocks CLK1 to CLKn are at L level, G
The power supply voltage is set to the Vdd level when the H level is set to the ND level.

The operation of the above-structured booster circuit will be described below.

First, consider the case where all of the boosting clocks CLK1 to CLKn are output from the clock generating means 3.

First, the odd-numbered clocks CLK1, CL
K3... Are at L level, even-numbered clocks CLK2,
When CLK4... Is at the H level, a forward bias is applied to the diode D1, and the capacitive element C1 is charged. Therefore, the potential of the node N1 of the first-stage booster cell group P1 is equal to the voltage drop of the diode D1 from Vdd. (= Vd) minus (Vdd-Vd)
Value. Next, the odd-numbered clocks CLK1, CL
K3... Are at H level, even-numbered clocks CLK2,
When CLK4... Become L level, the potential of the node N1 is boosted by (Vdd-Vd) by Vdd to become a value of (2Vdd-Vd).

At this time, a forward bias is applied to the diode D2 of the next-stage booster cell group P2, and the capacitive element C2
Is charged, the potential of the node N2 is obtained by subtracting the voltage drop (= Vd) by the diode D2 from the potential of the node N1 of the previous booster cell group P1 (2Vdd-Vd) -Vd = 2 (Vdd- Vd)
Value. Subsequently, the odd-numbered clocks CLK1, C
LK3... Are at L level, even-numbered clock CLK
2, CLK4... Become H level, the potential of the node N2 is boosted from 2 (Vdd-Vd) by Vdd to (3Vdd-2Vd).

At this time, a forward bias is applied to the diode D3 of the next-stage booster cell group P3, and the capacitive element C3
Is charged, the potential of the node N3 is obtained by subtracting the voltage drop (= Vd) by the diode D3 from the potential of the node N2 of the preceding booster cell group P2 (3Vdd-2Vd) -Vd = 3 (Vdd- V
d).

Hereinafter, by repeating the same operation,
The voltage is boosted by the number of stages of each of the booster cell groups P1 to Pn, and the potential of the node Nn of the booster cell group Pn at the nth stage becomes n · (Vdd−Vd). And the final output voltage obtained at the output terminal 2
Vpp is a value of (n + 1) · (Vdd−Vd) because the output rectifier 4 holds the potential of the node Nn.

However, such a final output voltage Vpp =
When the output voltage Vpp is low, the transitional operation until the voltage reaches (n + 1) · (Vdd-Vd) is, first, the node N of the booster cell group P1.
1 supplies electric charge to Vpp via the diode Do1. When the potential Vpp of the output terminal 2 gradually increases, the operation of the diode Do1 stops because the diode Do1 becomes reverse biased.
Thereafter, charge is supplied from the node N2, which is boosted from the node N1, to Vpp via the diode Do2. Output terminal 2
When the potential Vpp of the diode Do2 gradually rises, the diode Do2 becomes reverse biased, and the operation stops.

The above operation is repeated, and the final output voltage Vpp of the output terminal 2 becomes a value of (n + 1) · (Vdd-Vd).

Here, for example, when a voltage of n · (Vdd−Vd) is required as an output voltage Vpp in a certain operation mode,
A clock control signal is supplied from a control circuit such as a microcomputer (not shown), and among the boosting clocks CLK1 to CLKn output from the clock generating means 3, the clock supplied to the boosting cell group Pn at the nth stage Only the output of CLKn is stopped. Then, the boosting operation in the boosting cell group Pn is stopped. However, the clock CLK1 is applied to each of the boosting cell groups P1 to P (n-1) at the preceding stage.
To CLK (n-1) are continuously supplied, the potential of the node N (n-1) of the (n-1) th step-up cell group P (n-1) is boosted.
(n-1) · (Vdd-Vd).

At this time, the output rectifier 4 composed of the rectifying diode Do (n-1) and the capacitive element Co causes the (n-1)
Since the potential of the node N (n-1) of the booster cell group P (n-1) at the stage is held, the final output voltage Vpp obtained at the output terminal 2 is obtained.
Is a value of n · (Vdd−Vd). In this case, the other rectifying diodes Do1 to Do (n-2) are reverse biased and do not operate.

As is apparent from the above operation, by sequentially stopping the clocks from the boosting clock having the larger clock number, the final output voltage obtained at the output terminal 2 is obtained.
The potential of Vpp will decrease.

That is, whether the boosting clocks CLK1 to CLKn supplied from the clock generating means 3 are supplied,
By controlling whether to stop, an output that is an integral multiple of (Vdd-Vd) can be arbitrarily obtained as the value of the output voltage Vpp.

[0020]

However, in the above-mentioned conventional configuration, only one kind of output voltage can be taken out at the same time, and the current driving capability cannot be changed according to the fluctuation of the current load. When several types of high voltages are required, another booster circuit must be prepared, and when a high current driving capability is required, such as in a read mode such as a flash EEPROM, the maximum current load is taken into consideration. In addition, since the current driving capability must be set, the area of the capacitive element increases, and in the operation mode with a small current load, the area is inefficiently used.

The present invention solves the above-mentioned conventional problems. It is possible to simultaneously supply several types of high voltages and change the current driving capability in accordance with the operation mode, and to reduce the cost by reducing the circuit scale. It is an object of the present invention to provide a highly reliable booster circuit capable of efficiently supplying a stable output voltage.

[0022]

To achieve this object, a booster circuit according to the present invention is configured as follows.

According to a first aspect of the present invention, there is provided a booster cell group comprising at least one booster cell for boosting and outputting an input voltage, and at least two booster cell groups in accordance with a control signal.
Boosting cell group switching means for switching the two boosting cell groups so as to be connected in any form of series, parallel or series-parallel, and rectifying means for half-wave rectifying and outputting the output of the boosting cell group as an input; Wherein the output of the rectifier is output to a common output terminal. With this configuration, the boosting cell group can be freely connected in any form of a series, parallel, or series-parallel combination, so that the current driving capability corresponding to the operation mode is realized and the last stage of the boosting cell group is realized. Output voltage can be supplied.

According to a second aspect of the present invention, there is provided a booster cell group comprising at least one booster cell for boosting an input voltage and outputting the boosted voltage, and at least two booster cells in accordance with a control signal.
Boosting cell group switching means for switching the two boosting cell groups so as to be connected in any form of series, parallel or series-parallel, and rectifying means for half-wave rectifying and outputting the output of the boosting cell group as an input; An output switching means for switching at least one of the outputs of the diode element to connect to at least one output terminal in response to an output switching control signal.
With this configuration, the same operation as the operation according to the first aspect can be achieved, and the outputs of the booster cells other than the last stage can be simultaneously supplied as the output voltage.

According to a third aspect of the present invention, there is provided the booster circuit according to any one of the first and second aspects, further comprising a voltage level detecting means for receiving at least one output voltage and detecting the voltage level. Adjusting the control signal for controlling the boosting cell group switching means in accordance with the detection level of the voltage level detecting means, and switching the boosting cell group to connect in series, parallel, or series-parallel. Circuit. According to this configuration, the same operation as the operation according to claim 1 or 2 can be achieved, and further, the control signal for controlling the boosting cell group switching unit by determining the voltage value of the output voltage is adjusted. By doing so, the connection of the booster cell group can be switched to a desired connection, so that the output voltage can be optimized.

According to a fourth aspect of the present invention, in the booster circuit according to any one of the first to second aspects, the current level detecting means for detecting a current level of a load current flowing from at least one output terminal is provided. Adjusting the control signal for controlling the boosting cell group switching means according to the detection level of the current level detecting means, and switching the boosting cell group to connect in series, parallel, or series-parallel. It is a booster circuit. With this configuration,
The same operation as the operation corresponding to claim 1 or 2 can be achieved, and further, by adjusting the control signal for controlling the boosting cell group switching means by determining the current value of the load current, Since the connection of the booster cell group can be switched to a desired connection, the current driving capability can be optimized.

According to a fifth aspect of the present invention, a plurality of booster cell groups each including at least one booster cell for boosting and outputting an input voltage, and each of the booster cell groups according to a phase control signal. A step-up circuit comprising: a phase variable clock generation unit that supplies a step-up clock while controlling a phase; and a rectification unit that receives an output of the step-up cell group as an input, and performs half-wave rectification and outputs. . With this configuration, since the phases of the boosting clocks are shifted independently of each other, noise generated by the boosting operation can be reduced.

The invention corresponding to claim 6 is based on claims 1-4.
The booster circuit according to any one of the preceding claims, further comprising: a phase variable clock generation unit that supplies a boosting clock while controlling a phase to each of the boosting cell groups according to a phase control signal. This is a step-up circuit. With this configuration, the same operation as the operation according to the first to fourth aspects can be achieved, and further, since the phases of the boosting clocks are shifted independently of each other, noise generated by the boosting operation can be reduced. .

According to a seventh aspect of the present invention, a plurality of booster cell groups each including at least one booster cell for boosting and outputting an input voltage and each of the booster cell groups according to a frequency control signal are provided. The booster circuit includes frequency variable clock generating means for supplying a boosting clock while controlling the frequency, and rectifying means for receiving the output of the boosting cell group as input and performing half-wave rectification and outputting. According to this configuration, the frequency of the boosting clock output from the frequency variable clock generating means can be controlled, and the frequency of the boosting clock can be changed independently of each other. Can be supplied, and the current driving capability of each of the boosting cell groups can be optimized. Further, by stopping the boosting clock, unnecessary boosting cell groups can be stopped according to the operation mode.

According to an eighth aspect of the present invention, in the booster circuit according to any one of the first to fourth aspects, a boosting clock is supplied to each of the boosting cell groups while controlling a frequency in accordance with a frequency control signal. A booster circuit comprising a variable frequency clock generator for supplying. With this configuration, the same operation as the operation according to the first to fourth aspects can be achieved, and the frequency of the boosting clock can be changed independently of each other. On the other hand, the boosting clock whose frequency is changed can be supplied, and the current driving capability of each of the boosting cell groups can be optimized. Further, by stopping the boosting clock, unnecessary boosting cell groups can be stopped according to the operation mode.

According to a ninth aspect of the present invention, a plurality of booster cell groups each including at least one booster cell for boosting and outputting an input voltage, and an amplitude is applied to each of the booster cell groups according to an amplitude control signal. A booster circuit comprising variable amplitude clock generating means for supplying a boosting clock while controlling, and rectifying means for receiving an output of the boosting cell group as input and performing half-wave rectification and outputting. According to this configuration, the same operation as the operation corresponding to the first to fourth aspects can be achieved, and further, the amplitude of the boosting clock output from the amplitude variable clock generating means can be controlled, and the boosting clock can be controlled. Since the amplitudes of the clocks can be changed independently of each other, it is possible to supply the boosted clocks with the changed amplitudes to the desired boosted cell group, and to optimize the current drive capability of each boosted cell group.

The invention for claim 10 is based on claims 1 to 4
The boosting circuit according to any one of the above, further comprising an amplitude variable clock generating means for supplying a boosting clock while controlling an amplitude to each of the boosting cell groups according to an amplitude control signal. It is a booster circuit. With this configuration, the same operation as the operation according to the first to fourth aspects can be achieved, and the amplitude of the boosting clock can be changed independently of each other. On the other hand, the boosting clock whose amplitude is changed can be supplied, and the current driving capability of each of the boosting cell groups can be optimized.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a booster circuit according to a first embodiment of the present invention, and portions corresponding to those of the conventional example shown in FIG. In FIG. 1, reference numeral 10 denotes a boosting cell group switching unit that switches the connection relationship of the boosting cell group by a control signal. Each boost cell group P1
To Pn are rectifier diodes Do1 to Don, respectively.
The output rectifier 4 is connected to the common output terminal 2 via the capacitor and the capacitive element Co in the same manner as in the conventional example shown in FIG.

A feature of the present embodiment is that a plurality of boosting cell groups P1 to Pn for boosting and outputting an input voltage include:
The booster cell groups P1 to Pn are connected as shown in the figure via booster cell group switching means 10 for switching the serially, parallel or series-parallel connection of the booster cell groups P1 to Pn. That is, the boosting cell group switching means 10 is driven by the control signal. With this configuration, the booster cell groups P1 to Pn can be freely connected in any form of a series, parallel, or series-parallel combination.

Specifically, as shown in FIG.
Two booster cell groups P1 to P3 are connected as shown in the figure via booster cell group changeover switches 14 and 15 controlled by control signals 12 and 13, and each booster cell group P1 to P3 is connected to each booster clock CLK1 to P3. Driven by CLK3. The output of each of the boosting cell groups P1 to P3 is a rectifying diode D
The point that the output rectification unit 4 is configured by being connected to the common output terminal 2 via the capacitive elements Co1 to Do3 and the capacitive element Co is similar to the case of the conventional example shown in FIG. The booster cell group changeover switches 14 and 15 constitute the booster cell group changeover means 10.

Each of the boosting cell groups P1 to P3 has the same configuration as each other, and as shown in FIG.
1, D12 and capacitive elements C11 and C12, which are driven by a boosting clock CLK supplied from a clock generating means (not shown) or an inverted signal thereof to transfer charges from the capacitive elements C11 to C12 and to transfer C12 to C12. The charge and the charge of the capacitive element C11 and the charge transfer from C12 to the output side are alternately performed, so that the input voltage is boosted and output. Here, the input voltage is set to the Vdd level of the power supply voltage, and the L and H levels of the boosting clock CLK are set to GND, respectively, as in the case of FIG.
Level and power supply voltage Vdd level, diodes D11, D1
Assuming that the voltage drop due to 2 is Vd, the boosted and output voltage has the minimum value and the maximum value of 2 (Vdd-Vd), respectively, according to the same operation principle as the charge pump means 1 of FIG. 16 which is a conventional example.
And (3Vdd-2Vd).

The boosting cell group changeover switch 14 connects the input to the boosting cell group P2 to the power supply voltage Vdd and the output node of the first-stage boosting cell group P1 according to the L and H levels of the control signal 12. Switch to N1. Similarly, the booster cell group changeover switch 15 connects the input to the booster cell group P3 to the power supply voltage Vdd and the node N2 on the output side of the second-stage booster cell group P2 according to the L and H levels of the control signal 13. Can be switched.

The operation of the booster circuit of the present embodiment configured as described above will be described below.

First, the same boosting clocks CLK1 to CLK3 are all supplied from a clock generating means (not shown), and the L and H of each of the boosting clocks CLK1 to CLK3 are supplied.
It is assumed that the levels are set to the GND level and the power supply voltage Vdd level, respectively. At this time, when both control signals 12 and 13 are set to L level from a control circuit such as a microcomputer (not shown), the booster cell groups P1 to P3 are connected in parallel as shown in FIG. As described in the conventional booster circuit and the above configuration,
The outputs of the first-stage booster cells P1 to P3 are held, and 3 (Vdd-Vd) is obtained as the output voltage Vpp level. When the control signals 12 and 13 are both set to H level, the booster cell groups P1 to P3 are all connected in series, the output of the third booster cell group P3 is held, and the output voltage Vpp level is set. 7
(Vdd-Vd) can also be obtained.

When the control signals 12 and 13 are set to L and H levels, respectively, the booster cell groups P1 and P2 are connected in parallel, and the booster cell groups P2 and P3 are connected in series.
The output of the second-stage booster cell group P3 is held, and the output voltage Vp
5 (Vdd-Vd) can be obtained as the p level.

Here, when the power supply voltage Vdd is set to 2.5 [V] and the voltage drop Vd by the diodes D11 and D12 in the booster cell group P in FIG. 3 is set to 0.5 [V], for example, the flash EE
In a read mode such as a PROM, the booster cell groups P1 to P3
By connecting in parallel, it is possible to supply 6 [V] as the output voltage Vpp while increasing the current driving capability without increasing the area of the capacitive element. In the write / erase mode requiring a high voltage, the booster cell group is used. By connecting all of P1 to P3 in series, a high voltage of 14 [V] can be supplied as the output voltage Vpp. In a certain operation mode, the high voltage 10 [V] can be supplied as the output voltage Vpp by connecting the boosting cell groups P1 and P2 in parallel and connecting the boosting cell groups P2 and P3 in series.

As described above, according to the first embodiment, by providing the boosting cell group switching means 10, the boosting cell group can be connected to a desired configuration, and the boosting cell group can be connected by a control signal according to the operation mode. Desired current driving capability and high voltage can be realized by one booster circuit.

In this embodiment, each booster cell group P1
Using diodes D11 and D12 as constituent elements of .about.Pn;
The diodes Do1 to Do are also used as constituent elements of the output rectifier 4.
Although n is used, a similar effect can be obtained by using a MOS transistor instead of these diodes.

Further, the booster cell group used in the present embodiment is constituted by a very basic charge pump type booster circuit, but instead of the charge pump type booster circuit, a threshold voltage canceling type or a complementary type is used. A similar effect can be obtained with the charge pump type booster circuit and the like.

In the specific example of this embodiment, the number of boosting cells R1, R2 constituting each boosting cell group P1 to P3 is two.
However, the same effect can be obtained even if the boosting cell group is composed of one or three or more boosting cells.

Further, in this embodiment, each boost cell group P
Although the numbers of the boosting cells constituting 1 to P3 are all equal, the same effect can be obtained even if they are not equal. In this case, the output of the booster cell group can be more flexibly adjusted to a desired voltage.

Although the rectifying diodes Do1 to Don are connected to each of the boosting cell groups P1 to Pn, the same effect can be obtained by connecting only the desired boosting cell group. However, in that case, the current driving capability cannot be increased or the type of output voltage that can be extracted decreases in a certain boosting cell group connection pattern, but the number of rectifying diodes can be reduced, thereby reducing the circuit scale. Is advantageous.

FIG. 4 is a block diagram showing a configuration of a booster circuit according to the second embodiment of the present invention. The same reference numerals are given to portions corresponding to those of the first embodiment shown in FIG. In FIG. 4, reference numeral 16 denotes an output switching control signal for switching the output of the output rectification unit 4, and reference numeral 17 denotes an output switching unit that switches the output of the output rectification unit 4 according to the output switching control signal 16 to make a new output.

The feature of the second embodiment is that each of the rectifier diodes Do1 to Don is responsive to the output control switching signal 16.
The output switching means 17 is provided for inputting nodes X1 to Xn, which are respectively connected to the outputs of the first and second capacitive elements Co1 to Con, and connecting the inputs to at least one output terminal Y1 to Ym. .

As a specific example, the configuration is as shown in FIG. 5, and portions corresponding to those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals. The features of this embodiment are:
As shown in FIG. 5, each node X1 to X3 and each output terminal Y1,
Whether Y2 is connected and the output terminals Y1 and Y2 are connected (ON state) according to the H / L level of the output switching control signal 16
(OFF state) is provided. The connection pattern between the nodes X1 to X3 and the respective output terminals Y1 and Y2 as shown in FIG.
Constitute output switching means 17. The other configuration is the same as that of the first embodiment shown in FIG. 2, and the detailed description is omitted here.

The operation of the booster circuit of the present embodiment configured as described above will be described below.

The same boosting clocks CLK1 to CLK3 are all supplied from clock generating means (not shown), and the L and H levels of the boosting clocks CLK1 to CLK3 are set to the GND level and the power supply voltage Vdd level, respectively. This point is the same as in the first embodiment.

In accordance with control signals 12 and 13 from a control circuit such as a microcomputer (not shown), the inputs of the booster cells P2 and P3 are at the Vdd level of the power supply voltage and the outputs of the booster cells P1 and P2. The point of switching to the nodes N1 and N2 is the same as in the first embodiment.

The feature of the second embodiment is that each control signal
The connection configuration of each of the booster cell groups P1 to P3 is changed in accordance with 12, 13 and the output switching control signal 16, and each of the output terminals Y1, Y2
Is that a plurality of desired output voltages can be obtained at the same time. For example, as shown in FIG.
13 are set to H level, each of the booster cell groups P1 to P3
Are all connected in series (three stages in one series),
When the output switching control signal 16 is set to L level, the output terminals Y1 and Y2 are separated, and the output of the booster cell group P2 of the second stage is held from the output terminal Y1, and the output voltage is 10
[V] (= 5 (Vdd-Vd)) is obtained, the output of the third-stage booster cell group P3 is held from the output terminal Y2, and the output voltage is 14 [V] (= 7 (Vdd-Vd-Vd). Vd)) is obtained. That is, a plurality of output voltages can be obtained simultaneously.

When the control signals 12 and 13 are set to L and H levels, respectively, the booster cell groups P1 and P2 are connected in parallel, and the booster cell groups P2 and P3 are connected in series.
At this time, if the output switching control signal 16 is set to L level,
Each output terminal Y1 and Y2 are separated, and from the output terminal Y1,
The outputs of the first-stage booster cell groups P1 and P2 are held, and 6 [V] (= 3 (Vdd-Vd)) is obtained as an output voltage. The second-stage booster cell group is output from the output terminal Y2. The output of P3 is held, and 10 [V] (= 5 (Vdd-Vd)) is obtained as the output voltage. At this time, a plurality of output voltages can be supplied at the same time. In particular, an output voltage with improved current driving capability can be supplied from the output terminal Y1.

Further, when the control signals 12 and 13 are both set to L level and the output switching control signal 16 is set to H level, the output terminals Y1 and Y2 are connected, and the booster cell groups P1 to P3 are connected to 3 levels.
By being connected in parallel, the output of the first-stage booster cell group P1 to P3 is held at each of the output terminals Y1 and Y2, and the output voltage is 6 [V] (= 3 (Vdd-Vd)). Is obtained. When the output switching control signal 16 is set to the H level, the output terminals Y1 and Y2 are connected, so that the first terminal shown in FIG.
The operation is the same as that of the embodiment.

Here, the above operations are summarized as shown in the operation diagram of FIG.

As described above, according to the second embodiment, by providing the boosting cell group switching means 10 and the output switching means 17, the boosting cell group is connected to a desired configuration, and a plurality of output voltages are simultaneously output. Can be supplied. That is, a plurality of high voltages can be supplied by one booster circuit while realizing a desired current driving capability according to the operation mode.

Further, at the time of low-voltage output, by connecting a booster cell group that is not working effectively to a booster cell group that outputs a low voltage in parallel, it is possible to increase a desired current driving capability. Since each booster cell group can be effectively used, the area is advantageous.

FIG. 7 is a block diagram showing the configuration of a booster circuit according to the third embodiment of the present invention. The same reference numerals are given to parts corresponding to those of the second embodiment shown in FIG.

The feature of the third embodiment is that the output terminal Y
A voltage level detecting means for inputting at least one of the signals 1 to Ym, detecting a voltage level of the input signal, and controlling the boosting cell group switching means according to the voltage level; It is.

As a specific example, there is a configuration as shown in FIG. 8, and portions corresponding to those in the second embodiment shown in FIG. 5 are denoted by the same reference numerals.

The feature of this embodiment is that the signal of the output terminal Y2 is input, the voltage level of the input signal is detected, and the control signals 12 and 13 are controlled in accordance with the voltage level. That is, a voltage level detecting means 19 for switching the group changeover switches 14 and 15 is provided. Other configurations are
Since this is the same as the second embodiment shown in FIG. 5, a detailed description is omitted here.

The operation of the booster circuit according to the present embodiment configured as described above will be described below.

The same boosting clocks CLK1 to CLK3 are all supplied from a clock generating means (not shown), and the L and H levels of the boosting clocks CLK1 to CLK3 are set to the GND level and the power supply voltage Vdd level, respectively. This point is the same as in the first and second embodiments.

In response to control signals 12 and 13 from a control circuit such as a microcomputer (not shown), the inputs of the booster cells P2 and P3 are the Vdd level of the power supply voltage and the outputs of the booster cells P1 and P2. The switching to the nodes N1 and N2 is also the same as in the first and second embodiments.

Further, as shown in FIG.
X3 is connected to each of the output terminals Y1 and Y2, and according to the H / L level of the output switching control signal 16, the output terminals Y1 and Y2 are connected (ON state) or not (OFF state).
This is the same as the embodiment.

The features of the third embodiment are as follows.

For example, as in the first and second embodiments, the power supply voltage Vdd = 2.5 [V], the voltage drop Vd = 0.5 [V], the booster cell groups P1 and P2 are connected in parallel, When the cell groups P2 and P3 are connected in series, the output terminal Y2 always has 10 terminals regardless of the ON / OFF state of the output switch 18.
[V] (= 5 (Vdd-Vd)) is output.

The power supply voltage Vdd = 2 [V] and the voltage drop Vd =
When the booster cell groups P1 and P2 are connected in parallel and the booster cell groups P2 and P3 are connected in series,
7.5 [V] (= 5 (Vdd-Vd)) is output to the output terminal Y2.
That is, when the external power supply voltage Vdd changes due to noise or load current, the output voltage of the output terminal Y2 also changes accordingly.

Therefore, the voltage level of the output terminal Y2 is detected by the voltage level detecting means 19, and when the voltage of the output terminal Y2 is higher than the desired voltage, for example, all the booster cell groups P1 to P3 are connected in series. From the connected configuration, the booster cell groups P1 and P2 are connected in parallel and the booster cell groups P2 and P3
Is reconfigured to a series-connected booster cell group, so as to reduce the number of stages of the booster cell group, the booster cell group changeover switch 14,
Control 15

Conversely, when the voltage at the output terminal Y2 is lower than the desired voltage, the booster cell group changeover switches 14 and 15 are controlled so as to increase the number of stages of the booster cell group. Here, for example, the desired output voltage from output terminal Y2 is set to 10
[V], when the power supply voltage Vdd changes from 2.5 [V] to 2 [V], the output voltage from the output terminal Y2 becomes 7.5 as it is.
[V], which is too low. This is detected by the voltage level detecting means 19, and the boosting cell group changeover switches 14 and 15 are controlled so as to increase the number of stages of the boosting cell group. ＰP3 are all connected in series. Then, the output terminal Y2 is connected to the ON / OFF state of the output changeover switch 18.
Regardless of F, 10.5 [V] (= 7 (Vdd-Vd)) is output and Vdd = 2.
The desired output voltage at 5 [V] can be approximated to 10 [V].

As described above, according to the third embodiment, the power supply voltage Vd
Even when d fluctuates and the output voltage of each output terminal Y1 to Ym fluctuates, by detecting each output voltage and controlling the boosting cell group switching means 10 to adjust the number of stages of the boosting cell group, it is always possible to A stable output voltage can be obtained, and the reliability is dramatically improved.

Note that the current load fluctuates and each output terminal Y
Even when the output voltages of 1 to Ym fluctuate, each output voltage is detected, and the boosting cell group switching means 10 is controlled to increase or decrease the number of stages of the boosting cell groups connected in series, or are connected in parallel. By adjusting the connection configuration of the booster cell group by increasing or decreasing the number of booster cell groups, it is possible to approach a desired output voltage.

In the third embodiment shown in FIG. 7, all the voltage levels of the output terminals Y1 to Ym are detected. However, the same effect can be obtained by detecting only the voltage levels of some output terminals. Can be obtained. However, in this case, the number of output voltages that can be detected is reduced, but the structure of the voltage level detecting means 19 is simplified accordingly, and the wiring area is also reduced, so that the circuit scale can be reduced.

FIG. 9 is a block diagram showing a configuration of a booster circuit according to a fourth embodiment of the present invention. The same reference numerals are given to portions corresponding to those of the second embodiment shown in FIG.

The feature of the fourth embodiment is that the output terminal Y
At least one of the input terminals Y1 to Ym and an output terminal Y1
, The current level of the load current flowing from .about.Ym is detected, and the current level detecting means 20 for controlling the boosting cell group switching means 10 according to the current level is provided. The other configuration is the same as that of the second embodiment shown in FIG. 4, and the detailed description is omitted here.

The operation of the booster circuit according to the present embodiment configured as described above will be described below.

As in the first to third embodiments, all the same boosting clocks CLK1 to CLKn are supplied from a clock generation means (not shown).

Further, in accordance with a control signal from a control circuit such as a microcomputer (not shown), each of the boosting cell groups P1 to Pn is freely connected in any form of a series, parallel, or series-parallel combination. The switching point is the same as in the first to third embodiments.

Further, the point that each of the nodes X1 to Xn and each of the output terminals Y1 to Ym are switched to a desired connection in accordance with the output switching control signal 16 is the same as in the second and third embodiments.

The features of the fourth embodiment are as follows.

For example, suppose booster cell groups P1 to P (n-1) are all connected in parallel, and booster cell groups P (n-1) and Pn are connected in series. Output terminal Y
1 and Y2, and the output of the first-stage booster cell group P1 to P (n-1) connected in parallel with (n-1) is output to the output terminal Y1, and the second-stage booster cell group The output of Pn is output terminal Y
2, the level of the load current flowing through the output terminal Y1 is detected. At this time, when the current level of the detected load current is higher than a desired current level, the boosting cell group switching means 10 is controlled in accordance with the control signal, and the second boosting cell group Pn is changed to the first boosting cell group. Boost cell group P1 ~
By adding P (n-1) in parallel, the current driving capability can be increased.

As described above, according to the fourth embodiment, by providing the current level detecting means 20, the output terminal Y1
ＹYm, the current level is detected in accordance with the increase of the load current, and the boosting cell group switching means 10 is controlled in accordance with the control signal, so that one or a plurality of boosting cell groups at the desired number of stages are provided. One or more booster cell groups can be added in parallel, and the current driving capability can be increased.

In the fourth embodiment shown in FIG. 9, all the load current levels flowing from the output terminals Y1 to Ym are detected. However, only the load current levels flowing from some output terminals are detected. Can obtain the same effect. However, in this case, the number of load currents that can be detected is reduced, but the structure of the current level detecting means 20 is also simplified accordingly, so that the circuit scale can be reduced.

FIG. 10 is a block diagram showing a configuration of a booster circuit according to a fifth embodiment of the present invention. Parts corresponding to those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals.

The feature of the fifth embodiment is that the phase variable clock generating means 21 for supplying the boosting clocks CLK1 to CLKn having the desired phase control to each of the boosting cell groups P1 to Pn according to the phase control signal is provided. It is prepared.

The other configuration is the same as that of the first embodiment shown in FIG. 1, and the detailed description is omitted here.

The operation of the booster circuit having the above-described configuration according to the present embodiment will be described below.

In response to a control signal from a control circuit such as a microcomputer (not shown), each boost cell group P1
.. Pn are switched so as to be freely connected in any form of series, parallel, or series / parallel.
To the fourth embodiment.

The outputs of the boosting cell groups P1 to Pn are respectively connected to the rectifying diodes Do1 to Don and the capacitive element Co.
Is connected to the common output terminal 2 via the common terminal and forms an output rectification unit 4. The output terminal 2 is supplied with the output of the last-stage booster cell group in the same manner as in the first embodiment. It is.

The features of the fifth embodiment are as follows.

For example, each boost cell group P
When all of 1 to Pn are connected in parallel and used, the phase variable clock generation means 21 is controlled according to the phase control signal,
As shown in FIG. 11, each of the boosting clocks CLK1 to CLK
When the phases of n (cycle T) are set to be shifted at equal intervals, the boosting operation (the boosted voltage oscillates at the same frequency as the boosting clock to be inputted) in each of the boosting cell groups P1 to Pn. Since the peaks can be dispersed, noise generation can be reduced, and a stable output voltage can be obtained from the output terminal 2.

As described above, according to the fifth embodiment, the provision of the variable phase clock generation means 21 allows the boosting cell groups P1 to Pn to perform the desired phase control in accordance with the phase control signal. Since the clocks CLK1 to CLKn can be supplied, noise generation can be reduced, and a stable output voltage can be supplied from the output terminal 2.

Note that the same effect can be obtained even if a booster clock with desired phase control is supplied from the phase variable clock generator 21 to the booster cell group partially connected in parallel. it can.

In the booster circuits according to the second to fourth embodiments, the same effect can be obtained even if the phase variable clock generating means 21 is provided.

FIG. 12 is a block diagram showing the configuration of a booster circuit according to the sixth embodiment of the present invention. The same reference numerals are given to portions corresponding to those of the first embodiment shown in FIG.

The feature of the sixth embodiment is that the frequency variable clock generating means 22 for supplying the boosting clocks CLK1 to CLKn whose desired frequency has been controlled to the boosting cell groups P1 to Pn according to the frequency control signal is provided. It is prepared.

Since the other configuration is the same as that of the first embodiment shown in FIG. 1, detailed description is omitted here.

The operation of the booster circuit of the present embodiment configured as described above will be described below.

In response to a control signal from a control circuit such as a microcomputer (not shown), each boost cell group P1
.. Pn are switched so as to be freely connected in any form of series, parallel, or series / parallel.
To the fifth embodiment.

The outputs of the boosting cell groups P1 to Pn are respectively connected to the rectifying diodes Do1 to Don and the capacitive element Co.
The output rectifier 4 is connected to the common output terminal 2 via a common terminal, and the output of the booster cell group at the last stage is supplied to the output terminal 2 in the first and fifth embodiments. Same as in the case.

The features of the sixth embodiment are as follows.

For example, each booster cell group P
In the case where all of 1 to Pn are connected in series and used, the frequency variable clock generation means 22 according to the frequency control signal.
And each boosting clock CLK as shown in FIG.
The frequency of 1 to CLKn (period T) is set to double (period T
/ 2), the capacity of the boosting operation (the boosted voltage oscillates at the same frequency as the input boosting clock) in each of the boosting cell groups P1 to Pn is doubled.
From the output terminal 2, an output voltage whose current driving capability is doubled can be obtained.

As described above, according to the sixth embodiment, the provision of the variable frequency clock generation means 22 allows the boosting cell groups P1 to Pn to perform boosting with desired frequency control in accordance with the frequency control signal. Clocks CLK1 to CLK
n can be supplied, and the current drive capability of the output voltage can be increased to a desired level.

Further, the frequency of the boosting clock is increased,
By increasing the current driving capability, the number of booster cells used in parallel connection can be reduced, so that the circuit scale can be reduced and the cost can be reduced.

Conversely, the boosting clocks CLK1 to CL
By reducing at least one frequency of Kn, the current drive capability of useless output voltage can be reduced, but in this case, power consumption can be reduced.

Further, the same effect can be obtained even if all the boosting cell groups P1 to Pn are not connected in series.

Further, the boosting clock can be stopped by setting the frequency of the boosting clock to zero, but by sequentially stopping the boosting clock supplied to the final stage boosting cell group, The output voltage can also be adjusted. In this case, generation of an unnecessary boosting clock and unnecessary boosting operation of the boosting cell group can be completely stopped, so that power consumption can be reduced.

Further, in the booster circuits according to the second to fourth embodiments, the same effect can be obtained even if the frequency variable clock generating means 22 is provided.

FIG. 14 is a block diagram showing a configuration of a booster circuit according to a seventh embodiment of the present invention. The same reference numerals are given to parts corresponding to those of the first embodiment shown in FIG.

A feature of the seventh embodiment is that the variable amplitude clock generating means 23 for supplying the boosting clocks CLK1 to CLKn having the desired amplitude control to each of the boosting cell groups P1 to Pn according to the amplitude control signal is provided. It is prepared.

It is assumed that each of the booster cell groups P1 to Pn is composed of two booster cells R1 and R2 as shown in FIG.

The other configuration is the same as that of the first embodiment shown in FIG. 1, and a detailed description is omitted here.

The operation of the booster circuit of the present embodiment configured as described above will be described below.

Each of the booster cell groups P1 is controlled according to a control signal from a control circuit such as a microcomputer (not shown).
.. Pn are switched so as to be freely connected in any form of series, parallel, or series / parallel.
To the sixth embodiment.

The outputs of the boosting cell groups P1 to Pn are respectively connected to the rectifying diodes Do1 to Don and the capacitive element Co.
Are connected to a common output terminal 2 through the output terminal 2 to form an output rectifier 4. The output terminal 2 is also supplied with the output of the last stage booster cell group. This is the same as in the embodiment.

The features of the seventh embodiment are as follows.

For example, each boost cell group P is controlled by a control signal.
When 1 to Pn are all connected in series and used, the amplitude variable clock generation means 23 is controlled according to the amplitude control signal, and the n-th boost clock CL is used as shown in FIG.
When only the amplitude of Kn is set to twice (2 Vdd), the boosting operation capability in the boosting cell group Pn is enhanced.

Specifically, the power supply voltage Vdd is set to 2.5 [V], and FIG.
Voltage drop Vd due to diodes D11 and D12 at
Is 0.5 [V] and the number n of the booster cell groups P1 to Pn is 3,
When each of the boosting cell groups P1 to Pn is driven by using the normal boosting clocks CLK1 to CLKn (L level is GND level and H level is power supply voltage Vdd level), the final voltage obtained from the output terminal 2 is 14 [V] (= (2n + 1) (Vdd-Vd))
However, if only the amplitude of the n-th boost clock CLKn is set to twice (2 Vdd) as shown in FIG. 15, the final voltage obtained from the output terminal 2 is 21 [V] (= 2n (Vdd -V
d) +2 (2Vdd-Vd)), and the final output voltage can be increased.

As described above, according to the seventh embodiment, by providing the variable amplitude clock generating means 23, each of the boosting cell groups P1 to Pn performs the boosting operation in which the desired amplitude control is performed in accordance with the amplitude control signal. Since the clocks CLK1 to CLKn can be supplied, the final output voltage can be changed to a desired voltage without changing the configuration of each booster cell group P1 to Pn.

In the above example, the boosting clock CL
Although the amplitude of Kn has been increased, the boosting clocks CLK1 to CLK1
By reducing at least one amplitude of CLKn, the final output voltage can be reduced, but in this case, power consumption can be reduced.

The same effect can be obtained even if all the boosting cell groups P1 to Pn are not connected in series.

Further, in the booster circuits according to the second to fourth embodiments, the same effect can be obtained even if the variable amplitude clock generating means 23 is provided.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0127]

As described above, according to the present invention, boosting cell group switching means is provided for a plurality of boosting cell groups constituted by at least one boosting cell for boosting and outputting an input voltage. Thereby, the booster cell group can be changed to a desired connection configuration in series, parallel, or series / parallel.
It realizes a low-cost, high-efficiency, and highly-reliable booster circuit that can optimize the output voltage and current drive capability with two booster circuits and can reduce the circuit scale by efficiently using the booster cell group. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of a booster circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a booster cell group including booster cells;

FIG. 4 is a block diagram illustrating a configuration of a booster circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating an example of a configuration of a booster circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining types of output voltages that can be extracted according to a connection configuration of a booster cell group according to the second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a booster circuit according to a third embodiment of the present invention.

FIG. 8 is a block diagram illustrating an example of a configuration of a booster circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a booster circuit according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a booster circuit according to a fifth embodiment of the present invention.

FIG. 11 is a diagram illustrating an example of a waveform of a boosting clock input to a boosting cell group according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a booster circuit according to a sixth embodiment of the present invention.

FIG. 13 is a diagram illustrating an example of a waveform of a boosting clock input to a boosting cell group according to a sixth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a booster circuit according to a seventh embodiment of the present invention.

FIG. 15 is a diagram illustrating an example of a waveform of a boosting clock input to a boosting cell group according to a seventh embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a conventional booster circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Charge pump means 2 Clock generation means 3 Output rectification part 10 Boost cell group switching means 12, 13 Control signal 14, 15 Boost cell group switching switch 16 Output switching control signal 17 Output switching means 18 Output switching switch 19 Voltage level detecting means 20 Current level detecting means 21 Variable phase clock generating means 22 Variable frequency clock generating means 23 Variable amplitude clock generating means

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Ikuo Fuchigami 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Tomio Kimura 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (reference) 5H730 AA14 AA15 BB02 BB57 BB82 BB86 FD01 FG07

Claims (10)

[Claims] 1. A booster cell group comprising at least one booster cell for boosting and outputting an input voltage, and at least two booster cell groups in series, parallel or series-parallel according to a control signal. A boosting cell group switching means for switching to be connected in any form of combination, and a rectifying means for receiving an output of the boosting cell group as an input and performing half-wave rectification and outputting the output, all outputs of the rectifying means being a common output A booster circuit, which is output to a terminal. 2. A plurality of booster cell groups each including at least one booster cell for boosting and outputting an input voltage, and at least two booster cell groups in series, parallel or series-parallel according to a control signal. Boosting cell group switching means for switching to be connected in any form of combination, rectifying means for receiving the output of the boosting cell group as input and performing half-wave rectification and outputting, and output of the rectifying means in response to an output switching control signal Output switching means for switching at least one of the two to connect to at least one output terminal. 3. The step-up circuit according to claim 1, further comprising: a voltage level detecting unit that receives at least one output voltage and detects a voltage level of the output voltage. A booster circuit, wherein the control signal for controlling the booster cell group switching means is adjusted according to a detection level, and the booster cell group is switched so as to be connected in series, parallel, or series-parallel. 4. The boosting circuit according to claim 1, further comprising a current level detecting means for detecting a current level of a load current flowing from at least one output terminal, wherein said current level detecting means is provided. Wherein the control signal for controlling the boosting cell group switching means is adjusted according to the detection level of the boosting cell group, and the boosting cell group is switched so as to be connected in series, parallel, or series-parallel. 5. A plurality of boosting cell groups each including at least one boosting cell for boosting and outputting an input voltage, and boosting each of the boosting cell groups while controlling a phase of each of the boosting cell groups according to a phase control signal. 1. A booster circuit comprising: a phase variable clock generator for supplying a clock for use; and a rectifier for half-wave rectifying the output of the booster cell group as input. 6. The booster circuit according to claim 1, wherein the booster circuit supplies a booster clock while controlling a phase to each booster cell group in accordance with a phase control signal. A booster circuit comprising: a generator. 7. A plurality of boosting cell groups each including at least one boosting cell for boosting and outputting an input voltage, and boosting each of the boosting cell groups while controlling a frequency in accordance with a frequency control signal. 1. A booster circuit comprising: a frequency variable clock generator that supplies a clock for use; and a rectifier that receives an output of the booster cell group as input and performs half-wave rectification and outputs the result. 8. The boosting circuit according to claim 1, wherein the boosting circuit supplies a boosting clock while controlling a frequency to each of the boosting cell groups in accordance with a frequency control signal. A booster circuit comprising a generator. 9. A plurality of boosting cell groups each including at least one boosting cell for boosting and outputting an input voltage, and boosting each of the boosting cell groups while controlling the amplitude of each of the boosting cell groups according to an amplitude control signal. 1. A booster circuit comprising: a variable amplitude clock generator that supplies a clock for use; and a rectifier that receives an output of the booster cell group as an input and performs half-wave rectification and outputs the result. 10. The variable-amplitude clock according to claim 1, wherein the variable-amplitude clock supplies a boosting clock while controlling an amplitude to each of the boosting cell groups according to an amplitude control signal. A booster circuit comprising a generator.