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JP2000348974A - Chip composite function device - Google Patents

Chip composite function device

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Publication number
JP2000348974A
JP2000348974A JP2000141516A JP2000141516A JP2000348974A JP 2000348974 A JP2000348974 A JP 2000348974A JP 2000141516 A JP2000141516 A JP 2000141516A JP 2000141516 A JP2000141516 A JP 2000141516A JP 2000348974 A JP2000348974 A JP 2000348974A
Authority
JP
Japan
Prior art keywords
film dielectric
insulating substrate
film
protective layer
terminal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000141516A
Other languages
Japanese (ja)
Inventor
Minoru Sobane
実 曽羽
Takeshi Izeki
健 井関
Takashi Ikeda
隆志 池田
Koji Nishida
孝治 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000141516A priority Critical patent/JP2000348974A/en
Publication of JP2000348974A publication Critical patent/JP2000348974A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】 【課題】 本発明は、保護層の厚みが薄く、かつ膜誘電
体の耐湿性を向上させることができるチップ複合機能素
子を提供することを目的とする。 【解決手段】 絶縁基板11に設けられた4個の端子電
極12a〜12dと、隣接する2個の端子電極対12
a,12bの層間に形成された膜誘電体13と、この膜
誘電体13が形成される絶縁基板11面とは反対の面に
もう一方の隣接する端子電極対12c,12dの間に形
成された膜抵抗体15と、前記膜誘電体13及び膜抵抗
体15を被覆する保護層とを備え、前記膜誘電体13の
保護層を、下層の結晶化ガラスと上層の非晶質ガラスの
二重構造としたものである。
(57) Abstract: An object of the present invention is to provide a chip composite function element in which the thickness of a protective layer is small and the moisture resistance of a film dielectric can be improved. SOLUTION: Four terminal electrodes 12a to 12d provided on an insulating substrate 11 and two adjacent terminal electrode pairs 12 are provided.
a film dielectric 13 formed between the layers a and 12b, and another terminal electrode pair 12c and 12d formed on the surface opposite to the surface of the insulating substrate 11 on which the film dielectric 13 is formed. A film resistor 15 and a protective layer covering the film dielectric 13 and the film resistor 15. The protective layer of the film dielectric 13 is formed of a lower layer of crystallized glass and an upper layer of amorphous glass. It is a heavy structure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、コンデンサと抵抗
を内蔵したチップ複合機能素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip multifunction device having a built-in capacitor and a resistor.

【0002】[0002]

【従来の技術】近年、電子機器の軽薄短小化に伴い、回
路素子の小型化、薄型化、面実装化が要望され、チップ
抵抗器、チップコンデンサ等のチップ部品の需要が高ま
っている。また、コンデンサと抵抗を1チップ内に内蔵
したチップ複合機能素子の需要も高まりつつある。
2. Description of the Related Art In recent years, as electronic devices have become lighter, thinner and smaller, there has been a demand for smaller, thinner, and more surface-mounted circuit elements, and demand for chip components such as chip resistors and chip capacitors has been increasing. In addition, the demand for a chip composite function element in which a capacitor and a resistor are built in one chip is increasing.

【0003】従来、このコンデンサと抵抗を内蔵したチ
ップ複合素子は実用化されておらず、アルミナ等の絶縁
基板に厚膜抵抗体等の膜抵抗体と厚膜誘電体等の膜誘電
体とを形成したものが考えられている。以下に従来のア
ルミナ基板上に膜抵抗体と膜誘電体を形成したチップ複
合機能素子について説明する。
Heretofore, a chip composite device having a built-in capacitor and a resistor has not been put to practical use, and a film resistor such as a thick film resistor and a film dielectric such as a thick film dielectric are formed on an insulating substrate such as alumina. What has formed is considered. Hereinafter, a conventional chip composite function element in which a film resistor and a film dielectric are formed on an alumina substrate will be described.

【0004】図5(a)は、従来のアルミナ基板上に膜
抵抗体と膜誘電体を形成したチップ複合機能素子の上面
図を示すものであり、図5(b)はその等価回路図であ
る。図5(a)において、1はアルミナ等からなる方形
の絶縁基板で、端子電極2,3が両端に形成されてい
る。4は中間電極で、端子電極3との間で容量を、端子
電極2との間で抵抗をそれぞれ形成する。5は膜抵抗体
で、中間電極4及び端子電極2間に形成されている。6
は膜誘電体で、中間電極4上に一部重なるように形成さ
れている。7は膜誘電体6上に形成された上部電極で、
端子電極3に接続している。図には示していないが、こ
のチップ複合機能素子の表面は、端子電極2,3及び中
間電極4の一部を除き、ポリイミド、または非晶質ガラ
ス等からなる保護コートで覆われている。
FIG. 5A shows a top view of a conventional chip composite function element in which a film resistor and a film dielectric are formed on an alumina substrate, and FIG. 5B is an equivalent circuit diagram thereof. is there. In FIG. 5A, reference numeral 1 denotes a rectangular insulating substrate made of alumina or the like, and terminal electrodes 2 and 3 are formed at both ends. Reference numeral 4 denotes an intermediate electrode that forms a capacitance with the terminal electrode 3 and a resistance with the terminal electrode 2. Reference numeral 5 denotes a film resistor formed between the intermediate electrode 4 and the terminal electrode 2. 6
Is a film dielectric formed so as to partially overlap the intermediate electrode 4. 7 is an upper electrode formed on the film dielectric 6,
Connected to terminal electrode 3. Although not shown in the figure, the surface of the chip composite function element is covered with a protective coat made of polyimide, amorphous glass, or the like, except for a part of the terminal electrodes 2 and 3 and the intermediate electrode 4.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記し
た従来のチップ複合機能素子は、図5(b)に示すよう
に、抵抗とコンデンサの直列回路にしか対応できないと
いう課題を有していた。
However, as shown in FIG. 5B, the above-mentioned conventional chip composite function element has a problem that it can only cope with a series circuit of a resistor and a capacitor.

【0006】さらに、膜誘電体6を覆う保護コートはポ
リイミド、または非晶質ガラス等からなるものであるた
め、膜誘電体6の耐湿性を向上させることができないと
いう課題も有していた。
Furthermore, since the protective coat covering the film dielectric 6 is made of polyimide, amorphous glass, or the like, there is another problem that the moisture resistance of the film dielectric 6 cannot be improved.

【0007】また、膜誘電体6の耐湿性を向上させるに
は保護コートの厚みを厚くする必要があった。
Further, in order to improve the moisture resistance of the film dielectric 6, it is necessary to increase the thickness of the protective coat.

【0008】本発明は上記従来の課題を解決するもの
で、コンデンサと抵抗の直列回路のみならずあらゆる回
路に容易に対応できるとともに、保護コートの厚みが薄
く、かつ膜誘電体の耐湿性を向上させることができるチ
ップ複合機能素子を提供することを目的とする。
The present invention solves the above-mentioned conventional problems and can easily cope with not only a series circuit of a capacitor and a resistor but also any circuit, and has a thin protective coat and an improved moisture resistance of a film dielectric. It is an object of the present invention to provide a chip multifunction device capable of causing the chip multifunction device to operate.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明のチップ複合機能素子は、一端縁に2個以下で
全端縁で4個の凹部または凸部を有する方形の絶縁基板
と、この絶縁基板の凹部または凸部に基板表面から裏面
にかけて設けられた4個の端子電極と、この端子電極の
うち隣接する2個の端子電極対の層間に形成された膜誘
電体と、この膜誘電体が形成される絶縁基板面とは反対
の絶縁基板裏面に前記端子電極対と異なるもう一方の隣
接する端子電極対の間に形成された膜抵抗体と、前記膜
誘電体及び膜抵抗体を被覆する保護層とを備え、前記膜
誘電体の保護層が、下層の結晶化ガラスと上層の非晶質
ガラスの二重構造であることを特徴とするものである。
In order to achieve the above object, a chip composite function device according to the present invention comprises a rectangular insulating substrate having two or less at one end and four concaves or convexes at all edges. Four terminal electrodes provided on the concave or convex portion of the insulating substrate from the front surface to the rear surface of the substrate, and a film dielectric formed between two adjacent terminal electrode pairs among the terminal electrodes; A film resistor formed between another adjacent terminal electrode pair different from the terminal electrode pair on the back surface of the insulating substrate opposite to the insulating substrate surface on which the film dielectric is formed; A protective layer for covering the body, wherein the protective layer of the film dielectric has a double structure of a lower layer of crystallized glass and an upper layer of amorphous glass.

【0010】[0010]

【発明の実施の形態】本発明の請求項1に記載の発明
は、一端縁に2個以下で全端縁で4個の凹部または凸部
を有する方形の絶縁基板と、この絶縁基板の凹部または
凸部に基板表面から裏面にかけて設けられた4個の端子
電極と、この端子電極のうち隣接する2個の端子電極対
の層間に形成された膜誘電体と、この膜誘電体が形成さ
れる絶縁基板面とは反対の絶縁基板裏面に前記端子電極
対と異なるもう一方の隣接する端子電極対の間に形成さ
れた膜抵抗体と、前記膜誘電体及び膜抵抗体を被覆する
保護層とを備え、前記膜誘電体の保護層が、下層の結晶
化ガラスと上層の非晶質ガラスの二重構造であることを
特徴とするもので、この構成によれば、抵抗・コンデン
サを有するチップ複合機能素子の抵抗素子部、コンデン
サ素子部の両端を、4つの端子電極の何れかに割り当
て、抵抗素子部の両端が独立した端子電極として取り出
せるため、抵抗値測定を容易に行うことができ、かつ4
つの端子電極とプリント基板の配線パターンを変更する
ことにより、抵抗・コンデンサ直列回路等の各種回路に
も対応できる。これに加え、内部に空隙を有する結晶化
ガラスの空隙部に非晶質ガラスが埋まるため、保護層の
厚みが薄く、かつ膜誘電体の耐湿性を向上させることが
できるという作用を有するものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a rectangular insulating substrate having two or less at one end and four concaves or convexes at all edges, Alternatively, four terminal electrodes provided on the convex portion from the front surface to the back surface of the substrate, a film dielectric formed between two adjacent terminal electrode pairs among the terminal electrodes, and the film dielectric are formed. A film resistor formed on the back surface of the insulating substrate opposite to the surface of the insulating substrate opposite to the pair of terminal electrodes, and a protective layer for covering the film dielectric and the film resistor. Wherein the protective layer of the film dielectric has a double structure of a lower layer of crystallized glass and an upper layer of amorphous glass, and according to this configuration, it has a resistor and a capacitor. Both ends of the resistance element part and the capacitor element part of the chip composite function element, One assignment to one of the terminal electrodes, since that can be taken out as a terminal electrode both ends of which are independent of the resistance element, it is possible to perform a resistance measurement easily and 4
By changing the wiring patterns of the two terminal electrodes and the printed circuit board, it is possible to cope with various circuits such as a series circuit of a resistor and a capacitor. In addition, since the amorphous glass is buried in the voids of the crystallized glass having voids inside, the protective layer has a small thickness, and has the effect of improving the moisture resistance of the film dielectric. is there.

【0011】(実施の形態1)以下、本発明の実施の形
態1におけるチップ複合機能素子について、図面を参照
しながら説明する。図1(a),(b)及び図2はそれ
ぞれ本発明の実施の形態1におけるチップ複合機能素子
の表側上面図、裏側上面図、等価回路図を示すものであ
る。図1、図2において、11はアルミナ等の方形状の
絶縁基板で、端縁部に4つの凹部を有している。この4
つの凹部から絶縁基板11の表裏面にかけて、端子電極
12a,12b,12c,12dが設けられている。1
3は基板表面の端子電極12a上に形成された膜誘電
体、14はこの膜誘電体13及び端子電極12bに重な
る上部電極、15は基板裏面の端子電極12c,12d
の間に形成された膜抵抗体である。なお、図には示して
いないが、膜誘電体13及び膜抵抗体15を保護するた
めの保護層によって絶縁基板表面は端子電極の端縁部を
除き被覆されている。
(Embodiment 1) Hereinafter, a chip multifunctional element according to Embodiment 1 of the present invention will be described with reference to the drawings. FIGS. 1A, 1B, and 2 show a front top view, a back top view, and an equivalent circuit diagram of a chip composite function device according to Embodiment 1 of the present invention, respectively. 1 and 2, reference numeral 11 denotes a rectangular insulating substrate such as alumina, which has four concave portions at the edge. This 4
Terminal electrodes 12a, 12b, 12c, and 12d are provided from the three concave portions to the front and back surfaces of the insulating substrate 11. 1
Reference numeral 3 denotes a film dielectric formed on the terminal electrode 12a on the front surface of the substrate, 14 denotes an upper electrode overlapping the film dielectric 13 and the terminal electrode 12b, and 15 denotes terminal electrodes 12c and 12d on the back surface of the substrate.
It is a film resistor formed between them. Although not shown in the figure, the surface of the insulating substrate is covered with a protective layer for protecting the film dielectric 13 and the film resistor 15 except for the edge of the terminal electrode.

【0012】なお、膜誘電体13の保護層が、下層の結
晶化ガラスと上層の非晶質ガラスの二重構造、膜抵抗体
15の保護層が、非晶質ガラスとなっている。
The protective layer of the film dielectric 13 has a double structure of a lower layer of crystallized glass and an upper layer of amorphous glass, and the protective layer of the film resistor 15 has an amorphous glass.

【0013】以上のように構成された本発明の実施の形
態1におけるチップ複合機能素子は、一般に内部に空隙
を有する結晶化ガラスの空隙部に非晶質ガラスが埋まる
ため、膜誘電体13の保護層の厚みが薄く、さらに膜誘
電体13に外部の水分が侵入できなくなるため、膜誘電
体13の耐湿性を向上させることができ、これにより膜
誘電体13の絶縁性が悪化してコンデンサ素子部(膜誘
電体13)がコンデンサとしての機能を成さなくなるこ
とを防止できるという効果が得られる。
In the chip composite function device according to the first embodiment of the present invention configured as described above, the amorphous glass is generally buried in the voids of the crystallized glass having voids therein. Since the thickness of the protective layer is small and external moisture cannot penetrate into the film dielectric 13, the moisture resistance of the film dielectric 13 can be improved. The effect of preventing the element portion (film dielectric 13) from functioning as a capacitor can be prevented.

【0014】また、基板表面の端子電極12a,12b
間でコンデンサ素子を、基板裏面の端子電極12c,1
2d間で抵抗素子をそれぞれ独立に形成するため、容易
に通常の直流電流測定法で抵抗素子の抵抗値が測定でき
る。また、図3(a),(b),(c)に示すように4
つの端子電極に対するプリント基板の配線パターンを変
更することにより、抵抗・コンデンサ直列回路等の各種
回路にも対応することができる。図3(a)はRC直列
回路の例、図3(b)はローパスフィルタの例、図3
(c)はハイパスフィルタの例である。
The terminal electrodes 12a, 12b on the substrate surface
A capacitor element is interposed between the terminal electrodes 12c and 1 on the back of the substrate.
Since the resistance elements are independently formed between 2d, the resistance value of the resistance element can be easily measured by a normal DC current measurement method. Also, as shown in FIGS. 3 (a), (b), and (c),
By changing the wiring pattern of the printed circuit board for one terminal electrode, it is possible to cope with various circuits such as a resistor / capacitor series circuit. 3A shows an example of an RC series circuit, FIG. 3B shows an example of a low-pass filter, and FIG.
(C) is an example of a high-pass filter.

【0015】また、本実施の形態では、4つの端子電極
は凹部電極であるが、凸部電極であっても、絶縁基板の
一端縁に2つ以下であれば4端縁にどのように設けられ
ても同様の効果が得られる。
In the present embodiment, the four terminal electrodes are concave electrodes. However, even if the four terminal electrodes are two or less at one edge of the insulating substrate, how they are provided at the four edges is provided. The same effect can be obtained.

【0016】(実施の形態2)以下、本発明の実施の形
態2におけるチップ複合機能素子について、図面を参照
しながら説明する。図4(a),(b)はそれぞれ本発
明の実施の形態2におけるチップ複合機能素子の表側上
面図、裏側上面図を示すものである。図4において、2
1はアルミナ等の方形状の絶縁基板で、端縁部に4つの
凹部を有している。この4つの凹部から絶縁基板21の
表裏面にかけて、端子電極22a,22b,22c,2
2dが設けられている。23は基板表面の端子電極22
a上に形成された膜誘電体、24はこの膜誘電体23及
び端子電極22bに重なる上部電極、25は端子電極2
2c,22dの間に形成された膜抵抗体である。なお、
図には示していないが、膜誘電体23及び膜抵抗体25
を保護する保護層によって絶縁基板21表面は端子電極
の端縁部を除き、被覆されている。
(Embodiment 2) Hereinafter, a chip multifunctional element according to Embodiment 2 of the present invention will be described with reference to the drawings. FIGS. 4A and 4B are a top view and a back view, respectively, of the chip multifunction device according to the second embodiment of the present invention. In FIG. 4, 2
Reference numeral 1 denotes a rectangular insulating substrate such as alumina, which has four concave portions at the edge. From the four concave portions to the front and back surfaces of the insulating substrate 21, terminal electrodes 22a, 22b, 22c, 2
2d is provided. 23 is a terminal electrode 22 on the substrate surface
a, a top electrode overlapping the film dielectric 23 and the terminal electrode 22b; and 25, a terminal electrode 2
This is a film resistor formed between 2c and 22d. In addition,
Although not shown, the film dielectric 23 and the film resistor 25
The surface of the insulating substrate 21 is covered with a protective layer for protecting the terminal electrodes except for the edge portions of the terminal electrodes.

【0017】なお、膜誘電体23の保護層が、下層の結
晶化ガラスと上層の非晶質ガラスの二重構造、膜抵抗体
25の保護層が、非晶質ガラスとなっている。
The protective layer of the film dielectric 23 has a double structure of the lower layer of crystallized glass and the upper layer of amorphous glass, and the protective layer of the film resistor 25 has an amorphous glass.

【0018】以上のように構成された本発明の実施の形
態2におけるチップ複合機能素子は、一般に内部に空隙
を有する結晶化ガラスの空隙部に非晶質ガラスが埋まる
ため、膜誘電体23の保護層の厚みが薄く、さらに膜誘
電体23に外部の水分が侵入できなくなるため、膜誘電
体23の耐湿性を向上させることができ、これにより、
膜誘電体23の絶縁性が悪化してコンデンサ素子部(膜
誘電体23)がコンデンサとしての機能を成さなくなる
ことを防止できるという効果が得られる。
In the chip composite function device according to the second embodiment of the present invention configured as described above, generally, the amorphous glass is buried in the voids of the crystallized glass having voids therein. Since the thickness of the protective layer is small and external moisture cannot enter the film dielectric 23, the moisture resistance of the film dielectric 23 can be improved.
The effect is obtained that it is possible to prevent the deterioration of the insulating property of the film dielectric 23 and prevent the capacitor element portion (the film dielectric 23) from functioning as a capacitor.

【0019】また、端子電極22a,22b間でコンデ
ンサ素子を、端子電極22c,22d間で抵抗素子をそ
れぞれ全く独立に基板表面に形成するため、容易に通常
の直流電流測定法で抵抗素子の抵抗値が測定できる。ま
た、図3に示すように4つの端子電極に対するプリント
基板の配線パターンを変更することにより、抵抗・コン
デンサ直列回路等の各種回路にも対応することができ
る。
Further, since a capacitor element is formed between the terminal electrodes 22a and 22b and a resistance element is formed completely independently between the terminal electrodes 22c and 22d on the substrate surface, the resistance of the resistance element can be easily determined by a normal DC current measuring method. The value can be measured. Further, by changing the wiring pattern of the printed circuit board for the four terminal electrodes as shown in FIG. 3, it is possible to cope with various circuits such as a series circuit of resistors and capacitors.

【0020】また、本実施の形態でも、4つの端子電極
は凹部電極であるが、凸部電極であっても、絶縁基板の
一端縁に2つ以下であれば4端縁にどのように設けられ
ても同様の効果が得られる。
Also, in this embodiment, the four terminal electrodes are concave electrodes. However, even if the four terminal electrodes are convex electrodes, if they are two or less at one edge of the insulating substrate, how are they provided at the four edges? The same effect can be obtained.

【0021】[0021]

【発明の効果】以上のように本発明は、一端縁に2個以
下で全端縁で4個の凹部または凸部を有する方形の絶縁
基板と、この絶縁基板の凹部または凸部に基板表面から
裏面にかけて設けられた4個の端子電極と、この端子電
極のうち隣接する2個の端子電極対の層間に形成された
膜誘電体と、この膜誘電体が形成される絶縁基板面とは
反対の絶縁基板裏面に前記端子電極対と異なるもう一方
の隣接する端子電極対の間に形成された膜抵抗体と、前
記膜誘電体及び膜抵抗体を被覆する保護層とを備え、前
記膜誘電体の保護層が、下層の結晶化ガラスと上層の非
晶質ガラスの二重構造であることを特徴とするもので、
この構成によれば、抵抗・コンデンサを有するチップ複
合機能素子の抵抗素子部、コンデンサ素子部の両端を、
4つの端子電極の何れかに割り当て、抵抗素子部の両端
が独立した端子電極として取り出せるため、抵抗値測定
を容易に行うことができ、かつ4つの端子電極とプリン
ト基板の配線パターンを変更することにより、抵抗・コ
ンデンサ直列回路等の各種回路にも対応できる。
As described above, the present invention provides a rectangular insulating substrate having two or less at one end and four concaves or convexes at all edges, and a substrate surface at the concave or convex part of the insulating substrate. The four terminal electrodes provided from the terminal electrode to the back surface, the film dielectric formed between two adjacent terminal electrode pairs among the terminal electrodes, and the insulating substrate surface on which the film dielectric is formed A film resistor formed between another terminal electrode pair different from the terminal electrode pair on the back surface of the opposite insulating substrate, and a protective layer covering the film dielectric and the film resistor; Dielectric protective layer, characterized in that it has a double structure of the lower layer of crystallized glass and the upper layer of amorphous glass,
According to this configuration, both ends of the resistance element portion and the capacitor element portion of the chip composite function element having the resistance / capacitor,
Assigned to any of the four terminal electrodes, and both ends of the resistance element portion can be taken out as independent terminal electrodes, so that resistance value measurement can be easily performed and the wiring pattern of the four terminal electrodes and the printed circuit board can be changed. Accordingly, various circuits such as a series circuit of a resistor and a capacitor can be supported.

【0022】さらに、内部に空隙を有する結晶化ガラス
の空隙部に非晶質ガラスが埋まるため、保護層の厚みが
薄く、かつ膜誘電体の耐湿性を向上させることができる
という効果を奏するものである。
Furthermore, since the amorphous glass is filled in the voids of the crystallized glass having voids therein, the protective layer has a small thickness and the moisture resistance of the film dielectric can be improved. It is.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)本発明の実施の形態1におけるチップ複
合機能素子の表側上面図 (b)同裏側上面図
FIG. 1A is a front top view of a chip multifunction device according to a first embodiment of the present invention; FIG.

【図2】同等価回路図FIG. 2 is an equivalent circuit diagram of the same.

【図3】同チップ複合機能素子の回路使用の一例を示す
回路図
FIG. 3 is a circuit diagram showing an example of using a circuit of the chip multifunction device.

【図4】(a)本発明の実施の形態2におけるチップ複
合機能素子の表側上面図 (b)同裏側上面図
FIG. 4A is a top side view of the chip multifunction device according to Embodiment 2 of the present invention, and FIG.

【図5】(a)従来のチップ複合機能素子の上面図 (b)同等価回路図FIG. 5A is a top view of a conventional chip multifunction device. FIG. 5B is an equivalent circuit diagram thereof.

【符号の説明】[Explanation of symbols]

11 絶縁基板 12a,12b,12c,12d 端子電極 13 膜誘電体 14 上部電極 15 膜抵抗体 DESCRIPTION OF SYMBOLS 11 Insulating substrate 12a, 12b, 12c, 12d Terminal electrode 13 Film dielectric 14 Upper electrode 15 Film resistor

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01G 4/12 445 H01G 1/02 J (72)発明者 池田 隆志 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 西田 孝治 大阪府門真市大字門真1006番地 松下電器 産業株式会社内──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification FI theme coat ゛ (Reference) H01G 4/12 445 H01G 1/02 J (72) Inventor Takashi Ikeda 1006 Odakadoma, Kadoma City, Osaka Matsushita Electric Within Sangyo Co., Ltd. (72) Inventor Koji Nishida 1006 Kazuma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 一端縁に2個以下で全端縁で4個の凹部
または凸部を有する方形の絶縁基板と、この絶縁基板の
凹部または凸部に基板表面から裏面にかけて設けられた
4個の端子電極と、この端子電極のうち隣接する2個の
端子電極対の層間に形成された膜誘電体と、この膜誘電
体が形成される絶縁基板面とは反対の絶縁基板裏面に前
記端子電極対と異なるもう一方の隣接する端子電極対の
間に形成された膜抵抗体と、前記膜誘電体及び膜抵抗体
を被覆する保護層とを備え、前記膜誘電体の保護層が、
下層の結晶化ガラスと上層の非晶質ガラスの二重構造で
あることを特徴とするチップ複合機能素子。
1. A rectangular insulating substrate having two or less concave portions or convex portions at one end and four or less at all edges, and four concave portions or convex portions provided on the insulating substrate from the front surface to the rear surface of the substrate. Terminal electrode, a film dielectric formed between two adjacent terminal electrode pairs among the terminal electrodes, and the terminal on the back surface of the insulating substrate opposite to the surface of the insulating substrate on which the film dielectric is formed. A film resistor formed between another adjacent terminal electrode pair different from the electrode pair, and a protective layer covering the film dielectric and the film resistor, wherein the protective layer of the film dielectric is
A chip composite function element having a double structure of a lower layer of crystallized glass and an upper layer of amorphous glass.
JP2000141516A 2000-01-01 2000-05-15 Chip composite function device Pending JP2000348974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000141516A JP2000348974A (en) 2000-01-01 2000-05-15 Chip composite function device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000141516A JP2000348974A (en) 2000-01-01 2000-05-15 Chip composite function device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP04128479A Division JP3104398B2 (en) 1992-05-21 1992-05-21 Chip composite function device

Publications (1)

Publication Number Publication Date
JP2000348974A true JP2000348974A (en) 2000-12-15

Family

ID=18648616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000141516A Pending JP2000348974A (en) 2000-01-01 2000-05-15 Chip composite function device

Country Status (1)

Country Link
JP (1) JP2000348974A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100771501B1 (en) 2006-04-07 2007-10-30 주식회사 쎄라텍 Composition for surface coating of multilayer chip type electronic component, multilayer chip type electronic component using same and method for manufacturing same
KR20140027454A (en) * 2011-07-11 2014-03-06 가부시키가이샤 무라타 세이사쿠쇼 Electronic component
JP2017126704A (en) * 2016-01-15 2017-07-20 株式会社村田製作所 Composite electronic component

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100771501B1 (en) 2006-04-07 2007-10-30 주식회사 쎄라텍 Composition for surface coating of multilayer chip type electronic component, multilayer chip type electronic component using same and method for manufacturing same
KR20140027454A (en) * 2011-07-11 2014-03-06 가부시키가이샤 무라타 세이사쿠쇼 Electronic component
CN103703526A (en) * 2011-07-11 2014-04-02 株式会社村田制作所 Electronic component
KR101656294B1 (en) * 2011-07-11 2016-09-09 가부시키가이샤 무라타 세이사쿠쇼 Electronic component
JP2017126704A (en) * 2016-01-15 2017-07-20 株式会社村田製作所 Composite electronic component

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