JP2000348011A - Microcomputer with electrically rewritable nonvolatile memory - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent the CPU 1 from stopping in a memory rewrite mode. In a memory rewrite mode in which a ROM is externally rewritten, a data-only address bus and a data bus occupied by the memory rewrite are connected to a CPU.
1 by releasing the dedicated address bus 9 and the code bus 10 which are not occupied in the memory rewriting mode for code access and data access to the RAM 16 in a time-division manner.
1 is provided with a bus control means for enabling access to the RAM 16 and avoiding stopping the operation of the CPU 1 in the memory rewrite mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Harvard architecture type microcomputer having a built-in electrically rewritable nonvolatile memory.

[0002]

2. Description of the Related Art FIG. 6 is a circuit block diagram showing a schematic partial configuration of a conventional Harvard architecture type microcomputer (hereinafter referred to as Harvard type microcomputer) having a built-in electrically rewritable nonvolatile memory. is there. In the drawing, 1 is a CPU, 2 is a code interface unit (CIU), 3 is a data interface unit (DIU), 5 is a code dedicated address terminal of the code interface unit 2, 6 is a code terminal of the code interface unit 2, and 7 is a data terminal. 8 is a data terminal of the data interface unit 3, 9 is a code-only address bus (C_AD), 11 is a data-only address bus (D_AD), 10 is a code bus (CB), and 12 is data. A bus (DB), 16 is a RAM, and 18 is a ROM.

Reference numeral 15 denotes a RAM interface circuit.
The code-only address bus 9 or the data-only address bus 11 is connected to the address bus 20 (RAM_
AD), and the code bus 10 or the data bus 12 is connected to a bus 21 (RAM_DB) in the RAM 16.

Reference numeral 17 denotes a ROM interface circuit.
The code-only address bus 9 or data-only address bus 11 is connected to the address bus 22 (ROM_ROM
AD), and the code bus 10 or the data bus 12 is connected to a bus 23 (ROM_DB) in the ROM 18.

[0005] In the memory rewrite mode 19,
This is a memory rewriting interface circuit for connecting external terminals to the data bus 11 and the data bus 12. Reference numeral 24 denotes a mode setting circuit, which is set to "0" in the microcomputer mode when a mode is selected by terminal setting,
A control signal H which becomes "1" in the memory rewrite mode is output.

[0006] First, referring to FIG.
An operation in a mode (microcomputer mode) of operating by accessing codes and data in the RAM 18 and RAM 16 will be described.
In this microcomputer mode, the CPU 1 reads a code from the ROM 18 or the RAM 16 and decodes the code to execute a command. If the command is a data read command, the CPU 1 reads data from the ROM 18 or the RAM 16. If the instruction is a write instruction, the data stored in the register of CPU 1 is stored in RAM 1.
Write to 6. Thus, in microcomputer mode, CPU
1 performs two accesses to the ROM 18 and the RAM 16, namely, code reading (code access) and data reading / writing (data access).

In particular, as shown in FIG. 6, those having independent code dedicated address bus 9 and code bus 10 for code access and independent data dedicated address bus 11 and data bus 12 for data access are code access and data access. Can be performed at the same time, so that the processing performance is improved. Such an architecture in which a bus for code access and a bus for data access are separated is called a Harvard architecture.

Reference numeral 4 in FIG. 6 denotes an arbitration circuit for the code interface unit 2 and the data interface unit 3, which generates a gate control signal E at the same time so that code access and data access do not overlap in the same memory.

In FIG. 6, a gate control signal / E represents an inverted signal of the gate control signal E. Here, arbitration is required only when code access and data access to the same memory overlap at the same time. For example, code access is performed to the ROM 18 at the same time, and data access is performed to the RAM 16 at the same time. When the code access is performed to the RAM 16 at the same time and the data access is performed to the ROM 18 at the same time, there is no operational problem.

FIG. 7 is a timing chart showing an operation at the time of memory access by the CPU 1 of the Harvard microcomputer shown in FIG. When the gate control signal E is "1", the address bus 20 in the RAM 16 becomes the code-only address bus 9, the bus 21 in the RAM 16 becomes the code bus 10, and the address bus 22 in the ROM 18 becomes the data-only address bus 11. , Bus 2 in ROM 18
3 are connected to the data bus 12, respectively.

When the gate control signal E is "0", the address bus 20 in the RAM 16 is the data dedicated address bus 11, the bus 21 in the RAM 16 is the data bus 12, and the address bus 22 in the ROM 18 is the code bus. The dedicated address bus 9 and the bus 23 in the ROM 18 are connected to the code bus 10, respectively.

That is, when the gate control signal E is "1", code access to the RAM 16 is performed,
Data access to the ROM 18 is performed. When the gate control signal E is “0”, data access to the RAM 16 and code access to the ROM 18 are performed. (Since the control signal H is "0" in the microcomputer mode, the data-only address bus 11 and the data bus 12 are not connected to the memory-rewriting interface circuit 19, so that the memory-rewriting interface circuit 19 does not operate and the data-only address bus 11 and Data bus 12
Has no effect. )

Next, the operation in the memory rewrite mode will be described. FIG. 8 is a timing chart showing an operation in the memory rewrite mode of the Harvard microcomputer shown in FIG. Here, the memory rewrite mode is the ROM1
8 is a mode for electrically rewriting the contents of
1 is a reset mode in which the microcomputer chip 1 is stopped, and the microcomputer chip behaves as a single memory.

When the memory rewrite mode is set by the setting of the external terminal, the control signal H output from the mode setting circuit 24 becomes "1". At this time, the CPU 1, the code interface unit 2, and the data interface unit 3 stop, and the gate control signal E output from the arbitration circuit 4 becomes "1". At this time, as shown in FIG.
The address bus 20 in the inside is connected to the code-only address bus 9,
The bus 21 in the RAM 16 is connected to the code bus 10 and the ROM 1
The address bus 22 in 8 is a data-only address bus 11
Meanwhile, the buses 23 in the ROM 18 remain connected to the data bus 12, respectively.

As a result, the memory rewriting interface circuit 19 supplies the address and the data information inputted from the external terminals to the ROM 18 via the data access dedicated address bus 11 and the data bus 12 to perform the rewriting operation of the ROM 18. Can be accomplished.

[0016]

Since the conventional microcomputer with a built-in electrically rewritable nonvolatile memory is constructed as described above, when the data in the ROM 18 is rewritten using the memory rewriting mode, The dedicated data address bus 11 and the data bus 12 for data access are occupied by the memory rewrite interface circuit 19, so that the CPU 1 cannot access the data, and the CPU 1 has to stop. Therefore, there is a problem that the system in which the microcomputer is mounted is stopped because the CPU 1 does not operate while the memory is being rewritten.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and is an electrically rewritable nonvolatile memory which does not stop the CPU even while rewriting the memory in the memory rewriting mode. It is intended to obtain a microcomputer with a built-in memory.

It is another object of the present invention to provide an electrically rewritable nonvolatile memory built-in microcomputer capable of reducing the time required for rewriting the memory in the memory rewriting mode and reducing the time for stopping the system equipped with the microcomputer. .

[0019]

A microcomputer with an electrically rewritable nonvolatile memory according to the present invention has a data-only address bus occupied by the memory rewrite in a memory rewrite mode in which the nonvolatile memory is rewritten from the outside. And the data bus is released from the CPU, and the code-only address bus and the code bus which are not occupied in the memory rewrite mode are separately used in a time-division manner for code access use and data access use for the volatile memory. A bus control means is provided for enabling access to the memory and avoiding the stop of the operation of the CPU in the memory rewrite mode.

A microcomputer with an electrically rewritable nonvolatile memory according to the present invention includes a data-only address bus, connection and disconnection of a data bus and a data interface unit, and a data interface for a code-only address bus and a code bus. A bus switching circuit for performing connection and disconnection to the unit and the code interface unit by time-division control in a memory rewrite mode based on a gate control signal; and, in the memory rewrite mode, connecting the volatile memory to the code-only address bus. A memory interface circuit for connecting a nonvolatile memory to the data-only address bus and the data bus based on a gate control signal; a memory interface circuit for connecting the nonvolatile memory to the data bus based on a gate control signal; A mode setting circuit for outputting a control signal corresponding to the setting of the microcomputer mode which allows the volatile memory and access to the nonvolatile memory with,
A gate circuit for connecting and disconnecting the data-only address bus and the data bus to and from the external terminals based on the control signal; and preventing code access and data access from overlapping in the same memory at the same time, and An arbitration circuit that outputs the gate control signal for realizing the division control based on a signal input / output state of the data interface unit and the code interface unit and the control signal output by the mode setting circuit. It is like that.

A microcomputer with an electrically rewritable non-volatile memory according to the present invention provides a microcomputer in a memory rewriting mode in which the non-volatile memory is rewritten from outside.
The data-only address bus and the data bus occupied by the memory rewrite are released from the CPU, and one of the code-only address bus and the code bus that is not occupied in the memory rewrite mode is connected to the C bus.
A bus control means for releasing from the PU and the volatile memory and using the one of the released buses as an extension bus for the data bus to speed up rewriting of the nonvolatile memory in the memory rewriting mode; It is like that.

A microcomputer having an electrically rewritable nonvolatile memory according to the present invention comprises a data address bus, a data bus and a data interface unit connected and disconnected, and a code bus connected to a code interface unit and an external terminal. And a gate circuit for controlling the opening and closing based on a control signal, and a gate control signal for connecting the volatile memory of the code bus whose connection with the code interface unit is released by the gate circuit in the memory rewriting mode. And a memory interface circuit for opening the code bus to an extended bus of the nonvolatile memory based on the control signal, the memory rewriting mode, the volatile memory and the nonvolatile memory by a CPU. Access to memory A mode setting circuit for outputting the control signal according to the setting of the microcomputer mode which enables scan,
At the same time, code access and data access to the same memory are prevented from overlapping, and the gate control signal for releasing the connection of the code bus to the volatile memory in the memory rewrite mode is transmitted to the data interface. And an arbitration circuit for outputting the signal based on the control signal output from the mode setting circuit.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit block diagram showing a schematic partial configuration of a microcomputer with an electrically rewritable nonvolatile memory according to the first embodiment. In the figure, 1 is a CPU, 2 is a code interface unit (CLU), 3 is a data interface unit (DU).
1U), 5 is a code dedicated address terminal of the code interface unit 2, 6 is a code terminal of the code interface unit 2, and 7 is a data interface unit 3.
8 is a data terminal of the data interface unit 3, 9 is a code-only address bus (C_AD), 10 is a code bus (CB), 11 is a data-only address bus (D_AD), and 12 is a data bus (DB). ) And 16 are a RAM (volatile memory) and 18 is an electrically rewritable ROM (non-volatile memory).

Reference numeral 15 denotes a RAM interface circuit (memory interface circuit, bus control means), which is a code-only address bus 9 or a data-only address bus 11.
Is connected to the address bus 20 (RAM_AD) in the RAM 16 and the code bus 10 or the data bus 12
Is connected to the bus 21 (RAM_DB) in the RAM 16.

Reference numeral 17 denotes a ROM interface circuit (memory interface circuit, bus control means), which is a code-only address bus 9 or a data-only address bus 11.
Is connected to the address bus 22 (ROM_AD) in the ROM 18 and the code bus 10 or the data bus 12
Is connected to the bus 23 (ROM_DB) in the ROM 18.

In the memory rewrite mode 19,
This is a memory rewriting interface circuit for connecting external terminals to the data bus 11 and the data bus 12. Reference numeral 24 denotes a mode setting circuit (bus control means) which outputs a control signal H which becomes "0" in the microcomputer mode and "1" in the memory rewrite mode when the mode is selected by terminal setting.

Reference numeral 25 denotes a bus switching circuit (bus control means), which can switch between connecting the code dedicated address bus 9 to the code interface unit 2 and the data interface unit 3. Can be switched between connecting to the code interface unit 2 side and connecting to the data interface unit 3 side. An arbitration circuit (bus control means) 41 outputs gate control signals A, B, C, and E in response to the input control signal H.

In FIG. 1, circuit elements indicated by the symbol ◇ and circuit elements such as G1 and G2 indicated by the symbol ゲ ー ト are gate circuits having control terminals. Control signals A, B, C, E
For example, it is possible to use a transmission gate whose on / off is controlled by the above. Gate circuits G1, G
2 corresponds to a bus control means.

Next, the operation will be described with reference to FIG. First, the operation in the microcomputer mode will be described with reference to FIG. FIG. 2 shows a control signal H, gate control signals A, B, C, and E in the microcomputer mode, an address bus 20 in the RAM 16, a bus 21 in the RAM 16,
8 and the bus 23 in the ROM 18.
It is a timing chart which shows an upper signal.

In this microcomputer mode, the control signal H becomes "0", the arbitration circuit 41 outputs the gate control signal A as "0", and the gate control signal B and the gate control signal C
Is output as “1”. At this time, since the data dedicated address terminal 7 of the data interface unit 3 is connected to the data dedicated address bus 11 and the data terminal 8 of the data interface unit 3 is connected to the data bus 12,
The operation in the microcomputer mode is the same as that described with reference to the timing chart of FIG.

Next, the operation in the memory rewrite mode will be described. FIG. 3 shows a control signal H, gate control signals A, B, C, E, and R in this memory rewrite mode.
Address bus 20 in AM 16 and bus 2 in RAM 16
1. Address bus 22 in ROM 18 and ROM 18
6 is a timing chart showing signals on a bus 23 in FIG.

In the memory rewrite mode, the control signal H becomes "1", and the arbitration circuit 41 outputs the gate control signal B as "0" and the gate control signal E as "1". Since the gate control signal E is "1", the data dedicated address bus 11 and the data bus 12 are connected to the memory rewriting interface circuit 19 and the ROM 18 in the same manner as described in the prior art.
And the data in the ROM 18 is rewritten.

The difference between the timing chart of FIG. 3 and the timing chart of FIG. 8 described in the prior art is as follows. When the gate control signal C is "1" and the gate control signal A is "0", the address bus 20 in the RAM 16 is
Are connected to the code bus 10, respectively.
When the gate control signal C is “0” and the gate control signal A is “1”, the address bus 20 in the RAM 16 is connected to the data dedicated address bus 11 via the code dedicated address bus 9 and to the bus 21 in the RAM 16. Are connected to the data bus 12 via the code bus 10, respectively.

By utilizing this, the CPU 1 can operate even in the memory rewriting mode. That is, when the gate control signal C is "1" and the gate control signal A is "0", code access to the RAM 16 is performed. When the gate control signal C is "0" and the gate control signal A is "1", code access is performed. RA
The CPU 1 can perform data access to M16.

As described above, by using the dedicated code address bus 9 and the code bus 10 in a time-sharing manner for code access to the RAM 16 and data access to the RAM 16, the CPU 1 can access and operate the RAM 16 even during execution of ROM rewriting. Can be done.

As described above, the first embodiment
According to this, in order to operate the CPU 1 in the memory rewrite mode, the code-only address bus 9 and the code bus 10
Therefore, there is an effect that a microcomputer with an electrically rewritable nonvolatile memory can be obtained which can avoid the stop of the operation of the system due to the stop of the CPU 1 without increasing the chip area by adding a new bus. .

Embodiment 2 FIG. 4 shows the second embodiment.
1 is a circuit block diagram showing a schematic partial configuration of a microcomputer with a built-in electrically rewritable nonvolatile memory. 4, the same or corresponding parts as in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The difference from the conventional microcomputer with built-in electrically rewritable nonvolatile memory shown in FIG. 6 is that the code bus 10 is connected to the memory rewriting interface circuit 59 via the control signal H, and the ROM 18 The point indicated by the reference numeral 61 switched by the control signal H is added to the interface circuit 37, and the condition by the control signal H (the control signal H and the gate control signal E When both are “0”, the gate control signal D becomes “1” and the RAM 1
6 is connected to the code bus 10) and the connection terminal of the code bus 10 in the code interface unit 2 and the code bus 10 are switched by the control signal H. .

In FIG. 4, 4 is an arbitration circuit (bus control means), 35 is a RAM interface circuit (memory interface circuit, bus control means), 37 is a ROM interface circuit (memory interface circuit, bus control means), and 59 is a memory. It is a rewriting interface circuit. In the second embodiment, the code bus 10 is connected to the memory rewriting interface circuit 59 and the code interface unit 2.
Is configured between.

In FIG. 4, the circuit elements indicated by the symbol 、 and the circuit elements such as G3, G4, G5 and G6 indicated by the symbol ◇ are gate circuits having control terminals, and control signals supplied to the control terminals. It is possible to use a transmission gate whose on / off is controlled by the signal H, the gate control signals E and D, and the like. Gate circuit G
3, G4, G5 and G6 correspond to bus control means.

Next, the operation in the microcomputer mode and the memory rewrite mode will be described. In the microcomputer mode, the control signal H becomes "0", and the gate between the code bus 10 and the memory rewrite interface circuit 59 and the bus 23 in the ROM 18 which is switched by the control signal H in the ROM interface circuit 37 and the code bus 10 Since the gate is cut off, the operation of the circuit shown in FIG. 4 is the same as that of the conventional circuit shown in FIG. That is, the operation is the operation shown in the timing chart of FIG. 7 described in the related art.

Next, the operation in the memory rewrite mode will be described. In this memory rewriting mode, the control signal H becomes "1", and the ROM 1 switched between the code bus 10 and the memory rewriting interface circuit 59 and the ROM 1 switched by the control signal H in the ROM interface circuit 37.
8 and the code bus 10 are connected.

That is, for the ROM 18, the code bus 10 and the data bus 12 are connected to the bus 23 inside the ROM 18.
Will be connected. The code bus 10 and the data bus 1 are also connected to the memory rewriting interface circuit 59.
2 will be connected.

The advantage of such a connection is that the code bus 10 which has not been used in the conventional memory rewrite mode is used as a data transmission path when rewriting the memory.
2 is that the data bus width for memory rewriting can be doubled. If the bit width of the data bus 12 is 16 bits and the bit width of the code bus 10 is 16 bits
With bits, the bus width for data transmission in the memory rewrite mode in FIG. 4 can be extended to 32 bits. By this bus width expansion, the time required for rewriting can be reduced, and, for example, the time required for verifying the data in the memory is theoretically halved.

FIG. 5 shows a timing chart in the memory rewrite mode. The difference from the timing chart shown in FIG. 8 in the conventional microcomputer with built-in electrically rewritable nonvolatile memory is that the bus 23 in the ROM 18 uses both the code bus 10 and the data bus 12 and the memory rewriting interface circuit 59. In the memory rewriting mode of the second embodiment, the CPU 1 remains stopped.

As described above, according to the second embodiment, the code bus 10 can be diverted and the bus width can be expanded in order to increase the rewrite speed in the memory rewrite mode, so that a new bus is added. This makes it possible to increase the rewriting speed in the memory rewriting mode without increasing the chip area, and to obtain an electrically rewritable nonvolatile memory built-in microcomputer that can reduce the system stop time due to the CPU stop. is there.

[0046]

As described above, according to the present invention, in the memory rewrite mode in which the nonvolatile memory is rewritten from the outside, the code-only address bus and the code bus which are not occupied for rewriting the nonvolatile memory are connected to the volatile memory. It is configured so that it can be used in a time-sharing manner for code access and data access for
The volatile memory can be accessed by the CPU in the memory rewrite mode, and the CPU can operate without stopping in the memory rewrite mode.

The microcomputer with built-in electrically rewritable nonvolatile memory according to the present invention includes a data-only address bus, connection and disconnection of a data bus and a data interface unit, and a data interface for a code-only address bus and a code bus. The bus switching circuit controls the connection and disconnection to the unit and the code interface unit in the memory rewrite mode in a time-division manner based on the gate control signal, so that the CPU can access the volatile memory in the memory rewrite mode. Therefore, the CPU can access the volatile memory in the memory rewrite mode, and the CPU can operate without stopping in the memory rewrite mode.

A microcomputer with an electrically rewritable nonvolatile memory according to the present invention is capable of rewriting a nonvolatile memory from the outside in a memory rewriting mode.
The data-only address bus and the data bus occupied by the memory rewrite are released from the CPU, and one of the code-only address bus and the code bus that is not occupied in the memory rewrite mode is connected to the C bus.
Since the configuration is configured to be released from the PU and the volatile memory and to use the released one bus as an extension bus of the data bus, it is possible to speed up the rewriting process for the nonvolatile memory in the memory rewriting mode, This has the effect of reducing the time during which the microcomputer-equipped system stops.

The microcomputer with built-in electrically rewritable nonvolatile memory according to the present invention comprises: a connection and disconnection of a data-only address bus, a data bus and a data interface unit, and a connection of a code bus to a code interface unit and an external terminal. And a gate circuit for controlling the opening and closing based on a control signal according to the setting of the memory rewrite mode and the microcomputer mode, and the code bus in which the connection to the code interface unit is released by the gate circuit in the memory rewrite mode. A memory interface circuit that opens the connection with the volatile memory based on the gate control signal and the control signal and connects the code bus to an expansion bus of the nonvolatile memory based on the control signal. Because it was configured in The code bus that is not occupied in the memory rewrite mode can be released from the CPU and the volatile memory, and the released code bus can be used as an expansion bus for the data bus. This has the effect of speeding up the rewriting process for the memory and reducing the time during which the system with the microcomputer is stopped.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a schematic partial configuration of a microcomputer with a built-in electrically rewritable nonvolatile memory according to a first embodiment of the present invention;

FIG. 2 is a timing chart showing an operation in a microcomputer mode of the microcomputer with a built-in electrically rewritable nonvolatile memory according to the first embodiment of the present invention;

FIG. 3 is a timing chart showing an operation in a memory rewriting mode of the microcomputer with a built-in electrically rewritable nonvolatile memory according to the first embodiment of the present invention;

FIG. 4 is a circuit block diagram showing a schematic partial configuration of a microcomputer with a built-in electrically rewritable nonvolatile memory according to a second embodiment of the present invention;

FIG. 5 is a timing chart showing an operation in a memory rewrite mode of a microcomputer with an electrically rewritable nonvolatile memory according to a second embodiment of the present invention;

FIG. 6 is a circuit block diagram showing a schematic partial configuration of a conventional Harvard architecture microcomputer incorporating an electrically rewritable nonvolatile memory.

FIG. 7 is a timing chart at the time of memory access by a CPU of a Harvard architecture type microcomputer incorporating a conventional electrically rewritable nonvolatile memory.

FIG. 8 is a timing chart showing an operation in a memory rewriting mode of a Harvard architecture type microcomputer incorporating a conventional electrically rewritable nonvolatile memory.

[Explanation of symbols]

1 CPU, 2 code interface unit, 3
Data interface unit, 4,41 arbitration circuit (bus control means), 9 dedicated code address bus, 10
Code bus, 11 Data-only address bus, 12
Data bus, 15, 35 RAM interface circuit (memory interface circuit, bus control means), 16
RAM (volatile memory), 17, 37 ROM interface circuit (memory interface circuit, bus control means), 18 ROM (non-volatile memory), 24 mode setting circuit (bus control means), 25 bus switching circuit (bus control means) , G1, G2, G3, G4, G5, G6 gate circuits (bus control means).

Claims (4)

[Claims] An independent bus dedicated to code access and a code bus for data access, and an independent address bus dedicated to data access and a data bus for data access;
A nonvolatile memory built-in microcomputer including a volatile memory and an electrically rewritable nonvolatile memory accessible through the code dedicated address bus and the code bus, and the data dedicated address bus and the data bus, In a memory rewrite mode in which the nonvolatile memory is externally rewritten, the data-only address bus and the data bus occupied by the memory rewrite are released from the CPU, and the code-only address bus and the code bus not occupied in the memory rewrite mode Is used for code access and data access to the volatile memory in a time-sharing manner, thereby enabling the CPU to access the volatile memory, and stopping the operation of the CPU during the memory rewrite mode. A microcomputer with a built-in electrically rewritable nonvolatile memory, characterized by comprising a bus control means for avoiding shutdown. 2. A bus control means for connecting and disconnecting a dedicated data address bus and a data bus to a data interface unit, and connecting and disconnecting a dedicated code address bus and a code bus to and from the data interface unit and the code interface unit. A bus switching circuit for performing time-division control in a memory rewrite mode based on a gate control signal; and, in the memory rewrite mode, transferring a volatile memory to the code-only address bus and the code bus based on a gate control signal. A memory interface circuit that connects the nonvolatile memory to the data-only address bus and the data bus based on a gate control signal; and the memory rewrite mode, and the CPU accesses the volatile memory and the nonvolatile memory. To A mode setting circuit for outputting a control signal according to the setting of the microcomputer mode to be enabled; a gate circuit for connecting and disconnecting the data-only address bus and the data bus to external terminals based on the control signal; The gate control signal for realizing the time-division control while preventing code access and data access from overlapping in the same memory at the same time is determined based on the signal input / output states of the data interface unit and the code interface unit. 2. The microcomputer with built-in electrically rewritable nonvolatile memory according to claim 1, further comprising an arbitration circuit that outputs the control signal based on the control signal output from a mode setting circuit. 3. A code dedicated address bus and code bus for code access, and a data dedicated address bus and data bus for data access are independently provided,
A nonvolatile memory-equipped microcomputer including a volatile memory and an electrically rewritable nonvolatile memory accessible through the code-only address bus and the code bus, and the data-only address bus and the data bus, In a memory rewrite mode in which the nonvolatile memory is rewritten from outside, the data dedicated address bus and the data bus occupied by the memory rewrite are released from the CPU, and the code dedicated address bus or the code bus not occupied in the memory rewrite mode. By releasing any one of the buses from the CPU and the volatile memory, and using the released one bus as an extension bus of the data bus, the nonvolatile memory in the memory rewrite mode can be used. A microcomputer with a built-in electrically rewritable nonvolatile memory, comprising a bus control means for speeding up rewriting. 4. The bus control means controls connection and disconnection of a data-only address bus and a data bus to a data interface unit, and connection and disconnection of a code bus to a code interface unit and an external terminal based on control signals. A gate circuit, and in a memory rewrite mode, a connection between the code circuit and the volatile memory of the code bus whose connection to the code interface unit is released by the gate circuit is released based on a gate control signal and a control signal, A memory interface circuit for connecting the code bus to an extension bus of the nonvolatile memory based on a control signal; and a memory mode for enabling the memory rewrite mode and a CPU to access the volatile memory and the nonvolatile memory by a CPU. Outputs the control signal according to the setting A mode setting circuit for inputting the code access and the data access to the same memory at the same time, and the gate for releasing the connection of the code bus to the volatile memory in the memory rewrite mode. 4. An arbitration circuit for outputting a control signal based on a signal input / output state of the data interface unit and the code interface unit and the control signal output by the mode setting circuit. The microcomputer with built-in electrically rewritable nonvolatile memory described in the above.