JP2000235481A - Data table selection arithmetic unit - Google Patents

Abstract

(57) [Problem] To provide a two-dimensional function for calculating y using x and z as arguments in a conventional device, using an adder / subtractor / multiplier / divider when the function formula is complicated. With this configuration, there is a problem that the circuit scale becomes large and the operation becomes slow. SOLUTION: A selection circuit unit 200, 201, 202 that approximates a function expression to a data table that monotonically increases and selects a data table row from input values of a row that increases or decreases.
And comparison circuit units 300 to 302, 310, and 3 for comparing the input data table value with the value stored in the data table in the row selected by the selection circuit unit.
20, 330, and a comparison value output from the comparison circuit unit, and an output circuit unit 400 that converts a value output from a combination circuit that detects a change point between 0 and 1 into a value of the data table column. Since all circuits can be configured without using any adder / subtractor / multiplier / divider, the circuit scale is small and high-speed operation is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data table selection / calculation device, and more particularly to a data table selection / calculation device which simplifies an output circuit which detects a change point between 0 and 1 and converts it into a combination data table sequence value.

[0002]

2. Description of the Related Art As information communication devices become smaller and lighter, digital signal processing circuits including a data table selection processor are required to be smaller and operate faster. As a basic configuration method of the data table selection operation device, the data table selection operation device is configured by a circuit that determines a function expression using an adder and a multiplier and obtains an output value of a data table column or row.

[0003]

However, in a conventional apparatus, in a two-dimensional function for calculating y using x and z as arguments, if the function formula is complicated (quadratic formula, cubic formula,
If a circuit is configured using an adder / subtractor / multiplier / divider for a trigonometric function, a logarithmic function, etc., there is a problem that the circuit scale becomes large and the operation becomes slow. SUMMARY OF THE INVENTION It is an object of the present invention to solve such a problem and to provide a data table selecting / calculating apparatus which operates at high speed with a simple and small circuit scale.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the object, the present invention is directed to a data processing apparatus comprising: Selecting circuit means for selecting a data table row from input values; comparing circuit means for comparing the input data table value with a value stored in the data table in the row selected by the selecting circuit means; Combination circuit means for detecting a change point between 0 and 1 based on a comparison value output from the circuit means, and output circuit means for converting a value output from the combination circuit means into a value of the data table column. It is characterized by having.

According to the present invention, all circuits are provided with an adder / subtractor / multiplier / divider by a combination of a selection circuit, a comparison circuit, a combination circuit for detecting a change point between 0 and 1, and an output circuit. Since the configuration can be performed without using any components, the circuit scale can be reduced and the operation can be performed at high speed.

According to a second aspect of the present invention, the circuit means for outputting the upper address of the data table row and the circuit means for outputting the lower address of the data table row have a configuration in which the output circuit is divided into two. Features.

According to the present invention, the configuration of the output circuit means is 2
By dividing the output table means into one, the configuration of the output circuit means according to the first aspect of the present invention can be simplified, so that the circuit scale of the data table selection operation device can be reduced and the operation can be performed at high speed. Having.

The invention according to claim 3 is characterized in that the selection circuit means is replaced by a selection circuit means for selecting a column of a data table.

According to the present invention, it is possible to reduce the circuit scale and operate at high speed.

[0010]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

(Embodiment) FIG. 1 is a block diagram showing a configuration of a data table selection operation device according to an embodiment of the present invention. As shown in FIG. 1, selection circuit units 200, 201, and 202 select a data table row from input values of an increasing or decreasing row, and input data table values and specific data in a row selected from the selection circuit unit. Comparison circuit units 300, 301, 30 for comparing table values
2, 310, 320, and 330, and an output circuit section 400 for outputting a value of a data table column from a comparison value output from the comparison circuit section.

FIG. 2 is a block diagram showing a configuration of the selection circuit units 200, 201, and 202 for selecting a row of the data table of FIG. This selection circuit section is for all mbit X
Is decoded by the decoder circuit 21.

FIG. 3 shows a comparison circuit section 300, 301, 302, 310, 32 for comparing columns of a selected row in FIG.
It is a block diagram which shows the structure of 0,330. The comparison circuit includes a value of the output circuit 31 that outputs H when the n-bit input data table value (Z value) that is arbitrarily changed is smaller than the specific data table value (table value). NOR circuit 3 with output value (X-deck)
2 is performed.

FIG. 4 is a block diagram showing a configuration of an upper bit output unit of the output circuit unit 400 for detecting a transition point between 0 and 1 in FIG. 1 when the column (j) of the data table has 128 rows. The configuration is described as an example.

The circuit for detecting the change point between 0 and 1 is as follows:
The values of all the comparison circuit units for each row of one column are ORed by the OR circuit 41, and the result is processed by the NAND circuit 42 by eight columns in order to make the result 16 bits. The result is processed by the EXOR circuit 43 with adjacent values. However, the processing result of the NAND circuit in the last column is directly used as 16-bit least significant data. And 16bi
The upper 4 bits of the value of Y are determined by encoding the result of t by the 16-bit encoder circuit 44.

FIG. 5 is a block diagram showing the structure of the lower bit output section of the output circuit section 400 for detecting the transition point between 0 and 1 in FIG. 1. As in FIG. Has 128 lines as an example. The circuit for detecting the transition point between 0 and 1 calculates the result of the logical sum by the OR circuit 41 of the higher-order bit output unit, and uses the result of the higher-order bit output unit as a selector signal from 16 to 16 tol-selector. In circuit 51, select
The result is processed by the EXOR circuit 52 with adjacent values. However, the result of inverting the selector in the last column is used as it is as 16-bit least significant data. And 8 bits
Is encoded by the 8-bit encoder circuit 53, so that the lower 3 bits of the value of Y are determined.

Next, a data table selection operation device according to an embodiment of the present invention is described by using z = 0.2xy + 0.2x in FIG.
Using a data table represented by a function formula of +0.1 as an example, x
The operation when = 1 and z = 0.6 will be described with reference to FIGS.

In FIG. 1, the value (1) of mbit X is selected by the selection circuit section (X-dec0, X-dec1, X-dec).
k) When input to 200 to 202, the decoder circuit 2
1 (FIG. 2), only the selection circuit unit (X-dec1) has 0
Is output, and the remaining selection circuit units (X-dec0, X-d
eck) outputs 1. Then, paying attention to the selected row (first row), the comparison circuit units (C0,1, C1,1, C2,
When the value of Z (0.6) is input to (1, Cj, 1), 0 is output only to the comparison circuit units (C0, 1, C1, 1), and the remaining comparison circuit units (C2, 1, Cj) are output. , 1) outputs 1. Further, 0 is output from the comparison circuit units in other rows.

The data of the column output from the comparison circuit is ORed by the OR circuit 41 (FIG. 4) for each of the eight columns in the upper bit configuration unit of the output circuit.

The output result is T1 [0] and T1 on the right
Only [1] outputs 0, and 1 is output from the remaining T1. NAND circuit 42 of upper bit configuration section of output circuit section
In FIG. 4, only the leftmost outputs 1 and the remaining NAND
The circuit 42 outputs 0.

EXOR of upper bit configuration section of output circuit section
Only the leftmost outputs 1 from the circuit 43 (FIG. 4), and outputs 0 from the remaining EXOR circuits 43. as a result,
16-bit encoding of the upper bit configuration unit of the output circuit unit
10000000000000000 is input to the er circuit 44, and the output Y [6: 3] = 0. Also, 16 tol-selector 51 of the upper bit configuration unit of the output circuit unit
In FIG. 5, T1 [0], T1 [1], and T1 [7] are selected, and only 0 is output for T1 [0] and T1 [1], and 1 is output for the remaining T1 [7]. You. As a result, the 8-bit encoder circuit 53 of the lower bit configuration unit of the output circuit unit
01000000 is input to (FIG. 5) and output Y [2: 0]
= 1. From the above, the output value obtained is Y = 1.

[0022]

As described above, according to the data table selection operation device of the present invention, the combination of the selection circuit means, the comparison circuit means, the combination circuit means for detecting a change point between 0 and 1, and the output circuit means Accordingly, all the components can be configured without using any adder / subtractor / multiplier / divider, so that the circuit scale can be reduced and high-speed and high-speed operation can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data table selection operation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a selection circuit unit for selecting a row of the data table of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a comparison circuit unit for comparing columns of a selected row in FIG. 1;

FIG. 4 is a block diagram showing a configuration of an upper bit output unit of the output circuit unit for detecting a change point between 0 and 1 in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a lower bit output unit of the output circuit unit for detecting a transition point between 0 and 1 in FIG. 1;

FIG. 6 is a data table diagram represented by a functional expression of z = 0.2xy + 0.2x + 0.1.

[Explanation of symbols]

200 1st row selection circuit section 201 2nd row selection circuit section 202 kth row selection circuit section 300 1st row and 1st column comparison circuit section 301 2nd row and 1st column comparison circuit section 302 kth row and 1st column comparison circuit section 310 1 Row 2 column comparison circuit section 320 1st row 3rd column comparison circuit section 330 1st row jth column comparison circuit section 400 Output circuit section for detecting a transition point between 0 and 1 21 Decoder circuit of selection circuit section 31 Comparison circuit section Output circuit of Z value and table value (H value when Z value <table value is true) 32 NOR circuit in comparison circuit section 41 OR circuit in output circuit upper bit configuration section 42 NAND circuit in output circuit upper bit configuration section 43 EXOR circuit of output circuit high-order bit configuration unit 44 16-bit-enc of output circuit high-order bit configuration unit
order circuit 51 16 tol-sel of lower bit configuration part of output circuit
Vector circuit 52 EXOR circuit of output circuit lower bit configuration unit 53 Output circuit lower bit configuration unit 8 bit-encode
er circuit

Claims (3)

[Claims] 1. A data table column which approximates a function expression to a monotonically increasing data table and arbitrarily changes an input data table value based on a range of values stored in a data table having an increasing characteristic. Selecting circuit means for selecting a data table row from the input values of the increasing or decreasing rows in order to output the value of the input data table value and storing the data in the data table in the row selected by the selecting circuit means Comparison circuit means for comparing the values output from the comparison circuit means; combination circuit means for detecting a change point between 0 and 1 based on the comparison value output from the comparison circuit means; A data table selection / calculation device, comprising output circuit means for converting the data table value into a value. 2. The data table selection operation device according to claim 1, wherein said output circuit means includes respective circuit means for outputting each of an upper address and a lower address of said data table column. 3. When the selection circuit means selects a data table row from input values of an increasing or decreasing column, the data is stored in a data table having an increasing characteristic with respect to an arbitrarily changing input data table value. 2. The data table selection / calculation device according to claim 1, wherein the data table selection / calculation device operates as a data table selection / calculation device that outputs a value of a data table row based on the range of the value.