JP2000232168A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory device capable of suppressing occurrence of corner rounding at the time of patterning a resist, reducing the cell size, and achieving high integration. SOLUTION: The length DT. W ₁ , the channel length DT. L ₁ , the length of the word transistor WT. W ₁ and the word channel length of the transistor WT. Between L _1, the following relationship is to be established. (DT.W ₁ /WT.W ₁ ) / (WT.L ₁ /DT.L
₁ ) <1.2 Length DT. Length WT of W ₁ and the word transistor. W ₁ and the p-type active region 101
a, 101b while reducing the channel length WT. The L _1, the channel length of the driving transistor DT. Greater than L ₁ to _{(WT.L 1 /DT.L 1> 1)} .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SRAM (Static Random Access Memory) having, for example, a 6-transistor configuration.
The present invention relates to a semiconductor memory device such as a static random access memory (cell).

In general, an SRAM cell has a flip-flop and conduction / non-conduction controlled in accordance with a voltage applied to a word line, and determines whether or not each of two storage nodes of the flip-flop is connected to a bit line. And a transistor (word transistor). This S
RAM cells can be broadly classified into two types, a MOS transistor load type and a high resistance load type, depending on the difference in the load element of the flip-flop. Of these, the MOS transistor load type
It has a configuration having six transistors. Depending on the type of the load transistor, a p-channel MOS transistor (hereinafter, referred to as pMOS) load type, TFT (Thin)
Film Transistor (load type) is known.

FIG. 6 shows an example of an arrangement pattern of a conventional pMOS load type SRAM cell. This drawing shows the state after the gate of the transistor is formed, and the upper wiring layers such as connection lines and bit lines inside the cell are omitted.

The pMOS load type SRAM cell 100
Are two p-type active regions 101a and 101b in which an n-channel MOS transistor (hereinafter, referred to as nMOS) as a driving transistor is formed, and a p-channel MOS transistor (hereinafter, pMO) as a load transistor.
S) are formed on the two n-type active regions 102a,
102b. These p-type active regions 101a,
The periphery of 101b and the n-type active regions 102a and 102b is, for example, a LOCOS (Local Oxidation of Silicon) or an element isolation insulating region 103 having a trench structure.

In this conventional SRAM cell 100,
The two p-type active regions 101a and 101b each have a step 106, and are arranged vertically in parallel in the figure. In the p-type active region 101a, the step 106
A drive transistor Qn1 and a word transistor Qn3 are formed on both sides of the. In the other p-type active region 101b, a word transistor Qn4 and a drive transistor Qn2 are formed on both sides of the step 106. The word line (WL) 104a also serving as the gate electrode of the word transistor Qn3 is a p-type active region 101a.
The word line (WL) 104b also serving as the gate electrode of the word transistor Qn4 is connected to the p-type active region 101b.
Are arranged so as to be orthogonal to each other. On the other hand, the common gate line 105a (GL1) also serving as the gate electrode of the drive transistor Qn1 is connected to the p-type active region 10
The common gate line 105b (GL2) is perpendicular to the vertical direction of FIG.
01b. The common gate lines 105a and 105b and the word lines 104a and 104
b is formed by a first polysilicon layer containing impurities.

The common gate line 105a is connected to the n-type active region 10
It is also orthogonal to 2a. Similarly, common gate line 1
05b is also orthogonal to the n-type active region 102b. As a result, the pMOS (load transistor Qp1 or Qp2) is applied to each of the n-type active regions 102a and 102b.
Are formed. A first inverter is configured by the load transistor Qp1 and the drive transistor Qn1,
Similarly, load transistor Qp2 and drive transistor Q
A second inverter is constituted by n2. The first inverter and the second inverter constitute a flip-flop. Note that the common gate line 105
a and the word line 104b, and the common gate line 105b and the word line 104a are respectively arranged in the same straight line. Each of the p-type active regions 101a and 101b is electrically connected to a bit line (not shown) or a supply line (not shown) for V _SS (common potential) via a contact 107. Further, the p-type active region 101a and the n-type active region 102a, and the p-type active region 101b and the n-type active region 102b are respectively formed by contacts (not shown).
Are electrically connected to each other. The n-type active regions 12a and 12b are connected to V _CC via a contact (not shown).
(Power supply voltage) supply line.

[0007]

SUMMARY OF THE INVENTION As described above, the conventional 6
Looking at the relationship between a word transistor and a driving transistor in an SRAM having a transistor configuration, the channel length of the driving transistors Qn1 and Qn2 is DT. L,
The channel length of the word transistors Qn3 and Qn4 is W
T. L, DT. L = WT. L.
As a specific example, for example, as shown in Table 1 below,
DT. L = WT. L = 0.18 μm. The length of the driving transistors Qn1 and Qn2 is DT.
W and the length of the word transistors Qn3 and Qn4 are expressed as WT.
W, DT. W = 0.64 μm, WT. W = 0.
49 μm. Note that the length of each transistor indicates the length in the direction orthogonal to the direction in which the channel current flows.

Conventionally, in such an SRAM cell, D
T. W / WT. W = DT. L / WT. In general, L = 1.0, that is, the size (channel length and length) of the driving transistors Qn1 and Qn2 and the word transistors Qn3 and Qn4 are generally equal to each other.

[0009] However, in the case of a cell design in which the stability of cell operation such as a static noise margin (hereinafter referred to as SNM) is to be ensured, the drive transistor Qn is required as described above.
1 and Qn2 and the size of the word transistors Qn3 and Qn4 are not equalized, but the drive transistors Qn
1, the length DT. W is the word transistor Qn
3, Qn4 length WT. The resistance component with respect to the channel current of the word transistors Qn3 and Qn4 is made relatively larger than that of the drive transistors Qn1 and Qn2, thereby reducing the pull-down current. Therefore, as shown in FIG. 6, in the above-described conventional SRAM cell 100, drive transistors Qn1 and Qn2 and word transistor Qn are connected to each other.
A step 106 is formed in the pattern of the p-type active regions 101a and 101b so that the lengths of n3 and Qn4 are different. Here, the size of the step 16 is DT. WW
T. W = 0.15 μm.

By the way, in such an SRAM cell, a self-aligned contact technique is introduced for the purpose of high integration, or a first polysilicon layer (that is, an underlying first polysilicon layer when forming a contact pattern). Word lines 104a, 104b, common gate lines 105a, 1
By improving the alignment accuracy with respect to 05b), the space between the polysilicon layer and the contact 107 is reduced, thereby reducing the cell size.

However, in general, in the resist patterning process, the p-type active regions 101a and 101b
In the step 106 of the pattern of the above, the corner portion is rounded (Corner Rounding; corner rounding),
The pattern shape as designed cannot be obtained. Therefore, as described above, the space between the polysilicon layer and the contact 107 is reduced, and as a result, when the distance between the drive transistors Qn1 and Qn2 and the word transistors Qn3 and Qn4 is reduced, , And the drive transistor Qn1, Qn2,
The distance between the word transistors Qn3 and Qn4 is reduced. That is, as shown by the two-dot chain line in FIG. 6, the drive transistors Qn1 and Qn2 and the word transistor Qn are located at or near the corner-rounding portion (corner-rounding generating section 106a).
3, Qn4 will be formed. Therefore, in the conventional SRAM cell, there is a problem that a drive transistor and a word transistor having the designed length cannot be obtained.

For this reason, in the conventional SRAM cell, a self-aligned contact technique is introduced,
Alternatively, even when the space between the polysilicon layer and the contact is reduced by improving the alignment accuracy with respect to the underlying polysilicon layer when forming the contact pattern, the gap between the driving transistor and the word transistor is reduced. It is necessary to expand the space to an area that is not affected by the corner rounding occurrence,
This eventually became a factor that hindered the reduction in cell size.

The present invention has been made in view of the above problems, and has as its object to suppress the occurrence of corner rounding during the patterning of a resist, to reduce the cell size, and to achieve high integration. It is to provide a storage device.

[0014]

A semiconductor memory device according to the present invention has a length DT. W, the channel length DT. L, the length of the word transistor WT. W and channel length W of word transistor
T. L, (DT.W / WT.W) / (WT.L / DT.L) <
1.2. Note that in each transistor, the length refers to a length in a direction orthogonal to a direction in which a channel current flows.

In this semiconductor memory device, the length DT. W, channel length of drive transistor D
T. L, the length of the word transistor WT. W and the channel length WT. L having the above relationship with DT.L. W / WT. W close to 1.0 and WT. L / DT. L is larger than 1.0, that is, the channel length WT. L
Is the channel length DT. Of the driving transistor. By making L larger than L, the step of the pattern in the active region is reduced or the step is eliminated. Therefore, occurrence of corner rounding during patterning of the resist is suppressed.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Prior to the description of a specific embodiment, a circuit configuration of a pMOS load type SRAM cell will be described with reference to FIG.

This pMOS load type SRAM cell has a structure composed of six transistors, and is an n-channel type MOS transistor (hereinafter referred to as nMOS) Qn.
1, Qn2, and p-channel MOS transistors (hereinafter referred to as pMOS) Qp1 and Qp2. n
MOSs Qn1 and Qn2 are drive transistors, p
The MOSs Qp1 and Qp2 each function as a load transistor. These load transistors pMO
SQp1 and Qp2 and drive transistor nMOSQn
1 and Qn2, two inverters (flip-flops) are formed in which the input terminals cross each other, one input terminal is connected to the other output terminal, and the other input terminal is connected to one output terminal. I have.

The nMOS Qn3 and nMOS Qn4 connect the connection points (storage nodes ND1, ND2) of each inverter to the bit line BL in accordance with the voltage applied to the word lines WL1, WL2.
1, a word transistor that controls whether or not to connect to BL2. This cell configuration is common, where
A more detailed description of the connection relationship will be omitted.

In this pMOS load type SRAM cell,
One bit line BL1 is set to a high potential, and the word lines WL are connected to the gates of the word transistors Qn3 and Qn4.
1 and WL2, a predetermined voltage is applied to turn on both transistors Qn3 and Qn4, and the storage node ND
1. Charge is stored in ND2. One of the storage nodes is "H
(High), the driving transistors Qn1 and Qn2 and the load transistors Qp1 and Qp2 operate so that the other storage node becomes "L (low)" as a feature of the flip-flop configuration. For example, when the storage node ND1 is “H” and the storage node ND2 is “L”,
The drive transistor Qn2 and the load transistor Qp1 are turned on, and the drive transistor Qn1 and the load transistor Q
p2 is off, and storage node ND1 is at power supply voltage V
Receiving the supply of charge from the cc supply line, storage node ND2 is kept at the ground potential. Conversely, when the potential of the bit line BL1 is “L”, the word transistor Qn3 is turned on to force the storage node ND1 to go to “L”, or when the potential of the bit line BL2 is “H”, the word transistor Qn4 is turned on. Turns on, storage node ND
2 forcibly shifts to "H", the driving transistor Q
n1 and Qn2 and load transistors Qp1 and Qp2 are all inverted, and storage node ND2 receives supply of charge from the supply line of power supply voltage Vcc, and storage node ND1 is held at the ground potential. As described above, the charge is statically stored in the storage node ND by performing the charge holding by the flip-flop.
1, ND2 and the potential is “L” or “H”
Is associated with the data “0” and “1”, respectively, and this data can be stored in the six transistors in the cell.

[First Embodiment] Next, referring to FIG. 1, a six-transistor type S according to a first embodiment of the present invention will be described.
The configuration of the pattern of the RAM cell will be described. This S
The RAM cell 10 includes p-type active regions 11a and 11b as active regions of the first conductivity type and n-type active regions 12a and 12b as active regions of the second conductivity type. These p-type active regions 11a and 11b and n-type active region 1
The periphery of 2a, 12b is, for example, an element isolation insulating region 13 having a LOCOS or trench structure.

In this SRAM cell 10, two p
The mold active regions 11a and 11b are respectively arranged vertically in parallel in the figure. In one p-type active region 11a, a drive transistor Qn1 and a word transistor Qn3 are formed on both sides thereof. In the other p-type active region 11b, a word transistor Qn4 and a drive transistor Qn2 are formed on both sides thereof. Word line (WL) also serving as gate electrode of word transistor Qn3
The word line (WL) 1 serving as a gate electrode of the word transistor Qn4 is provided in the p-type active region 11a.
4b are wired so as to be orthogonal to the p-type active region 11b. On the other hand, the common gate line 15a (G) serving also as the gate electrode of the drive transistor Qn1
L1) is perpendicular to the p-type active region 11a in the vertical direction of FIG. 1, and is also similar to the common gate line 15b (GL
2) is orthogonal to the p-type active region 11b.

The common gate line 15a is connected to the n-type active region 12a
Are also orthogonal. Similarly, the common gate line 15b
Are orthogonal to the n-type active region 12b. Thereby, the pMOSs are respectively provided in the n-type active regions 12a and 12b.
(A load transistor Qp1 or Qp2). Load transistor Qp1 and drive transistor Qn1
Constitute a first inverter, and similarly, a second inverter is constituted by the load transistor Qp2 and the drive transistor Qn2. The first inverter and the second inverter constitute a flip-flop. Note that the common gate line 15a and the word line 14
b, and the common gate line 15b and the word line 14a are respectively arranged in the same straight line. The common gate lines 15a and 15b and the word lines 14a and 14b
Are formed by a first polysilicon layer containing impurities.

The basic configuration of the above SRAM cell 10 is as follows.
Although substantially the same as the conventional SRAM cell 100 (FIG. 6), the SRAM cell 10 of the present embodiment has the length DT. Of the drive transistors Qn1 and Qn2. W ₁ , the channel length DT. Of the drive transistors Qn1 and Qn2. L _1, word transistor Qn3, Qn4 of length WT. W ₁ and word transistors Qn3, the channel length of Qn4 WT. L
_The following relationship is established between the p-type active regions 11a and 11b, and the steps in the patterns of the p-type active regions 11a and 11b are eliminated.

(DT.W ₁ /WT.W ₁ ) / (WT.L ₁ /DT.L ₁ ) = 0.77─ (1)

In the present embodiment, the driving transistor length DT. Length WT of W ₁ and the word transistor.
W ₁ (DT.W ₁ = WT.W ₁ ), but the channel length WT. Channel length L ₁ is the driving transistor DT. L ₁ (WT.L ₁ /
DT. L ₁ > 1). Specific examples of the combinations of the lengths of the transistors having such a relationship include the following numerical values as described in column (d) of Table 1.

DT. W ₁ = WT. W ₁ = 0.49 μm,
WT. L ₁ = 0.23 μm, DT. L ₁ = 0.18 μm

[0028]

[Table 1]

In this embodiment, the driving transistor Qn
1, the length DT. W ₁ and the word transistor Qn
3, Qn4 length WT. W ₁ and a equally, while eliminating a step in the p-type active region 11a, 11b of the pattern, the word transistor Qn3, a channel length of Qn4 W
T. The L ₁ driving transistor Qn1, a channel length of Qn2 DT. It is set to be larger than L _1. That is, the channel length WT. Of the word transistors Qn3 and Qn4. L ₁ is driving transistor Qn1, a channel length of Qn2 DT. L
By being larger than ₁ , the word transistor Qn
3, the resistance component to the channel current in Qn4 is
The driving transistors Qn1 and Qn2 become relatively larger than those of the driving transistors Qn1 and Qn2, and cell operation such as SNM can be stabilized. Further, since there are no steps in the p-type active regions 11a and 11b, when these p-type active regions 11a and 11b are formed by patterning a resist, drive transistors Qn1 and Qn2 and word transistors Qn3 and Qn4 are formed.
Between them, no corner rounding as in the related art occurs.

Therefore, as described above, the self-aligned contact technique is introduced, or the accuracy of alignment with the underlying polysilicon layer at the time of forming the contact pattern is improved, so that the contact between the polysilicon layer and the contact is improved. This space can be made as small as possible without considering the effect of corner rounding. Therefore, in this embodiment, it is possible to reduce the cell area and achieve high integration while obtaining an SNM equivalent to that of a conventional SRAM cell.

In the above embodiment, the length DT. W ₁ and word transistor length W
T. W ₁ is made equal, and no step is formed in the p-type active regions 11a and 11b.
If the influence of the occurrence of corner rounding can be substantially ignored, DT. W ₁ and WT. With different lengths of the W _1, it may be provided some of the step.
That is, generally, the length DT.
W, the channel length DT. L, the length of the word transistor WT. W and the channel length WT. L may be configured to have the following relationship.

(DT.W / WT.W) / (WT.L / DT.L) <1.2─ (2)

Of course, also in this case, the channel length WT. L is the channel length DT. L (WT.L / DT.L>
1) is the same as in the above embodiment.

The above equation (2) is preferably the following equation (3), and more preferably the following equations (4) and (5).

(DT.W / WT.W) / (WT.L / DT.L) <1.1─ (3)

(DT.W / WT.W) / (WT.L / DT.L) <1.0─ (4)

(DT.W / WT.W) / (WT.L / DT.L) <0.9─ (5)

FIG. 5 shows the relationship between (DT.W / WT.W) /
(WT.L / DT.L) and the step [DT.L / DT.L]. W
-WT. W]. As is clear from this figure, (DT.W / WT.W) / (WT.L
/ DT. As the size ratio of L) decreases, the step [D
T. W-WT. W] is reduced, and the influence of corner rounding is eliminated. Table 1 shows (b) to
(D), the step [DT. W-WT. W] (that is, (DT.W / WT.W) is set to 1.
0), the channel length WT. L is the channel length DT. L
((WT.L / DT.L)> 1).

Hereinafter, (DT.W / WT.W) / (WT.
L / DT. Other examples of the specific value of L) will be described as a second embodiment and a third embodiment. In the following embodiments, the configuration other than the relationship between the length and the channel length of the driving transistor and the length and the channel of the word transistor is substantially the same as that of the SRAM cell 10 shown in FIG. Therefore, portions having substantially the same functions as those in the first embodiment are denoted by the same reference numerals, and a specific description thereof will be omitted.

[Second Embodiment] SR of this embodiment
AM cell 20 has a length DT. Of drive transistors Qn1 and Qn2. W ₂ , the channel length DT. Of the drive transistors Qn1 and Qn2. L ₂ , word transistors Qn3, Qn4
Length WT. W ₂ and the word transistor Qn3, Q
n4 channel length WT. Between L _2, we have the following relationship.

(DT.W ₂ /WT.W ₂ ) / (WT.L ₂ /DT.L ₂ ) = 0.93─ (6)

Specifically, as described in column (c) of Table 1, DT. W ₂ = 0.54, WT. W ₂ = 0.4
9 μm, WT. L ₂ = 0.21 μm, DT. L ₂ = 0.
18 μm. The pattern of the p-type active regions 11a and 11b has a step 16 (DT.W ₂ -WT.
W ₂ ) is present, but is one-third the size of the conventional SRAM cell 100. Further, the channel length WT. Of the word transistors Qn3 and Qn4. L
₂ is the channel length D of the driving transistors Qn1 and Qn2.
T. Is larger (1.18-fold) than the L _2.

[Third Embodiment] SR of this embodiment
AM cell 30 has a length DT. Of drive transistors Qn1 and Qn2. W ₃ , the channel length DT. Of the drive transistors Qn1 and Qn2. L ₃ , word transistors Qn3, Qn4
Length WT. W ₃ and word transistors Qn3, Qn
n4 channel length WT. Between the L _3, it has the following relationship.

(DT.W ₃ /WT.W ₃ ) / (WT.L ₃ /DT.L ₃ ) = 1.13─ (7)

Specifically, as described in column (b) of Table 1, DT. W ₃ = 0.59, WT. W ₃ = 0.4
9 μm, WT. L ₃ = 0.19 μm, DT. L ₃ = 0.
18 μm. In the present embodiment, the p-type active region 11
The patterns 16a and 11b have a step 16 (D
T. W ₃ -WT. W ₃ ), but the conventional SR
The size is two-thirds that of the AM cell 100. Further, the channel length WT. Of the word transistors Qn3 and Qn4. L ₃ is a drive transistor Qn1, Qn2
Channel length DT. Is larger (1.06-fold) than the L _3.

The effects of the SRAM cells 20 and 30 in the second and third embodiments are substantially the same as those of the SRAM cell 10 in the first embodiment. The occurrence of corner rounding can be suppressed, so that it is possible to reduce the cell size and achieve high integration while obtaining the same SNM as that of the related art.

[0047]

As described above, according to the semiconductor memory device of the present invention, the length DT. W, the channel length DT. L, the length of the word transistor WT. W and the channel length WT. L, (DT.W / WT.W) / (WT.L / DT.L) <
Since it is configured to have the relationship of 1.2, it is possible to suppress the occurrence of corner rounding at the time of patterning the resist, and thus it is possible to reduce the cell size and achieve high integration.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining a pattern configuration of an SRAM cell according to a first embodiment of the present invention.

FIG. 2 is a plan view for explaining a pattern configuration of an SRAM cell according to a second embodiment of the present invention.

FIG. 3 is a plan view for explaining a pattern configuration of an SRAM cell according to a third embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a pMOS load type SRAM cell.

FIG. 5: (DT.W / WT.W) / (WT.L / DT.
L) and the step [DT. W-WT. [W].

FIG. 6 is a diagram illustrating a pattern configuration of a conventional SRAM cell.

[Explanation of symbols]

10, 20, 30... SRAM cells, 11a, 11b.
Type active regions, 12a, 12b... N-type active regions, 13... Element isolation regions, 14a, 14b.
WL2), 15a, 15b... Common gate lines (GL1, G
L2), 16 steps

Claims (5)

[Claims] 1. A semiconductor memory device comprising, for each memory cell, a drive transistor and a word transistor adjacent to each other in an active region of the same conductivity type, wherein the drive transistor has a length DT. W, the channel length DT. L, the length WT. Of the word transistor. W and the channel length WT. L, (DT.W / WT.W) / (WT.L / DT.L) <
A semiconductor memory device having the relationship of 1.2. 2. (DT.W / WT.W) / (WT.L /
DT. 2. The semiconductor memory device according to claim 1, wherein L) <1.1. 3. (DT.W / WT.W) / (WT.L /
DT. 2. The semiconductor memory device according to claim 1, wherein a relationship of L) <1.0 is satisfied. 4. (DT.W / WT.W) / (WT.L /
DT. 2. The semiconductor memory device according to claim 1, wherein L) <0.9. 5. (DT.W / WT.W) ≧ 1 and
2. The semiconductor memory device according to claim 1, wherein a relationship of (WT.L / DT.L)> 1 is satisfied.