JP2000224039A - DA converter - Google Patents

Abstract

(57) Abstract: Provided is a low-distortion DA converter capable of making the time constants of settling characteristics at the time of rise and fall of the DA converter coincide with each other. A time constant adjusting circuit for adjusting an RC time constant of an analog output terminal according to a digital input code of a DA converter is provided.
It is provided in.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a DA converter for outputting an analog signal corresponding to an arbitrary digital input signal.

[0002]

2. Description of the Related Art A conventional DA converter will be described below with reference to the drawings. FIG. 8 is a circuit diagram showing an example of a conventional DA converter, and shows an n-bit current addition type DA converter. In the figure, reference numeral 81 denotes an n-bit digital input code (D1 to Dn) of the DA converter, and reference numeral 82 denotes ON / OFF of a predetermined current cell circuit according to the digital input code 81.
A decoder for outputting (2 n-1) control signals to be output, 83 a (2 n-1) current cell selection signal output as a control signal from the decoder 82, 84 a current cell selection signal Current cell circuit selected by 83, 85
Is a current cell block composed of (2 n-1) identical current cell circuits 84, 86 is an analog output terminal,
87 is a resistance element having a resistance value R connected between the analog output terminal 86 and the ground potential, and 88 is a capacitance having a capacitance value CL parasitic between the analog output terminal 86 and the ground potential.

FIG. 9 is a circuit diagram of a current cell circuit in the conventional DA converter shown in FIG. In the figure, 91 is a current output terminal, 92 is a current cell selection signal (SEL), 93 is a constant current source for supplying a unit current IE, 94 is a Pch transistor (TP1) which is a non-output side switch, and 95 is a current output A Pch transistor (TR) which is a switch on the terminal 91 side
2), 96 is an inverter, 97 is a Pch transistor (T
R2) is a capacitance that is parasitic on the drain of the transistor 95. The current cell selection signal (SEL) 92 is a Pch transistor (TP1).
In addition to the input to the gate of 94, the inverted signal is input to the gate of the Pch transistor (TP2) 95 via the inverter 96 to control the ON / OFF state of the current cell circuit. With such a circuit configuration, ON →
Match the speed of each state change from OFF, ON to OFF,
The difference in delay time between rising and falling, which causes distortion, is reduced.

FIG. 10 is a diagram for explaining the relationship between the current cell selection signal shown in FIG. 9 and the ON / OFF state of the current cell circuit.
When EL = 1, the Pch transistor (TP1) 94
Since the FF is performed and the Pch transistor (TP2) 95 is turned on, the constant current IE is output to the current output terminal 91, and the current cell circuit is turned on. Conversely, when SEL = 0, the Pch transistor (TP1) 94 is turned on,
Since the transistor (TP2) 95 is turned off, no current flows to the current output terminal 91 and the current cell circuit is turned off.

Next, the operation of the DA converter of the n-bit current addition type shown in FIG. 8 configured as described above will be described. First, by selecting (N 2 -1) current cell circuits 84 that perform the above operation by the number N corresponding to the digital input code, IE × N is applied to the analog output terminal 86.
, And the current is subjected to current-voltage conversion by the resistance element 87 to generate a voltage IE × R × N at the analog output terminal 86. At this time, the settling characteristic until reaching the predetermined output voltage follows the charge / discharge characteristic depending on the RC time constant at the analog output terminal 86. Therefore, in the above-described configuration, the RC time constant is set to the resistance element 87 and the parasitic capacitance 8
8 and (2 to the power of n-1) parasitic capacitances 97. In the output voltage IE × R × N, N changes from 0 to (2 to the power of n−1) according to the digital input code. A DA converter having (2 to the power of n-1) gradation can be realized.

The conversion speed, which is the greatest advantage of such a current addition type D / A converter, is based on the R output of the analog output terminal 86.
The RC time constant at the analog output terminal is one of the most important parameters in the current addition type D / A converter because the settling characteristic is also largely determined by the RC time constant as described above. You can say that.

[0007]

However, in such a configuration, since the output capacitance changes in accordance with the digital input code, the RC time constant in the settling characteristic until the output reaches the predetermined analog output changes. The following problems occur.

FIG. 11 is an explanatory diagram showing an example of a change in output capacitance value with respect to a general digital input, FIG. 12 is an explanatory diagram showing another example of a change in output capacitance value with respect to a general digital input, and FIG. FIG. 14 is an explanatory diagram of a simulation result of a general DA converter when the change of the output capacitance value is in the state shown in FIG. 11, FIG. 14 is an explanatory diagram of the frequency characteristic of the waveform shown in FIG. 13, and FIG. FIG. 16 is an explanatory diagram of a simulation result of a general DA converter when the change is in the state shown in FIG. 12, and FIG. 16 is an explanatory diagram of a frequency characteristic of the waveform shown in FIG. explain.

First, the output capacitance changes because the capacitance Ct of the parasitic capacitance 97 at the drain of the Pch transistor (TP2) 95 in FIG. 9 depends on the gate voltage, that is, the ON / OFF state of the current cell circuit. If the current cell circuit changes from OFF to ON, the parasitic capacitance 97
Is assumed to change by Ct → Ct + Cd, when the number of current cell circuits in the ON state changes from 0 to N, the output capacitance changes by + Cd × N, for example, 10 bits In the case of a DA converter, the output capacitance value changes as shown in FIG. 11 according to the digital input code N. Therefore, when the change of the output analog voltage is large, the RC time constant is significantly different between the rise time and the fall time, and the output waveform of the DA converter is distorted as described below.

When a sine wave of frequency fin and amplitude full scale is input as a digital code to the DA converter, and the DA converter is operated at a conversion frequency five times fin, the simulation result of the output waveform of the DA converter is as follows. As shown in FIG. 13, Ts, which is the unit on the horizontal axis, indicates the conversion period of the DA converter, and the vertical axis indicates the analog voltage output according to the digital input code in LSB units. This DA converter has a constant time constant of 7 times higher than that of falling.
It is set to 0%. FIG. 14 shows the frequency characteristics of the waveform of FIG. 13. As can be seen from FIG. 14, it can be seen that distortion occurs at an integral multiple of the input frequency fin, deteriorating the characteristics of the DA converter. On the other hand, when the output capacitance value is constant irrespective of the digital input code as shown in FIG. 12, the simulation result of the output waveform of the DA converter and its frequency characteristic are as shown in FIGS. 15 and 16, respectively. That is, it can be seen that the distortion as shown in FIGS. 16 to 14 is not generated.

As described above, the above conventional DA converter has a large problem that the RC time constant is greatly different between the rise time and the fall time, and it is inevitable that the output waveform is distorted.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a low-distortion DA converter capable of making the time constants of the settling characteristics at the time of rise and fall of the DA converter coincide with each other. With the goal.

[0013]

The DA converter according to the present invention comprises:
A time constant adjusting circuit capable of adjusting the RC time constant of the output terminal according to the digital input code input to the DA converter is provided at the output terminal.

According to the present invention, since a constant RC time constant can be maintained for an arbitrary digital input code, the time constant in the settling characteristics at the time of rising and falling of the waveform of the analog signal after DA conversion is obtained. , It is possible to reduce the distortion of the DA converter caused by the difference.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing a configuration of a DA converter according to Embodiment 1 of the present invention.
2 shows a configuration of a bit current addition type DA converter. In the figure, reference numeral 11 denotes an n-bit digital input code (D1 to Dn) of a DA converter, and reference numeral 12 denotes a predetermined current cell circuit that is turned on / off in accordance with the digital input code 11 (n−2 in FIG. 2).
A decoder 13 for outputting (1) control signals is output from the decoder 12 as a control signal (2 to the power of n-1).
Current cell selection signals, 14 is a current cell circuit selected by the current cell selection signal 13, and 15 is (2−1
Current cell block composed of the same number of the same current cell circuits 14, 16 is an analog output terminal, 17 is a resistance element having a resistance value R connected between the analog output terminal 16 and the ground potential, and 18 is an analog output terminal. This is the capacitance of the capacitance value CL parasitic between the terminal 16 and the ground potential.
1 has the same configuration and operation as that of the conventional example shown in FIG. 1, and the current cell circuit 14 in FIG. 1 has the same configuration and operation as those shown in FIG. Reference numeral 19 denotes a time constant adjusting circuit capable of adjusting the RC time constant of the analog output terminal 16 according to the digital input code.

FIG. 2 is a first embodiment of a DA converter according to the present invention.
3 is a circuit diagram showing the configuration of the time constant adjusting circuit in FIG. 2. In the figure, reference numeral 21 denotes an n-bit digital input code (D1 to Dn) of a DA converter, and 22 outputs m-bit data using the digital input code 21 as an address ( 2 to the power of n-1) ×
a ROM having a storage capacity of m bits; 23, a capacity cell selection signal output from the ROM 22 as m-bit data;
24 is a capacitance cell circuit selected by the capacitance cell selection signal 23, 25 is a variable capacitance block composed of m identical capacitance cell circuits 24, 26 is an output of each capacitance cell circuit connected to each other, and FIG. This is an analog output terminal connected to the analog output terminal 16. FIG. 3 is a circuit diagram showing a configuration of a capacitance cell circuit according to the first embodiment of the DA converter of the present invention.
L), 32 is a capacitive element, 33 is a switch, and 34 is an output terminal. FIG. 4 is an explanatory diagram of a change in an output capacitance value with respect to a digital input in the DA converter according to the first embodiment of the present invention.

Next, the operation of the D / A converter according to the present embodiment configured as described above will be described. First, the digital input code 11 of FIG.
In the case where the output capacitance that changes depending on the N / OFF state change changes as shown by the curve A in FIG. 4, the number of the m identical capacitive elements 32 selected is controlled to control the straight line B in FIG. As shown in the above, all the codes of the digital input code 11 are stored in the ROM 22 so as to have a constant output capacitance value. By using the ROM 22 and setting the digital input code 11 as an address and the ROM 22 selecting a predetermined number of capacitor cell circuits 24, a constant RC time constant can be maintained for all the digital input codes.

As described above, according to the present embodiment, by providing a time constant adjusting circuit including a ROM for controlling the output capacitance at the analog output terminal, a constant RC time constant can be set for all digital input codes. This makes it possible to hold the data, thereby reducing the distortion of the DA converter.

(Embodiment 2) This embodiment is a modification of the configuration of the time constant adjusting circuit in Embodiment 1 described above, and other configurations and operations are the same as those described in Embodiment 1. Therefore, a duplicate description will be omitted.

FIG. 5 shows a second embodiment of the DA converter according to the present invention.
5 is a circuit diagram showing the configuration of a time constant adjusting circuit in FIG. 5. In the figure, reference numeral 51 denotes an n-bit digital input code (D1 to Dn) of a DA converter, and 52 denotes a digital input code 51 (2
To n-1) control signals, 5
Reference numeral 3 denotes (2 to the (n-1) th) capacity cell selection signals output as control signals from the decoder 52; 54, a capacity cell circuit selected by the capacity cell selection signal 53;
1 is a variable capacity block composed of (n-1) -th same capacity cell circuits 54. Reference numeral 56 denotes an analog output terminal to which the outputs of the respective capacity cell circuits 54 are connected to each other. The analog output terminal 16 shown in FIG. It is connected to.

FIG. 6 shows a DA converter according to a second embodiment of the present invention.
9 is a circuit diagram showing a configuration of a capacity cell circuit in FIG. 7, in which 61 is a capacity cell selection signal (CSEL), 62 is a capacity element, and 63 is the same as the Pch transistor (TP2) 95 in the current cell circuit of FIG. Pch transistor (TP3),
64 is an output terminal, 65 is a Pch transistor (TP3) 6
3 is the parasitic capacitance of the drain. FIG. 7 is an explanatory diagram showing the relationship between the current cell selection signal shown in FIG. 6 and the ON / OFF state of the current cell circuit.

Next, the operation of the DA converter having the above-described configuration according to the present embodiment will be described. First, (2 n-1) current cell circuits 14 and (2 n-1) capacity cell circuits 54 operate in pairs. The ON / OFF state of each of the paired current cell circuit 14 and capacitance cell circuit 54 and the current cell selection signal 92 (S
EL) and the capacitance cell selection signal 61 (CSEL) are as shown in the explanatory diagram of FIG. 7, and when SEL = 1, C
EL = 1, and therefore, as shown in FIGS. 9 and 6, TP1 of each Pch transistor is OFF, TP2 is ON,
Since TP3 is turned off, the current cell circuit is turned on, and the capacity cell circuit is turned off. Conversely, when SEL = 0, CEL =
0, and therefore each Pc as shown in FIGS.
For the h transistor, TP1 is ON, TP2 is OFF, TP
3 turns on, the current cell circuit turns off, and the capacity cell circuit turns on.

As described above, the current cell circuit and the capacitance cell circuit which are paired with each other exist, and when one is turned on, the other is turned off.
It becomes F. Here, since the Pch transistor (TP2) 95 in the current cell circuit and the Pch transistor (TP3) 63 in the capacity cell circuit are the same, the Pch transistor (T
P2) Transistor capacitance 97 parasitic on the drain of 95
Pch transistor (TP3) of the capacitance cell circuit that changes the ON / OFF state of the capacitance value
The capacitance value of the parasitic capacitance 65 parasitic on the drain of 63 changes so as to cancel each other. Here, the capacitance element 62 in the capacitance cell circuit is not for adjusting the capacitance value of the output terminal, but is a capacitance parasitic on the source of the Pch transistor (TP3) 63, and is a Pch transistor (TP2) for the current cell circuit. It is equivalent to the capacitance value parasitic on the source 95 (omitted in FIG. 9).

As described above, according to the present embodiment, by providing the analog output terminal with the time constant adjusting circuit including the current cell circuit and the capacitor cell circuit which are paired with each other, a constant value can be maintained for all digital input codes. Can be held, and the distortion of the DA converter can be reduced.

In this embodiment, by arranging a current cell circuit and a capacitor cell circuit which are paired with each other close to each other on a semiconductor substrate, the transistor characteristics caused by factors such as the stress of the substrate and the manufacturing process are reduced. Variation is minimized, and more accurate capacitance adjustment is possible. Also,
Since the current cell selection signal can be used as it is as the capacitance cell selection signal, the decoder on the input side of the DA converter and the decoder of the time constant adjusting circuit can be used in common, thereby reducing the area of the DA converter. It is possible to do.

[0027]

As described above, according to the present invention, a time constant adjusting circuit capable of adjusting the RC time constant of the output terminal according to the digital input code of the DA converter is provided at the output terminal. The advantageous effect that the distortion of the DA converter can be suppressed extremely low is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a DA converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a time constant adjusting circuit according to the first embodiment of the DA converter of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a capacitance cell circuit in the DA converter according to the first embodiment of the present invention;

FIG. 4 is an explanatory diagram of a change in an output capacitance value with respect to a digital input in the DA converter according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram showing a configuration of a time constant adjusting circuit according to a second embodiment of the DA converter of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a capacitance cell circuit in a DA converter according to a second embodiment of the present invention;

FIG. 7 is an explanatory diagram showing the relationship between the current cell selection signal shown in FIG. 6 and the ON / OFF state of the current cell circuit.

FIG. 8 is a circuit diagram showing an example of a conventional DA converter.

FIG. 9 is a circuit diagram of a current cell circuit in a conventional DA converter.

10 is an explanatory diagram showing the relationship between the current cell selection signal shown in FIG. 9 and the ON / OFF state of the current cell circuit.

FIG. 11 is an explanatory diagram showing an example of a change in output capacitance value with respect to a general digital input;

FIG. 12 is an explanatory diagram showing another example of a change in the output capacitance value with respect to a general digital input.

FIG. 13 is an explanatory diagram of a simulation result of a general DA converter when the output capacitance value changes in the state shown in FIG. 11;

14 is an explanatory diagram of the frequency characteristics of the waveform shown in FIG.

FIG. 15 is an explanatory diagram of a simulation result of a general DA converter when the output capacitance value changes in the state shown in FIG. 12;

16 is an explanatory diagram of the frequency characteristics of the waveform shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Digital input code 12 Decoder 13 Current cell selection signal 14 Current cell circuit 15 Current cell block 16 Analog output terminal 17 Resistor 18 Parasitic capacitance 19 Time constant adjustment circuit 21 Digital input code 22 ROM 23 Capacity cell selection signal 24 Capacity cell circuit 25 Variable capacitance block 26 Analog output terminal 31 Capacitance cell selection signal 32 Capacitance element 33 Switch 34 Output terminal

Claims (3)

[Claims] 1. A decoder circuit for decoding a digital input code and outputting a plurality of control signals, a plurality of current cell circuits including a switch for turning on / off a predetermined unit current by the control signals and a constant current source. The output terminals of the current cell circuits are connected to each other, and the number of current cells corresponding to the digital input code are selected and turned on.
By doing so, a current corresponding to the digital input code is output to the output terminal, and the output terminal can adjust the RC time constant of the output terminal according to the digital input code. A DA converter, comprising a time constant adjusting circuit, wherein an RC time constant of the output terminal is maintained at a constant value. 2. A time constant adjustment circuit comprising: a plurality of capacitance cell circuits each having an output terminal connected to a unit capacitance via a switch;
A ROM storing a control signal for turning on / off the plurality of capacitor cell circuits so as to maintain the total capacity of the output terminal constant regardless of the digital input code, using the digital input code as address data. The DA converter according to claim 1, wherein: 3. The time constant adjusting circuit comprises a decoder circuit for decoding a digital input code of a DA converter and outputting a plurality of control signals, and a switch and a unit capacitor identical to those used in the current cell circuit. And the same number of capacitor cell circuits as the current cell circuits, the output terminals of the respective capacitor cell circuits are connected to each other, and the output terminals of the current cell circuits are always connected to each other by the control signal.
2. The DA according to claim 1, wherein the N / OFF state is reversed so that the total capacitance of the output terminal is kept constant regardless of the digital input code.
converter.