JP2000216843A - Digital demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain satisfactory demodulating characteristic by properly controlling according to the state of a transmission line. SOLUTION: A received signal from the transmission line is sampled by a sampling processing part 10 to obtain a sample value system. A delay quantity estimating part 30 receives a sample value system and obtains an estimated delay quantity EDelay in the transmission line. A selecting control part 40 compares EDelay with a switching threshold to input the sample value system to a delay detector by switching a switch when a delay quantity is small while to input it to an equalizer 60 when the delay quantity is large. A transmission symbol system is estimated by the equalizer 60 and the detector 70.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator of a receiver used for digital communication.

[0002]

2. Description of the Related Art Particularly in the case of communication in which one station moves, such as mobile communication, a transmitting station and a receiving station are connected by a wireless transmission path. On the transmitting station side, the data is converted into transmission symbols by an encoder, and the transmission symbols are complex-modulated to generate a complex baseband signal. The complex baseband signal is transmitted on a carrier wave. On the receiving station side, the received carrier is processed in the reverse procedure to extract data.

[0003] In mobile communication, the relative position between a transmitting station and a receiving station fluctuates. For this reason, the transmission path also varies. In particular, in the case of a mobile communication system such as a mobile phone, fluctuations occur at high speed, so that frequency selective fading is likely to occur. As a result, waveform distortion may occur in the signal received by the receiving station. Generally, an equalizer has been used to compensate for the waveform distortion caused by the transmission line that fluctuates at a high speed.

[0004] A receiving station using an equalizer samples a received complex baseband signal at symbol intervals to generate a sample value sequence. Next, the characteristics of the transmission path are compensated from the generated sample value sequence by the equalizer, and the transmission sample value sequence is estimated. The transmission sample value sequence estimated in this way is decoded by the decoder of the receiving station, and data is extracted.

[0005]

When waveform distortion occurs in a digital transmission line, compensation using delay detection is advantageous in terms of power consumption and demodulation characteristics if the amount of delay generated is small. However, in the delay detection, if there is a large delay amount, the demodulation characteristics are extremely deteriorated. On the other hand, the equalizer has an advantage that the demodulation characteristics do not change even with a large delay amount.
However, when the power consumption is large and the delay amount is small, the demodulation characteristics are inferior to the delay detection.

Therefore, in consideration of the demodulation characteristics when the delay amount is small and the suppression of power consumption, it is necessary to minimize the use of the equalizer and to properly use the delay detection properly. Accordingly, it is an object of the present invention to provide a digital demodulator capable of performing appropriate control according to the state of a transmission path and obtaining good demodulation characteristics.

[0007]

According to the present invention, in order to solve the above-mentioned problems, a digital demodulator detects the presence or absence of a delayed wave generated in a transmission line by observing an output of a correlator for clock recovery. According to the detection result, the delay detection and the equalizer are selectively used.

That is, the digital demodulator of the present invention comprises:
There is a delay amount estimating means for obtaining a delay amount in the transmission path. The delay amount estimating means obtains a correlation between a partial sequence of a sampled value sequence obtained by sampling a received signal and a synchronization sequence for each predetermined observation period. Then, the peak position of the correlation is obtained. Then, the peak position is held for a predetermined observation time, and an upper average and a lower average of the peak position in the observation time zone are obtained. Furthermore, the difference between the upper and lower averages is multiplied by the sampling interval,
Find the amount of delay.

[0009] A digital receiver according to the present invention has a differential detector and an equalizer for estimating a transmission symbol.
Further, there is provided switching means for switching between the delay detector and the equalizer. The switching unit selects the delay detector when the delay amount is equal to or less than the predetermined threshold, and supplies the sample value sequence of the received signal to the delay detector. On the other hand, the switching unit selects the equalizer when the delay amount is equal to or larger than the predetermined threshold, and supplies the sample value sequence of the received signal to the equalizer.

[0010]

Embodiments of the present invention will be described below. FIG. 1 shows a functional block diagram of a digital demodulator according to an embodiment of the present invention. This digital demodulator is provided, for example, in a receiver that receives a signal transmitted from a transmission line of digital mobile communication. This digital demodulator can be implemented by hardware or by a DSP (Digital
SignalProcessor).

The digital demodulator 1 has a sampling processing section 10 for sampling a received signal. The sampling processing unit 10 samples the received signal y (t) from the transmission line, and converts the sampled value sequence {yn} into
Output to the input buffer 20. The sampling processing unit 10 and the input buffer 20 sample and hold the received signal.

The output of the input buffer 20 is provided to the delay amount estimating unit 30 and the switch 4a. Delay amount estimation unit 3
0 receives the sample value sequence {yn} output from the input buffer 20, and estimates the delay amount EDelay in the transmission path. Then, the estimated delay amount EDelay is output to the selection control unit 40. The selection control unit 40 determines the given delay amount
Switch 4a and switch 4b based on EDelay
(Described later).

The output of the switch 4a is connected to an equalizer 60 and a delay detector 70. The outputs of the equalizer 60 and the delay detector 70 are provided to the switch 4b.

The selection control unit 40 compares the estimated delay amount EDelay estimated by the delay amount estimation unit 30 with a threshold value θ. As a result of this comparison, the estimated delay amount EDelay is equal to or smaller than the threshold θ (EDelay ≦
θ), the switch 4a is switched and the input buffer 2
The sample value sequence {yn} output from 0 is connected to the differential detector 60. The delay detector 60 is connected to the input buffer 20.
From the sample value sequence {yn} output from {circle around (1)}. The selection control unit 40 switches the switch 4b at the same time as the switch 4a,
Is output as the output of this digital demodulator.

The selection control unit 40 determines that
When the estimated delay amount EDelay is equal to or larger than the threshold value θ (EDelay ≧ θ), the switch 4 a is switched to connect the sample value sequence {yn} output from the input buffer 20 to the equalizer 50. The equalizer 50 estimates the transmission symbol {Exn} from the sample value sequence {yn} output from the input buffer 20.
Ask for. The selection control unit 40 switches the switch 4b at the same time as the switch 4a, and outputs the output of the equalizer 50 as the output of this digital demodulator.

The output of the switch 4b is connected to, for example, a decoder (not shown). With this decoder,
The estimated transmission symbol {Exn} output from the equalizer 50 or the delay detector 60 is decoded, and the transmitted original data is extracted.

Next, the delay amount estimating section 30 will be described in more detail. The delay amount estimating unit 30 obtains the peak position of the output of the correlator for clock recovery at every predetermined observation period (for example, frame period), and observes the variation to obtain the peak position of the delay amount generated in the transmission path. Make an estimate.

Here, the operation will be described based on the following definitions. Operation start time t0 Fluctuation observation time T1 = T2 × N1 Maximum value observation cycle T2 = Tsmp × N2 Sampling interval Tsmp Sampling value y (k, i) = y (t0 + (k-1) × T2 + i × Tsmp)

FIG. 2 shows a detailed block diagram of the delay amount estimating unit 30. The delay amount estimating unit 30 has a correlation calculating unit 31. The correlation calculation unit 31 calculates a correlation value between the synchronization sequence and a partial sequence of the sample value sequence of the received signal for each maximum value observation cycle. That is, the correlation calculator 31 calculates the correlation value C (k, i) at the time of the k-th maximum value observation cycle. And
The correlation value C (k, i) is output to the maximum correlation detector 32.

Here, the synchronization sequence, the sample value sequence of the received signal, and the partial sequence are represented as follows. Synchronous sequence: {φ1, φ2,..., ΦNt} Sample value sequence of the received signal stored in the input buffer 20: ｛y (k, 1), y (k, 2), ..., y (k , N2)｝ Subsequence: {y (k, i), y (k, i + 1), ..., y (k, (i + Nt-1))}

The maximum correlation detector 32 outputs the correlation value output from the correlation calculator 31 during the k-th maximum value observation cycle.
The maximum correlation value Cmax (k) is searched from C (k, i). When the maximum correlation value Cmax (k) is detected, the maximum correlation detector 32 also obtains the detection position Imax (k). Next, the maximum correlation detector 32 outputs the detected detection position Imax (k) to the detection position buffer 33.

Maximum correlation value in maximum correlation detector 32
The search for Cmax (k) is performed based on Equation 1 below.

The detection position buffer 33 stores the detection position data ｛Imax (k),
, Imax (k−1),..., Imax (k−N1 + 1)｝. This data is provided to the overall average calculator 34, the upper average calculator 35, and the lower average calculator 36. In addition, the output of the overall average calculator 34 is the upper average calculator 35,
And the lower average calculator 36.

The overall average calculator 34 calculates an overall average Avg which is an arithmetic average of the position Imax (k) at which the maximum correlation value Cmax (k) held in the detection position buffer 33 is detected. Next, the upper average calculation unit 35 calculates the position Imax (k) at which the maximum correlation value Cmax (k) held in the detection position buffer 33 is detected.
Of these, the upper average Avg1, which is the arithmetic average of those that are equal to or greater than the overall average Avg, is determined. The lower average calculator 36 calculates the maximum correlation value Cmax (k) held in the detection position buffer 33.
From the detected positions Imax (k), the lower average Avg2, which is the arithmetic average of those below the overall average, is determined.

More specifically, the overall average calculator 34 calculates the overall average Avg based on the following equation (2).

Outputs of the upper average calculator 35 and the lower average calculator 36 are supplied to a subtractor 37. Subtractor 37
Subtracts the lower average from the upper average, and the result of the subtraction is supplied to the multiplier 38. The multiplier 38 calculates the estimated delay EDelay by multiplying the difference between the upper average and the lower average by the sampling interval Tsmp.

That is, the estimated delay amount EDelay is obtained by the following equation (3). Estimated delay amount obtained in this way
The EDelay is provided to the selection control unit 40. EDelay = {Avg1-Avg2} x Tsmp (Equation 3)

FIG. 3 shows an equalizer 60 in this embodiment.
FIG. 2 shows a specific block diagram. As the equalizer 60, an adaptive equalizer can be used. The adaptive equalizer generally has an equalization processing unit 61 and a transmission channel estimation unit 62. The sample value series held in the input buffer 20 is
These are input to the equalization processing section 61 and the transmission path estimation section 62. The output of the equalization processing unit 61 is provided to the switch 4b as an estimated transmission symbol sequence {Exn}, and is also input to the transmission path estimation unit 62.

The transmission path estimating section 62 estimates an impulse response in the transmission path from the input sample value sequence and the estimated transmission symbol sequence estimated by the equalization processing section 61, and uses this as an estimated impulse response sequence. This is given to the processing unit 61. The equalization processing unit 61 performs an equalization process based on the input sample value sequence and the estimated impulse response sequence to generate an estimated transmission symbol sequence.

FIG. 4 shows a specific block diagram of the delay detector 70 in this embodiment. Generally, in the delay detector 70, the sample value sequence given from the input buffer 20 is given to the multiplier 73 and the delay unit 71. The sample value sequence delayed by the delay unit 71 is then input to the conjugate unit 72. In the conjugate unit 72, a complex conjugate of the delayed sample value sequence is obtained.

In this way, the multiplier 73 has the input buffer 2
The sample value sequence given from 0 and the complex conjugate of the delayed sample value sequence are input. Multiplier 73
Multiplies these, and gives the multiplication result to the decision unit 74.
Judgment unit 74 estimates transmission symbols and outputs an estimated transmission symbol sequence {Exn}.

As described above, when the estimated delay amount EDelay is equal to or smaller than the threshold value θ (EDelay ≦ θ), a delay detector is used for estimating a transmission symbol sequence. Therefore, good demodulation characteristics can be obtained without consuming a large amount of power.

On the other hand, the estimated delay amount EDelay is equal to or larger than the threshold value θ (E
If Delay ≧ θ), an equalizer is used for estimating the transmission symbol sequence. Therefore, good demodulation characteristics can be obtained even when the delay amount is large.

The delay amount estimating section 30, the equalizer 60, and the delay detector 70 are not limited to the above-described configuration, but may have various other configurations. Further, it goes without saying that the present invention can be applied not only to mobile communication but also to other digital communication.

[0035]

As described above in detail, according to the present invention, it is possible to appropriately select and use a delay detector and an equalizer according to the delay state of a transmission line. Therefore, when the delay is small, the power consumption is suppressed by using the delay detector, and when the delay is large, by switching to the equalizer, appropriate control is performed according to the state of the transmission line, and the delay is not affected. And good demodulation characteristics can be obtained.

In order to obtain the estimated delay amount EDelay, an overall average, an upper average and a lower average are obtained, and a difference between the upper average and the lower average is multiplied by a sampling interval. For this reason, the delay amount in the transmission path can be accurately estimated without being affected by fading or clock asynchronousness.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital demodulator according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a delay amount estimating unit.

FIG. 3 is a block diagram illustrating an example of an equalizer.

FIG. 4 is a block diagram illustrating an example of a differential detector.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Sampling processing part 20 Input buffer 30 Delay amount estimation part 4a, 4b Switch 40 Selection control part 60 Equalizer 70 Delay detector

Claims (3)

[Claims] 1. A digital demodulator for sampling a received signal received from a transmission path and estimating a transmission symbol, comprising: a delay detector for receiving a sample value sequence of the reception signal and estimating the transmission symbol; An equalizer for receiving the sample value sequence of the received signal and estimating the transmission symbol, further comprising: a delay amount estimating means for obtaining a delay amount in the transmission path; A digital demodulator comprising: switching means for selectively using one of the delay detector and the equalizer based on the delay amount obtained. 2. The digital demodulator according to claim 1, wherein the switching unit selects the delay detector when the delay amount is equal to or less than a predetermined value, and the delay amount is equal to or more than a predetermined value. A digital demodulator, wherein the equalizer is selected in such a case. 3. The digital demodulator according to claim 1, wherein the delay amount estimating means receives a sample value sequence obtained by sampling the received signal, and performs a partial sequence of the sample value sequence for each predetermined observation period. Means for obtaining a correlation between the correlation sequence and the synchronization sequence; means for obtaining a peak position of the correlation; means for holding the peak position for a predetermined observation time; upper average of the peak positions of the correlation held in the holding means; and A digital demodulator comprising: means for calculating a lower average; and arithmetic means for calculating the delay amount by multiplying a difference between the upper average and the lower average by a sampling interval.