JP2000215673A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption required for precharging the bit line by dividing the word line by one bit or a plurality of bits to provide the local word lines, providing a sense amplifier to each block divided and the shortening the activation time of local word lines by non-activating the local word lines for each block based on the sense end signal. SOLUTION: A local word line driver(LWD) 103 for driving a local word line WLr and a sense amplifier 10 including a sense end function are provided to column structure units 100-0 to 100-z which is divided by one or a plurality of memory cell arrays. The local word line driver(LWD) 103 activates the local word line WLr corresponding to the global word line WLg activated with the global word line driver 101 and the local word line WLr is non-activated when the sense end signal FPD is supplied from the sense amplifier 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to divide a word line into one or more bits to form a local word line, provide a sense amplifier for each divided block, and generate a sense amplifier. The present invention relates to a semiconductor memory device in which a local word line of a block is inactivated based on a sense end signal to be reduced to reduce power consumption.

[0002]

2. Description of the Related Art In a synchronous memory circuit, there is widely known a technique for lowering power consumption by lowering a word line before a clock signal falls and stopping an operation of a sense amplifier.

For example, JP-A-8-7573 discloses that
A semiconductor memory device having a small operating current and data reading and writing methods are described. This semiconductor memory device is configured as follows. A NAND gate is provided for outputting an output determination detection signal in response to determination of the complementary output of the latch type sense amplifier. While activating the three-state buffer based on the output confirmation detection signal,
The selected word line is set to a non-selected state. This can prevent a through current from flowing from the power supply line to the ground line in the three-state buffer. Also,
The column current flowing to the memory cell in response to the word line being selected can be minimized.

FIG. 8 is a circuit block diagram of a conventional synchronous memory. FIG. 8 shows an (n + 1) column [(i + 1) *
(N + 1)] word × (z + 1) -bit synchronous memory. Note that z is an odd number. This conventional synchronous memory includes a memory block 500a, a dummy block (dummy cell column block) 500b, and a word line driver 501. The memory block 500a includes (z + 1) column configuration units (CU) 500c.

[0005] The column configuration unit (CU) 500c comprises:
A memory cell array 102, a precharge unit 104,
Column Selector 105 and Sense Amplifier (SA) 10
6 and a write buffer 107. The memory cell array 102 stores a plurality of memory cells MS (i
+1) rows and (n + 1) columns. D [0], D
B [0] is the bit line pair in the first column, D [n], DB
[N] indicates a bit line pair in the (n + 1) th column.

The memory cell MS includes a data storage circuit for storing data, two transmission gate circuits and the like provided between a complementary input / output point of the data storage circuit and a complementary bit line pair. The memory cell MS is connected to a word line WL [0: i].
Is activated (driven to the H level), each transmission gate circuit and the like are turned on. Thus, at the time of reading, a potential corresponding to the storage data is supplied to the bit line pair. Also,
At the time of writing, the data is stored in the data storage circuit based on complementary write data supplied to the bit line pair.

The precharge unit (PC) 104 sets each bit line pair D [0], DB [0] to D [n], DB [n] to a predetermined potential during, for example, the L level period of the clock signal CLK. Level, and each bit line pair D
Equalization (equalization of potential) is performed so that the potentials between [0] and DB [0] to D [n] and DB [n] become the same.

The column selector (CS) 105 selects one bit line pair D [0], DB [0] to D [n], DB [n] based on a column selector signal not shown, Selected bit line pair D [0], DB [0] to D
[N] and DB [n] are connected to a sense amplifier (SA) 106 and a write buffer (WB) 107. In addition,
The column selector (CS) 105 receives the clock signal CL
A counter circuit or the like that advances in synchronization with K, and one bit line pair D based on the count value of the counter circuit or the like.
[0], DB [0] to D [n], and DB [n] may be selected and designated. In this case, there is no need to externally supply a column selector signal.

When a read operation is requested based on read / write mode designation information (not shown), sense amplifier (SA) 106 performs the read operation in synchronization with clock signal CLK. Sense amplifier (SA)
106 differentially amplifies the potential difference between the bit line pair, determines the storage data of the memory cell MS based on the amplified output, and determines the signal of the determined logic level (read data output) DOUT
[0] to DOUT [z] are output.

When a read operation is requested based on read / write mode designation information (not shown), the write buffer (WB) 107 supplies a bit line based on write data inputs DIN [0] to DIN [z]. The pair is driven complementarily. The bit line pair is driven by the clock signal C
This is performed in synchronization with LK.

Dummy block (dummy cell column block)
500b includes a dummy cell array 508, a dummy precharge unit (dummy PC) 509, a dummy column selector unit (dummy CS) 510, and a dummy sense amplifier (dummy SA) 511. Dummy cell array 508
Comprises a plurality of dummy cells DS arranged in (i + 1) rows and one column.

The configuration of the dummy cell DS is the same as that of the memory cell MS. Dummy precharge unit (dummy PC) 50
9 is, for example, during the L level period of the clock signal CLK,
The bit line pairs in the dummy cell column are charged to the H level, and equalization (potential equalization) is performed so that the potential between the bit line pairs in the dummy cell column becomes the same. The dummy column selector unit (dummy CS) 510 connects the bit line pair of the dummy cell column to the dummy sense amplifier (dummy SA) 511 when a read operation is requested based on read / write mode designation information (not shown). .

Dummy sense amplifier (dummy SA) 511
Performs a read operation in synchronization with a clock signal CLK (in synchronization with a rise of the clock signal CLK) when a read operation is requested based on read / write mode designation information (not shown). The dummy sense amplifier (dummy SA) 511 differentially amplifies the potential difference between the bit line pairs in the dummy cell column, and determines the data stored in the dummy cell DS based on the amplified output. The dummy sense amplifier (dummy SA) 511 outputs, for example, an H level sense end signal FPD when data reading from the dummy cell DS is determined. The dummy sense amplifier (dummy SA) 511 stops outputting the sense end signal FPD when the clock signal CLK falls to the L level. The sense end signal FPD is supplied to the word line driver 501.

The word line driver 501 activates one word line WL [0: i] specified based on the address decode output signal A [0: i] in synchronization with, for example, the rising edge of the clock signal CLK ( Drive to H level),
The word line WL activated when the sense end signal FPD is supplied from the dummy sense amplifier (dummy SA) 511
[0: i] is deactivated (pulled down).

The synchronous memory shown in FIG. 8 has a word line WL [0: i] driven by a word line driver 501.
In this configuration, all the memory cells MS and the dummy cells DS are directly connected. Then, the word line driver 5
A dummy block (dummy cell column block) 500b is provided at a position farthest from 01. The dummy sense amplifier (dummy SA) 511 is configured to output a sense end signal FPD. The sense end signal FPD is supplied to the word line driver 501. Then, when the sense end signal FPD is supplied, the word line driver 501 deactivates (pulls down) the activated word line WL [0: i].

Dummy block (dummy cell column block)
Since the memory cell 500b is provided at a position farthest from the word line driver 501, a dummy sense amplifier (dummy SA) is provided after the data stored in the memory cell MS is sensed by the sense amplifier (SA) 106 in the memory block 500a. ) 511 outputs the sense end signal FPD. By supplying this sense end signal FPD to the word line driver 501, the clock signal CL
The word lines WL [0] to WL [i] can fall before K falls. That is, the memory block 5
Immediately after the sensing for the memory cell MS in 00a is completed, the activated word lines WL [0] to WL [i] can fall.

In a state where the word line is activated, the charge of the bit line pair is discharged according to the data stored in the memory cell MS. The amount of charge discharged from the bit line pair increases as the time during which the word line is activated becomes longer. As the amount of discharge increases, the amount of charge charged by precharging increases, and power consumption increases. The synchronous memory shown in FIG. 8 has a memory cell M in a memory block 500a.
Immediately after the sensing for S ends, the sense end signal F
Word lines WL [0] to WL activated based on PD
Since the configuration is such that [i] falls, the activation time of the word line can be reduced, thereby reducing the power consumption required for precharging.

However, the synchronous memory shown in FIG. 8 is configured to drive (z + 1) column configuration units (CU) 500c and dummy blocks 500b with each word line WL [0: i]. The physical length from the driver 501 to the dummy block 500b increases, and the delay time until the sensing end signal FPD is obtained increases. In other words, the word line driver 5
Data reading from the column configuration unit (CU) closest to 01 can be performed at high speed.
Data reading from the column configuration unit (CU) furthest to 1 is slowed down, and the operation speed is reduced in proportion to the number of column configuration units (CU) 500c.

FIG. 9 is a circuit block diagram of another conventional synchronous memory. The synchronous memory shown in FIG. 9 is divided into two memory blocks 600a and 600b in the same column and word configuration as the synchronous memory shown in FIG. It is an improvement. The synchronous memory shown in FIG. 9 includes two memory blocks 600a and 600b, a dummy block 600c, a global word line driver (GWD) 601, and two local word line drivers 602a and 602b.

Global word line driver (GWD) 6
01 is connected to the first local word line driver 602
a and the first memory block 600a are arranged on the other side of the global word line driver (GWD) 601.
Of the local word line driver 602b and the second memory block 600b. The divided memory blocks 600a and 600b are connected to local word lines WLr
[0: i]. Further, a dummy block 600c is arranged outside at least one of the divided memory blocks 600a and 600b. FIG. 9 shows an example in which a dummy block 600c is arranged outside the second memory block 600b.

Global word line driver (GWD) 6
01 is one global word line WLg [0: designated based on the address decode output signal A [0: i].
i] is activated (driven to H level) in synchronization with, for example, the H level period of the clock signal CLK.

The local word line drivers 602a, 60
2b is a plurality of (i + 1) 2-input AND gates G0 to G0.
Gi and an inverter I. These local word line drivers 602a and 602b receive a sense end signal F supplied from a dummy sense amplifier (dummy SA) 511.
When PD is at L level, local word line WLr [0: i] corresponding to activated (driven to H level) global word line WLg [0: i] is activated (driven to H level). If the sense end signal FPD is at the H level, the local word line WLr [0: i] is inactivated (pulled down).

Each of the memory blocks 600a and 600b is
[(Z + 1) / 2] column constituent units (CU) 5
00c. Column configuration unit (C
The configuration of U) 500c is the same as that shown in FIG.
The configuration of the dummy block 600c is the same as that of the dummy block 500b shown in FIG.

FIG. 10 is a timing chart showing a read operation of the synchronous memory shown in FIG. FIG.
FIG. 10A shows the logical level of the clock signal CLK.
10B shows the logic level of the i-th global word line WLg [i], FIG. 10C shows the logic level of the i-th local word line WLr [i], and FIG. 10D shows the sense end signal FPD. Are shown. FIG. 10 (e)
Indicates the potential of the bit line pair D and DB. FIG.
(F) shows the logical level of the read data output DOUT [0] of the column configuration unit (CU) 500c closest to the local word line driver 602a, and FIG. 10 (g) shows the read data of the other column configuration unit (CU) 500c. The logic levels of the outputs DOUT [1] to DOUT [z] are shown. FIG. 10 shows a case where the i-th global word line WLg [i] and the bit line pair D [0] and DB [0] are selected at the time of reading.

After the clock signal CLK shown in FIG. 10A transitions from L level to H level, as shown in FIG. 10B, the global word selected by the address decode output signal A [0: i] The line WLg [i] becomes H level. When the global word line WLg [i] changes from L level to H level, the local word line driver 60
The local word line WLr [i], which is the output of the 2-input AND gate Gi in 2a and 602b, changes from L level to H level as shown in FIG. Thereafter, as shown in FIG. 10E, a potential difference occurs between the pair of bit lines D [0: n] and DB [0: n] according to the data of the selected memory cell. Selected bit line pair D [0], DB [0]
Becomes a constant potential difference, a signal of the read data output DOUT [0: z] is output from each sense amplifier (SA) 106 as shown in FIGS. 10 (f) and 10 (g).

At this time, the column configuration unit (CU) 5 closest to the first local word line driver 602a
00c and the access time tacc until a read data output DOUT [(z + 1) / 2] of the column configuration unit (CU) 500c closest to the second local word line driver 602b is obtained. [0], tacc [(z + 1) /
2] is small. Conversely, the column configuration unit (CU) 50 farthest from the first local word line driver 602a
0c read data output DOUT [((z + 1) /
2) +1] read data output DOUT [((z +
1) / 2) +1], and the column configuration unit (C) farthest from the second local word line driver 602b.
U) An access time tacc [((z + 1) /) until a read data output DOUT [z] of 500c is obtained.
2) +1] and tacc [z] increase. Note that the access time tacc is a time from when the clock signal CLK rises to when the read data output DOUT is obtained, as shown in FIGS. 10 (f) and 10 (g).

Since the dummy block 600c is arranged outside the memory block 600b, the timing at which the H-level sense end signal FPD is output from the dummy sense amplifier (SA) 511 in the dummy block 600c depends on each local word. Line drivers 602a, 602b
Readout data output DOUT [((z + 1) / 2) + of each column configuration unit (CU) 500c furthest from
1], DOUT [z] is output.

As shown in FIG. 10D, when the H level sense end signal FPD is output, each of the two-input AND gates G0 to Gi constituting each of the local word line drivers 602a and 602b shown in FIG. Is supplied with an L-level inverted sense end signal obtained by inverting the H-level sense end signal FPD by the inverter I. Therefore, the local word line WLr
I-th 2-input AN driving [i] to H level
As shown in FIG. 10C, the output of the D gate Gi is L
Pulled down to level.

[0029]

The sense end signal FPD
Becomes H level after the completion of sensing of all bits,
In the column configuration unit (CU) 500c closest to each of the local word line drivers 602a and 602b, the period in which the electric charge of the bit line pair D and DB is discharged based on the data stored in the memory cell MS is the longest, and FIG. As shown in e), the potential difference Vpc between each bit line pair D and DB increases. On the other hand, each local word line driver 602a,
Column configuration unit (CU) 50 farthest from 602b
0c, the charge on the bit line pair D, DB is
Since the period for discharging based on the stored data is short, the potential difference Vpc between each bit line pair D and DB does not need to be so large. For this reason, the power consumption for precharging the bit line pair D and DB increases as the column configuration unit (CU) is closer to the local word line drivers 602a and 602b.

As described above, in the conventional synchronous memory, the period during which the word line is activated becomes longer according to the size of the memory block (the number of memory cell columns). For this reason,
In a memory cell column with a short access time, the potential difference between the bit line pair increases, and the power for precharging the bit line pair increases.

[0031]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problem, and to reduce the potential difference between a pair of bit lines by shortening the activation time of a word line, thereby reducing the power consumption required for bit line precharge. It is an object to provide a semiconductor memory device which is reduced.

[0032]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention is divided for each of the column-constituting units divided into one or a plurality of memory cell columns. A local word line driver for driving a local word line and a sense amplifier having a sense end function are provided, and the local word line driver sets the local word line based on a sense end signal supplied from the sense amplifier. It is configured to be deactivated.

Since the semiconductor memory device according to the present invention includes a local word line driver and a sense amplifier for each column constituent unit, it is possible to deactivate a local word line at the end of sensing for each column constituent unit. it can.

Thus, the activation period of the local word line can be determined for each column constituent unit.
Therefore, the activation period of the local word line can be shortened, and the potential difference between the bit line pair can be prevented from becoming excessive. Therefore, power consumption for precharging the bit line pair can be reduced, and a semiconductor memory device with low power consumption can be provided.

The local word line driver drives a local word line via an AND circuit,
The configuration may be such that the input of the AND circuit is controlled based on the sense end signal to inactivate the local word line. As the AND circuit, for example, a two-input AND gate or the like can be used.

By using a logical product circuit such as a two-input AND gate, a local word line driver can be easily realized with a simple circuit configuration.

The local word line driver may be composed of a transistor for driving the local word line to a high level and a transistor for driving the local word line to a low level.

With such a configuration, the number of transistor elements forming the local word line driver can be reduced, and the chip area of the semiconductor memory device can be reduced.

[0039]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit block diagram of a synchronous memory according to a first embodiment of the semiconductor memory device according to the present invention. FIG. 1 shows an (n + 1) column [(i + 1) * (n +
1)] shows a synchronous memory having a word × (z + 1) bit configuration. Note that z is an odd number. The synchronous memory shown in FIG. 1 includes a memory block 100 and a global word line driver 101. Memory block 100
Represents (z + 1) column constituent units (CU) 100
-0 to 100-z.

Column configuration unit (CU) 100-0
100-z denotes a memory cell array 102, a local word line driver (LWD) 103, a precharge unit (PC) 104, and a column selector unit (CS) 105.
, A write buffer (WB) 107 and a sense amplifier (SA) 108.

The memory cell array 102 has a plurality of memory cells MS arranged in (i + 1) rows and (n + 1) columns. D [0] and DB [0] represent bit line pairs in the first column,
[N] and DB [n] indicate bit line pairs in the (n + 1) th column.

The memory cell MS includes a data storage circuit for storing data, two transmission gate circuits and the like provided between a complementary input / output point of the data storage circuit and a complementary bit line pair. The memory cell MS is connected to the local word line WLr
When [0] to WLr [i] are activated (driven to an H level), each transmission gate circuit and the like are turned on. Thus, at the time of reading, a potential corresponding to the storage data is supplied to the bit line pair. At the time of writing, the data is stored in the data storage circuit based on complementary write data supplied to the bit line pair.

The precharge unit (PC) 104 sets each bit line pair D [0], DB [0] to D [n], DB [n] to a predetermined potential during, for example, the L level period of the clock signal CLK. Level, and each bit line pair D
Equalization (equalization of potential) is performed so that the potentials between [0] and DB [0] to D [n] and DB [n] become the same.

The column selector (CS) 105 selects one bit line pair D [0], DB [0] to D [n], DB [n] based on a column selector signal (not shown). Selected bit line pair D [0], DB [0] to D
[N] and DB [n] are connected to a sense amplifier (SA) 108 and a write buffer (WB) 107. In addition,
The column selector (CS) 105 receives the clock signal CL
A counter circuit or the like that advances in synchronization with K, and one bit line pair D based on the count value of the counter circuit or the like.
[0], DB [0] to D [n], and DB [n] may be selected and designated. In this case, there is no need to externally supply a column selector signal.

When a read operation is requested based on read / write mode designation information (not shown), sense amplifier (SA) 108 performs the read operation in synchronization with clock signal CLK. Sense amplifier (SA)
108 differentially amplifies the potential difference between the bit line pair, determines the storage data of the memory cell MS based on the amplified output, and determines the logic level signal (read data output) DOUT
[0] to DOUT [z] are output.

When the sense amplifier (SA) 108 determines the storage data of the memory cell MS based on the differential amplified output (at the time when the sensing of the memory cell is completed), the sense amplifier (SA) 108 goes high.
It generates and outputs level sense end signals FPD [0] to FPD [z]. Sense end signal FPD [0] to FPD
[Z] is the same column constituent unit (CU) 100-
It is supplied to the local word line driver 103 within 0 to 100-z. When H level sense end signals FPD [0] to FPD [z] are output, sense amplifier (SA) 108 ends H level sense when clock signal CLK falls from H level to L level. Signal FPD
The output of [0] to FPD [z] is stopped (the sense end signal goes to L level).

When a read operation is requested based on read / write mode designation information (not shown), the write buffer (WB) 107 supplies bit lines based on write data inputs DIN [0] to DIN [z]. The pair is driven complementarily. The bit line pair is driven by the clock signal C
This is performed in synchronization with LK.

Global word line driver (GWD) 6
01 is one global word line WLg [0] specified based on the address decode output signal A [0: i].
ＷＬWLg [i] are activated (driven to H level) in synchronization with, for example, the H level period of the clock signal CLK.
Each global word line WLg [0] to WLg [i]
Each column constituent unit (CU) 100-0 to 100-z
Are supplied to the local word line driver 103 in each of them.

The local word line driver 103 has the same number (i + 1) of two-input AND gates G0 to Gi as the number of global word lines WLg [0] to WLg [i], and an inverter I. Each 2-input AND gate G0-G
One input terminal of i is a global word line WLg [0]
To WLg [i]. The H-level sense end signals FPD [0] to FPD [z] are inverted by the inverter I, and the inverted sense end signals are supplied to the other input terminals of the two-input AND gates G0 to Gi. The output terminals of the input AND gates G0 to Gi are connected to the local word lines WLr [0] to WLr [i], respectively.

The local word line driver 103
Any one by global word line driver 101
When one of the global word lines WLg [0] to WLg [i] is activated (driven to the H level), the global word lines WLg [0] to WLg [activated via the two-input AND gates G0 to Gi are activated. The local word lines WLr [0] to WLr [i] corresponding to i] are activated (driven to H level). Then, the local word line driver 103
Are H level sense end signals FPD [0] to FPD
When [z] is supplied, the local word line WLr
[0] to WLr [i] are deactivated (driven to L level).

FIG. 2 is a timing chart showing a read operation of the synchronous memory shown in FIG. FIG. 2A shows the logic level of the clock signal CLK, and FIG. 2B shows the logic level of the i-th global word line WLg [i].
FIG. 2C shows the logic level of the i-th local word line WLr [i], and FIG. 2D shows the inside of the column configuration unit (CU) 100-0 arranged closest to the global word line driver 101. Of the sense end signal FPD [0] output from the sense amplifier 108 of FIG. FIG. 2E shows the potential of the bit line pair D and DB.

FIG. 2F shows the read data output DOUT of the column configuration unit (CU) 100-0 arranged closest to the global word line driver 101.
FIG. 2G shows the logical level of the read data output DOUT [1] to DOUT [z] of the other column configuration units (CU) 100-1 to 100-z. FIG. 2 shows a case where the i-th global word line WLg [i] and the bit line pair D [0], DB [0] are selected at the time of reading.
In FIG. 2, a column configuration unit (CU) 1 arranged closest to the global word line driver 101
Although the timing chart paying attention to the read operation of 00-0 is shown, another column configuration unit (CU) 10
The same applies to the read operation from 0-1 to 100-z.

When the clock signal CLK shown in FIG.
After the transition from the level to the H level, as shown in FIG. 2B, the global word line driver 101 changes the level of the global word line WLg [i] selected by the address decode output signal A [0: i] to the H level. Is driven. The global word line WLg [i] changes from L level to H
When the level becomes the level, the local word line WLr [i], which is the output of the two-input AND gate Gi in the local word line driver 103, changes from the L level to the H level as shown in FIG.

When local word line WLr [i] is activated to an H level and bit line pair D [0] and DB [0] are selected by column selector unit 105, local word line WLr [i] is selected. And bit line pair D [0], DB
[0] selects one memory cell MS.
Thus, as shown in FIG. 2E, the bit line pair D [0], D [0],
A potential difference occurs in DB [0]. Selected bit line pair D
When [0] and DB [0] have a constant potential difference, FIG.
As shown in FIG. 2F, the read data output DOUT [0] is output from the sense amplifier (SA) 108, and the H level sense end signal FPD [0] is output as shown in FIG. 2D. Is done.

H level sense end signal FPD [0]
Is the inverter I in the local word line driver 103
And the inverted sense end signal FPD [0] is supplied to the other input terminal of each of the two-input AND gates G0 to Gi, so that the two-input AND gate Gi which has generated an H-level output up to that time is supplied. Is at L level. Thereby, as shown in FIG. 2C, the local word line W
Lr [i] is inactivated (pulled down to L level).

When the local word line WLr [i] is inactivated (pulled down to L level), the memory cell MS which has been in the selected state until then is in the non-selected state (the data storage circuit in the memory cell). Complementary output terminal and bit line pair D
[0] and DB [0] are disconnected), and as shown in FIG. 2E, the bit line pair D [0] and D [0]
The discharge of the electric charge of B [0] stops.

The access times tacc [0] to tacc [z] from the time when the clock signal CLK rises to the time when the read signals D [0] to D [z] of the stored data are output by the respective sense amplifiers 108 are output. It is known that it differs for each bit (for each column configuration unit). In general, the output bit (column configuration unit) farther from the global word line driver 101 is,
The access time tacc increases. Even within the same column configuration unit, the access time tacc becomes longer as the memory cell column located farther from the local word line driver 103 is selected.

FIGS. 2B to 2F show column configuration units (C) closest to the global word line driver 101.
U) shows an operation waveform of 100-0, in other words, an operation waveform of reading data of the 0th bit. For this reason,
The 0th bit (column configuration unit 10) shown in FIG.
The read signal D [0] of the other bits (other column configuration units 100-1 to 100-1) shown in FIG.
0-z) are output earlier than the read signals D [1] to D [z].

The conventional synchronous memory shown in FIGS. 8 and 9 has a configuration in which the word line is deactivated after the longest access time tacc has elapsed. Therefore, in the column configuration unit requiring a short access time, even if the potential difference between the bit line pair exceeds the potential difference necessary for sensing the stored data, the charge on the bit line pair is discharged. For this reason, power consumption for precharging unnecessarily discharged charges increases.

The synchronous memory shown in FIG. 1 includes a sense amplifier 108 having a sense end detecting function for each column constituent unit (CU) 100-0 to 100z, and stores a memory cell MS to be read. When the sense of the data (read data) is completed, the local word lines WLr [0] to WLr [i] divided for each column constituent unit (CU) 100-0 to 100z are deactivated, so that the read data is read. Immediately after outputting D [0] to D [z], the local word lines WLr [0] to WLr [i] can be deactivated. Thereby, the activation time ton of the local word lines WLr [0] to WLr [i] can be shortened. That is, each column constituent unit (CU)
Local word line WLr every 100-0 to 100z
The activation time ton of [0] to WLr [i] can be reduced.

When the clock signal CLK shown in FIG. 2A goes low, the global word line driver 101
Is, as shown in FIG. 2B, a global word line WL.
g [i] is inactivated (driven to L level). FIG.
As shown in (e), during the precharge period Tpc when the clock signal CLK is at L level, the precharge unit (PC)
The bit line pair D [0] and DB [0] to D [0]
[N] and DB [n] are precharged, the bit line pair potential difference Vpc is equalized (equalized), and the bit line pair is charged (pulled up) to a predetermined precharge potential Vbpc.

The synchronous memory shown in FIG. 1 has an activation time to of local word lines WLr [0] to WLr [i] for each column constituent unit (CU) 100-0 to 100z.
Since n is shortened, the potential difference Vpc between the bit line pair does not become unnecessarily large as shown in FIG. 2E (the charge of the bit line pair is not unnecessarily discharged). . Therefore, the amount of charge required for precharge is reduced, and power consumption required for precharge can be reduced.

FIG. 3 is a circuit diagram showing a specific example of a sense amplifier having a sense end function. This sense amplifier 108 couples two sets of pre-stage differential amplifier circuits 81 and 82 for differentially amplifying the potential difference between the bit line pair D and DB, and the amplified outputs DD and DDB of the pre-stage differential amplifier circuits 81 and 82, respectively. A post-stage differential amplifier circuit 83 that performs differential amplification, an n-channel field-effect transistor (hereinafter, referred to as an n-channel transistor) 84 that operates as a power switch of each of the front-stage differential amplifier circuits 81 and 82, An n-channel field effect transistor (hereinafter, referred to as an n-channel transistor) 85 operating as a power switch of the
And a functional circuit unit 86.

The first pre-stage differential amplifying circuit 81 includes a pair of p-channel transistors P11 and P12 forming an active load of a current mirror configuration, and a pair of n-channel transistors N11 and N12 performing a differential amplifying operation. And a p-channel transistor P13 for short-circuiting the drains of the n-channel transistors N11 and N12 when the clock signal CLK is at the L level.

The potential of one bit line D is supplied to the gate of one n-channel transistor N11. The potential of the other bit line DB is equal to the potential of the other n-channel transistor N1.
2 gates. The drain of one n-channel transistor N11 is connected to one p-channel transistor P
11, and a first differential amplified output DD is taken out from the drain side of one n-channel transistor N11. The drain of the other n-channel transistor N12 is connected to the other p-channel transistor P
12 is connected to the drain. The sources of the n-channel transistors N11 and N12 are interconnected,
N-channel transistor 8 operating as power switch
4 is connected to the drain. The sources of the p-channel transistors P11 and P12 are connected to the positive power supply V +. The gates of the respective p-channel transistors P11 and P12 are connected to each other and to the drain of the other p-channel transistor P12.

The second pre-stage differential amplifier circuit 82 includes a pair of p-channel transistors P21 and P22 forming an active load of a current mirror configuration, and a pair of n-channel transistors N21 and N22 performing a differential amplification operation. And a p-channel transistor P23 for short-circuiting the drains of the n-channel transistors N21 and N22 when the clock signal CLK is at the L level.

The potential of one bit line D is supplied to the gate of one n-channel transistor N21. The potential of the other bit line DB is set to the other n-channel transistor N2
2 gates. The drain of one n-channel transistor N21 is connected to one p-channel transistor P
21 is connected to the drain. The drain of the other n-channel transistor N22 is connected to the drain of the other p-channel transistor P22, and the second differential amplified output DDB is taken out from the drain side of the other n-channel transistor N22. The sources of the n-channel transistors N21 and N22 are interconnected and connected to the drain of an n-channel transistor 84 operating as a power switch. The sources of the p-channel transistors P21 and P22 are respectively connected to the positive power supply V +. The gates of the p-channel transistors P21 and P22 are connected to each other and to the drain of one p-channel transistor P21.

When clock signal CLK is at L level, n-channel transistor 84 operating as a power switch
Is off, and the power supply to each of the pre-stage differential amplifier circuits 81 and 82 is cut off, so that the
1, 82 are in an operation stop state. When the clock signal CLK is at the H level, the n-channel transistor 84 is turned on, and power is supplied to each of the preceding-stage differential amplifier circuits 81 and 82. The p-channel transistors P13 and P23 are turned off by the H level of the clock signal CLK. As a result, each of the first-stage differential amplifier circuits 81 and 82 is in an operating state, the first first-stage amplifier circuit 81 outputs the first differential-amplified output DD, and the second second-stage amplifier circuit 82 outputs the second differential-amplified output. A differential amplified output DDB is output. Here, the differential amplified outputs DD and DDB have a complementary relationship.

The subsequent-stage differential amplifier circuit 83 includes a pair of p-channel transistors P31 and P32 forming an active load of a current mirror configuration, and a pair of n-channel transistors N31 and N32 performing a differential amplification operation.

The first differential amplification output is supplied to the gate of one n-channel transistor N31. The second differential amplified output is supplied to the gate of the other n-channel transistor N32. The drain of one n-channel transistor N31 is connected to the drain of one p-channel transistor P31. The other n-channel transistor N3
2 is connected to the drain of the other p-channel transistor P32 and the read data output D from the drain of the other n-channel transistor N32.
OUT is taken out. Each n-channel transistor N3
The sources of N1 and N32 are connected to each other and to the drain of an n-channel transistor 85 operating as a power switch. Each p-channel transistor P3
1 and P32 are connected to the positive power supply V +. The gates of the p-channel transistors P31 and P32 are connected to each other and to the drain of one p-channel transistor P31.

When clock signal CLK is at L level, n-channel transistor 85 operating as a power switch
Is in an off state, and the power supply to the latter-stage differential amplifier circuit 83 is cut off, so that the latter-stage differential amplifier circuit 83 is in an operation stop state. When the clock signal CLK is at the H level, n
The channel transistor 85 is turned on, and power is supplied to the second-stage differential amplifier circuit 83.
Is in the operating state. The post-stage differential amplifying circuit 83 in the operating state includes the outputs DD,
DDB is differentially amplified to output a read data output DOUT.

The NAND function circuit unit 86 includes a p-channel transistor P61 that pulls up the output line of the first differential amplification output DD when the clock signal CLK is at the L level.
A p-channel transistor P62 for pulling up the output line of the second differential amplified output DDB when the clock signal CLK is at the L level; and a first inverter I61 for inverting the logical level of the first differential amplified output DD. A second inverter I62 for inverting the logic level of the second differential amplified output DDB, and first and second inverters I62 and I62.
It comprises a NOR gate G61 which receives the outputs of 62 as inputs and generates a NOR logic output of those inputs, and a third inverter I63 which inverts the output of the NOR gate G61 and outputs a sense end signal FPD.

When clock signal CLK is at H level, each of p-channel transistors P61 and P62 is off. Therefore, the first differential amplified output DD is supplied to the input terminal of the first inverter I61, and the second differential amplified output DDB is supplied to the input terminal of the second inverter I62. When sensing is performed on the selected memory cell MS and the storage data of the memory cell MS is read, the potential of one of the differential amplification outputs DD and DDB decreases in accordance with the content of the storage data. When the potential difference between the differential amplified outputs DD and DDB exceeds a predetermined potential difference necessary for reliably reading the stored data, the latter-stage differential amplifier circuit 83 outputs the read data output DOUT and ends the sensing.

First and second inverters I61, I6
The input threshold voltage of No. 2 is set in consideration of the condition for ending the sensing. Therefore, when one of the differentially amplified outputs DD, DDB falls to the condition that the potential of the sense ends, the corresponding inverter I61, I62.
Becomes H level. When one of the outputs of the first and second inverters I61 and I62 becomes H level,
The output of the NOR gate G61 goes to L level, and the H level sense end signal FP via the third inverter I63.
D is output.

When the clock signal CLK goes low,
Each of the p-channel transistors P61 and P62 enters an operating state, and pulls up the output line of the first differential amplified output DD and the output line of the second differential amplified output DDB. Therefore, the first and second inverters I
Both the input terminals of 61 and I62 are at the H level, and the outputs of the inverters I61 and I62 are both at the L level.
Therefore, the output of NOR gate G61 attains an H level, and a sense end signal F via third inverter I63.
PD is driven to L level.

As described above, the sense amplifier 1 shown in FIG.
08 starts the sensing operation when the clock signal CLK rises from the L level to the H level, and outputs the H level sense end signal FPD when the read data output DOUT is determined. The H level sense end signal FPD is output until the clock signal CLK falls to L level.

FIG. 4 is a circuit block diagram of a synchronous memory according to a second embodiment of the semiconductor memory device according to the present invention. FIG. 4 shows (n + 1) like the one shown in FIG.
Column [(i + 1) * (n + 1)] word × (z + 1)
2 shows a synchronous memory having a bit configuration. Note that z is an odd number. The synchronous memory shown in FIG. 4 includes a memory block 200 and a global word line driver 101. The memory block 200 includes (z + 1) column configuration units (CU) 200-0 to 200-z.

Column configuration unit (CU) 200-0
200-z is a memory cell array 102, a local word line driver (LWD) 203, a precharge unit (PC) 104, and a column selector unit (CS) 105.
, A write buffer (WB) 107 and a sense amplifier (SA) 108. Column configuration unit (C
U) 200-0 to 200-z are the same as those shown in FIG. 1 except that the configuration of the local word line driver (LWD) 203 is different from that shown in FIG.

Local word line driver (LWD) 20
3 denotes each of the local word lines WLr [0] to WLr [i].
, A p-channel field-effect transistor (hereinafter referred to as p
Channel transistors P0 to Pi) and n-channel field-effect transistors (hereinafter referred to as n-channel transistors) N0 to Ni.

The gate of each of the p-channel transistors P0 to Pi is supplied with a sense end signal FPD. One of the source or the drain of each of the p-channel transistors P0 to Pi is connected to a global word line WLg [0] to WLg [i].
, And the other is connected to the local word lines WLr [0] to Wr.
Lr [i]. Each n-channel transistor N
The sense end signal FPD is supplied to the 0 to Ni gates. The drains of the n-channel transistors N0 to Ni are connected to local word lines WLr [0] to WLr [i]. The sources of the n-channel transistors N0 to Ni are connected to ground (GND) (grounded).

This local word line driver (LWD)
203, when the sense end signal FPD is at the L level, the p-channel transistors P0 to Pi are turned on (conducted) and the global word lines WLg [0] to WLg
g [i] and local word lines WLr [0] to WLr
And [i]. When sense end signal FPD is at L level, n-channel transistors N0 to Ni are off (non-conducting state), and thus local word line WLr [0].
To WLr [i] are at the global word line WLg
It becomes equal to the potential of [0] to WLg [i]. That is,
When sense end signal FPD is at L level, local word lines WLr [0] to WLr [i] corresponding to global word lines WLg [0] to WLg [i] activated by global word line driver 101 are activated. Is done.

When sense end signal FPD is at an H level, p channel transistors P0 to Pi are turned off (non-conductive state) and global word lines WLg [0] to WLg
g [i] and local word lines WLr [0] to WLr
The connection with [i] is cut off, and the n-channel transistors N0 to Ni are turned on (conducting state) to pull down the potentials of the local word lines WLr [0] to WLr [i] to L level. That is, when the sense end signal FPD is at the H level, the local word lines WLr [0] to WLr [0] to
The driving of WLr [i] is stopped (deactivated).

Next, the read operation of the synchronous memory shown in FIG. 4 will be described. Since the operation of the synchronous memory shown in FIG. 4 is the same as the operation of the synchronous memory shown in FIG. 1, the timing chart shown in FIG. 2 will be referred to. The following description of the operation is based on the global word line WLg.
It is assumed that [i] and the bit line pair D [0], DB [0] are selected.

After clock signal CLK rises, global word line WLg [i] is selected based on address decoder output signals A [0: i]. At this time, since global word line WLg [i] is at H level and sense end signal FPD is at L level, local word line Wg [i] is at L level.
Lr [i] becomes H level (is activated). After that, a sense end signal FPD at H level is output from sense amplifier (SA) 108, so that local word line W
Lr [i] falls (becomes inactivated) to the L level.

As a result, the activation time ton of the local word lines WLg [0] to WLg [i] in the synchronous memory shown in FIG. 4 is determined for each read data output bit (column configuration units 200-0 to 200-z). Is shortened to
Therefore, the power consumption required for the bit line precharge can be reduced as in the case of the synchronous memory shown in FIG.

The local word line driver 1 shown in FIG.
03 uses two-input AND gates G0 to Gi. 2
Six transistors are required to constitute the input AND gates G0 to Gi. On the other hand, since the local word line driver 203 shown in FIG. 4 includes two transistors, the chip area can be reduced.

FIG. 5 is a circuit block diagram of a synchronous memory according to a third embodiment of the semiconductor memory device according to the present invention. The synchronous memory shown in FIG. 5 includes a plurality of memory blocks 300 and a global word line driver 101. The memory block 300 includes eight sets of column configuration units (CU) 301-0 to 301 to 7 and one local word line driver (LWD) 302. That is, one local word line driver (LWD) 3
02, the write and read data is 8
The memory block 300 configured in bit units is referred to as ((z
+1) / 8) sets are arranged. Local word line WLr
[0] to WLr [i] are connected to eight (8 bits) memory cell arrays 102.

Column configuration unit (CU) 301-0
Reference numerals 301 to 7 denote a memory cell array 102, a precharge unit (PC) 104, and a column selector unit (CS) 10
5, the sense amplifiers 106 and 108, and the write buffer (WB) 107. First to seventh (0th to 6th bits) column configuration units (CU) 301-
Nos. 0 to 301-6 include the sense amplifier 106 having no sense end detection function, and the eighth (7th bit)
The column configuration unit (CU) 301-7 includes a sense amplifier 108 having a sense end detection function.

The sense amplifier 106 not provided with the sense end detecting function is the same as the sense amplifier shown in FIG.
A circuit configuration excluding the D function circuit unit 86 can be used. The sense end signal FPD generated by the sense amplifier 108 is connected to a local word line driver (LW
D). The local word line driver (LWD) 302 is configured using the two-input AND gate shown in FIG.
103 or a local word line driver (LWD) 2 configured using the field effect transistor shown in FIG.
03 can be used.

Next, the read operation of the synchronous memory shown in FIG. 5 will be described. In this case, the read data 0
To the 7th bit, the global word line WL
The read operation will be described on the assumption that g [i] is selected.

FIG. 6 is a timing chart showing a read operation of the synchronous memory shown in FIG. 6A shows the logic level of the clock signal CLK, FIG. 6B shows the logic level of the i-th global word line WLg [i],
FIG. 6C shows the logic level of the i-th local word line WLr [i], and FIG. 6D shows the logic level output from the sense amplifier (sense amplifier for the seventh bit of read data) 108 having a sense end detection function. Indicates the logic level of the sense end signal FPD. FIG. 6E shows a bit line pair D, D
The potential of B is shown. FIG. 6F shows the logical level of the read data output DOUT [0] of the seventh bit in FIG.
(G) is a read data output DOUT of the 0th to 6th bits.
The logic level of [0] is shown.

When the clock signal CLK shown in FIG. 6A rises, the global word line driver 101 causes the address decode output signal A as shown in FIG.
The global word line WLg [i] selected and designated based on [0: i] is driven to H level (activated).
The local word line driver 302 outputs the sense end signal F
Since PD is at L level, global word line WLg
Based on the H level of [i], the local word line WLr [i] is driven to H level (activated) as shown in FIG. 6C.

As shown in FIG. 6 (g), after the sense amplifier 106 sequentially outputs the read data outputs D [0] to D [6] from the 0th bit to the 6th bit, FIG. ), The seventh bit read data output D from the sense amplifier 108 having the sense end function.
[7] is output and the H level sense end signal FP is output from the sense amplifier 108 as shown in FIG.
D is output. This H level sense end signal FPD
Are supplied to the local word line driver 302. The local word line driver 302 outputs the sense end signal FPD
Is driven to the H level, the local word line WLr [i] is driven to the L level (deactivated), as shown in FIG.

As a result, the activation time ton of the local word lines WLg [0]-[i] in the synchronous memory shown in FIG. 5 is reduced to every 8 bits of read data (each memory block 300). Therefore, power consumption required for bit line precharge can be reduced.

The synchronous memory shown in FIG. 5 can reduce the number of local word line drivers 302 as compared with the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. In addition, the chip area of the synchronous memory can be reduced.

FIG. 7 is a circuit block diagram of a synchronous memory according to a fourth embodiment of the semiconductor memory device according to the present invention. The synchronous memory shown in FIG. 7 includes a plurality of memory blocks 400 and a global word line driver 101. The memory block 400 includes eight sets of column configuration units (CU) 401-0 to 401 to 7 and one local word line driver (LWD) 302. That is, one local word line driver (LWD) 3
02, the write and read data is 8
A memory block 400 composed of bits is assigned to ((z
+1) / 8) sets are arranged. Local word line WLr
[0] to WLr [i] are connected to eight (8 bits) memory cell arrays 102.

Column configuration unit (CU) 401-0-0
Reference numerals 401 to 7 denote a memory cell array 102, a precharge unit (PC) 104, and a column selector unit (CS) 10
5, a write buffer (WB) 107, and a sense amplifier 108 having a sense end detection function.

The synchronous memory shown in FIG. 7 differs from the synchronous memory shown in FIG. 5 in that all the sense amplifiers 108 detect the end of sense. Sense end signals FPD [0] to outputted from each sense amplifier 108
FPD [7] is supplied to each input of an 8-input AND gate 303, and the output of the 8-input AND gate 303 is supplied to the local word line driver 302 as an in-block sense end signal. That is, the synchronous memory shown in FIG. 7 has eight column configuration units (CU) 401.
At the point in time when all of −0 to 401 to 7 have been read, the in-block sense end signal is set to the H level, and the active local word lines WLr [0] to WLr [i] are deactivated. Things.

Next, the read operation of the synchronous memory shown in FIG. 7 is focused on the 0th to 7th bits of the read data, and it is assumed that the global word line WLg [i] is selected. explain. The basic operation of the synchronous memory shown in FIG. 7 is the same as the read operation of the synchronous memory shown in FIG. 5, but the characteristic of the read operation of the synchronous memory shown in FIG. Word line W
The point that Lr [i] falls (inactivates) at the time when all eight sense end signals FPD [0] to FPD [7] are at the H level. In other words, the activation time ton of the local word lines WLr [0] to [i] is determined according to the timing at which the end of sensing is the latest among the 8-bit read data.

As a result, the synchronous memory shown in FIG.
Similarly to the synchronous memory shown in FIG. 5, the activation time ton of the local word lines WLr [0] to [i] can be reduced to every eight bits of read data (each memory block 400). Therefore, power consumption required for bit line precharge can be reduced.

Further, the synchronous memory shown in FIG.
Similarly to the synchronous memory shown in FIG. 1, the number of local word line drivers 302 can be reduced as compared with the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. The chip area of the memory can be made smaller.

Further, the synchronous memory shown in FIG.
−0 to 401-7, even if the sense end is delayed, the local word line WL is adjusted to the latest sense end timing.
It is possible to automatically lower r [0] to [i]. Therefore, for example, even when the read data output timing of the other bits is later than the read data output timing of the seventh bit, the read data of each bit can be reliably output.

[0104]

As described above, the semiconductor memory device according to the present invention drives a local word line divided for each column constituent unit for each column constituent unit divided for one or a plurality of memory cell columns. Since the local word line driver and the sense amplifier having the sense end function are provided, the local word line can be deactivated at the end of the sense for each column constituent unit. Thus, the activation period of the local word line can be determined for each column constituent unit. Therefore, the activation period of the local word line can be shortened, and the potential difference between the bit line pair can be prevented from becoming excessive. Therefore, power consumption for precharging the bit line pair can be reduced, and a semiconductor memory device with low power consumption can be provided.

By configuring a local word line driver using an AND circuit such as a two-input AND gate, the circuit configuration of the local word line driver can be simplified. Further, by configuring the local word line driver with a transistor for driving the local word line to a high level and a transistor for driving the local word line to a low level, the number of transistor elements constituting the local word line driver can be reduced. And the chip area of the semiconductor memory device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a synchronous memory according to a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart showing a read operation of the synchronous memory shown in FIG.

FIG. 3 is a circuit configuration diagram showing a specific example of a sense amplifier having a sense end function.

FIG. 4 is a circuit block diagram of a synchronous memory according to a second embodiment of the semiconductor memory device according to the present invention;

FIG. 5 is a circuit block diagram of a synchronous memory according to a third embodiment of the semiconductor memory device according to the present invention;

FIG. 6 is a timing chart showing a read operation of the synchronous memory shown in FIG. 5;

FIG. 7 is a circuit block diagram of a synchronous memory according to a fourth embodiment of the semiconductor memory device according to the present invention;

FIG. 8 is a circuit block diagram of a conventional synchronous memory.

FIG. 9 is a circuit block diagram of another conventional synchronous memory.

FIG. 10 is a timing chart showing a read operation of the synchronous memory shown in FIG. 9;

[Explanation of symbols]

100, 200, 300, 400 memory blocks 100-0 to 100-z, 200-0 to 200-z, 3
01-0 to 301-7, 401-0 to 401-7 Column configuration unit 101 Global word line driver 102 Memory cell array 103, 203, 302 Local word line driver 104 Precharge unit 105 Column selector unit 106 Sense amplifier (sense end detection) No function) 107 Write buffer 108 Sense amplifier with sense end detection function G0-Gi 2-input AND gate N0-Ni n-channel field effect transistor P0-Pi p-channel field effect transistor

Claims (6)

[Claims] 1. A local word line driver for driving a local word line divided for each column constituent unit for each column constituent unit divided by one or a plurality of memory cell columns, and a sense having a sense end function. And a local word line driver configured to deactivate the local word line based on a sense end signal supplied from the sense amplifier. 2. The local word line driver drives the local word line through an AND circuit, and controls the input of the AND circuit based on the sense end signal to thereby disable the local word line. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is activated. 3. The local word line driver according to claim 1, wherein said local word line driver comprises a transistor for driving said local word line to a high level and a transistor for driving said local word line to a low level. Semiconductor storage device. 4. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a synchronous memory. 5. The semiconductor memory device according to claim 2, wherein said AND circuit is a two-input AND gate. 6. The semiconductor memory device according to claim 3, wherein said transistor is an n-channel field-effect transistor or a p-channel field-effect transistor.