JP2000215226A - Logic verification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time required for logic verification by exchanging the operated result of verification on a logic to be verified between a hardware emulator and a software simulator. SOLUTION: The software simulator 1 reads logic information held on a recording medium 4 and corresponding to the abstraction level of each module in that logic information, the logic information is divided into a module to be verified by a hardware emulator 2 and a module to be verified by the software simulator 1. At the time of verification, according to this connection relation, the exchange of input data or operated result for logic operation is executed through communication equipment 3 between the software simulator 1 and the hardware emulator 2. Thus, the time required for logic verification can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logic verification device for verifying a logic circuit by using a software simulator and a hardware emulator together.

[0002]

2. Description of the Related Art Advances in semiconductor technology have led to the development of logic LSIs.
(Large Scale Integrated circuit) has been improved year by year, and large-scale systems can be integrated into one chip, and systems such as electronic devices can be built with one or several chips of LSI. It is getting.

[0003] The manufacturing cost of an LSI is extremely high, and the manufacturing period requires one month or more.
It is important to conduct a thorough verification before manufacturing.

[0004] Verification occurs during various phases of the design. The design process takes many steps from an abstract level in the initial design to a detailed manufacturing level in the final step, and handles logical information corresponding to each level. For example, at the initial design stage, abstract level logic information that determines the degree of input / output relationship, at the function design stage, function level logic information that determines the function of each logical part, and at the final detailed design stage, the structure that determines the logical structure Level logical information is handled. It is possible to express the above-described logic information at various design stages by various commonly used hardware description languages (HDL).

Conventionally, a method of verifying the logic of an LSI or a system using a plurality of LSIs includes a method using a software simulator and a method using a hardware emulator. Generally, software simulators are HDL
Since the logical information described in (1) is executed as a computer program, it can be used in various design stages and is widely used in many fields. On the other hand, the hardware emulator is an FPGA (Field Programmable G
ate Array) or FPID (Field ProgrammableInterconn)
ect Device), and is a device capable of reconfiguring a logical structure based on an externally input signal. Since the device is hardware, it is possible to execute a logical operation at high speed and in parallel.

FIG. 5 is a diagram showing a conventional hardware logic emulation system. In the figure, 201
Is a management computer such as a workstation or a personal computer that reads logical information of an LSI to be verified from a predetermined recording medium 204, converts the logical information into data for the emulation device 202, and supplies the data to the emulation device 202. 202 indicates a plurality of FPs
The emulation device is configured by the GA 221 and the FPID 222, and reconfigures a logical structure based on data from the management computer 201. Reference numeral 205 denotes an external device including a CPU 231, a memory 232, and another LSI 233, which are components related to a logic LSI to be verified by the emulation device 202.

Next, the operation will be described. FIG. 6 shows FIG.
9 is a flowchart for explaining the operation of the management computer of FIG. As shown in FIG. 6, the management computer 201
Reads the logic information of the LSI to be verified from the predetermined recording medium 204 (step ST21), compiles the logic information, and compiles the FP of the emulation device 202.
The structure data for the GA 221 and the structure data for the FPID 222 are generated (step ST22), and the data is supplied to the emulation device 202.

[0008] The emulation device 202
The logic of the LSI to be verified is emulated based on the structural data. At the time of logic verification, input data is supplied from the management computer 201, a logical operation is performed on the input data, and the result of the operation is output. Also, at the time of logic verification, depending on the logic to be verified, the external device 20
5 is also executed.

Next, FIG. 7 shows, for example, Japanese Patent Application Laid-Open No. 10-171.
FIG. 1 is a block diagram illustrating a configuration of a first conventional logic verification device described in Japanese Unexamined Patent Publication No. 847-847. In the figure, reference numeral 310 denotes an FPGA device that emulates a logic to be verified, and 3
Numeral 14 denotes a simulation module for simulating the logic to be verified. Numeral 312 denotes each FPGA device 3.
10 and FPGA of each simulation module 314
322 is a programmable interconnect that connects
A system controller 326 is connected to the system bus 328 and executes downloading of structural data to the FPGA device 310 and the simulation module 314.

In the simulation module 314, 320 is a RAM for storing logic information and the like expressed by the action description, 316 is a CPU for executing the logic to be verified expressed by the action description for each fragment, 322 is an FPGA that determines the fragments to be executed and their order, and 318 is an RA
M320, a microprocessor bus for interconnecting the CPU 316 and the FPGA 322, and 324 a microprocessor bus 318 and a system bus 328
Is a bus controller connected to.

Next, the operation will be described. In the first conventional logic verification device, the CPU 316 simulates the logic to be verified based on the logic information expressed by the action description. At this time, the logic to be verified is all emulated by the FPGA device 310 and the FPGA 322 in a logical structure based on the structure data from the system controller 326. Then, the programmable interconnector 312 appropriately executes communication between the FPGA 310 device and the FPGA 322.

As described above, in the first conventional logic verification device shown in FIG. 7, the FPGA device 310 and the FPGA 322
Emulates all of the logic to be verified.

FIG. 8 shows, for example, Japanese Patent Application Laid-Open No. 9-2930.
FIG. 2 is a block diagram showing a configuration of a second conventional logic verification device described in Japanese Patent Application Publication No. 02-2002. In the figure, reference numeral 402 denotes a control circuit 504 and a memory 52 for storing a target program 522.
6, a processor emulator that models the target processor and the target program, 406 is a hardware simulator that has a processor model shell 510 that models the target circuit, and 410 is a translator 414 and a mapper. 416 is a software kernel. Translator 414 performs format conversion between the first data format for processor emulator 402 and the intermediate data format, and mapper 416 performs format conversion between the second data format for hardware simulator 406 and the intermediate data format. Performs format conversion. Note that the hardware simulator 406 and the software kernel 410 are realized as software.

Reference numeral 420 denotes a hardware simulator 40
Reference numeral 422 denotes a communication link connecting the processor emulator 402 and the software kernel 410.

Next, the operation will be described. The hardware simulator 406 operates to give an external hardware response to the processing based on the target program 522. At this time, the processor model shell 510 synchronizes communication between the hardware simulator 406 and the software kernel 410.

The software kernel 410 includes a hardware simulator 406 and a processor emulator 4
02 is executed while appropriately performing the format conversion described above.

The processor emulator 402 executes the target program 522 and executes the software kernel 410
The communication with the hardware simulator 406 is executed as necessary.

As described above, in the second conventional logic verification apparatus shown in FIG. 8, the target circuit is simulated by the hardware simulator 406, and the processor emulator 4
At 02, the target processor and the target program are emulated, and communication between the target processor and the target program is appropriately performed, thereby simulating the interaction between the target circuit and the target processor and the target program.

As another logic simulator, there is one described in JP-A-6-96151.

[0020]

Since the conventional logic verification apparatus is configured as described above, in order to emulate all of the logic to be verified by the hardware emulator, the logic information is determined to the structure level. It is difficult to perform verification until the final stage of the design, and if a design defect is found, the process must return to the initial stage of the design. There were problems such as difficulty in shortening the period.

When only a software simulator is used for verification, logic verification based on the logic information can be executed while flexibly corresponding to logic information of various levels of abstraction. Becomes larger, the processing time required for verification increases. Further, for example, 1
In order to perform verification to improve the design quality of an LSI with over one million gates or the whole system including it, it is necessary to perform function verification at least for each application such as image processing related or communication related. Since the processing time required to verify the application scale is large, it is difficult to execute the verification in a realistic period. Also, CP
Software modeling of general-purpose components such as U is difficult, and it is difficult to faithfully simulate a system to be verified.

Further, in the first conventional logic verification apparatus, since all the logic to be verified is emulated by hardware, when a simulation is executed based on abstract-level logic information in an initial design stage,
A simulation that faithfully reflects the logic information may not be executed. In general, when designing a large-scale logic, the logic is divided into modules, and the design progresses on a module-by-module basis. The level may be different, but in such a case the first
In the conventional logic verification apparatus of the related art, there is a possibility that the simulation that faithfully reflects the logic information is not executed.

Further, in the second conventional logic verification apparatus, the target circuit is simulated by the hardware simulator 406 and the processor emulator 402
By emulating the target processor and the target program in, and appropriately performing communication between the two, the target circuit and the interaction between the target processor and the target program are simulated. It is almost limited to processors, and what is simulated by software is the peripheral circuits of the processor, and it is difficult to execute simulation and emulation according to the progress of design.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. A portion of logic information, which has been determined up to the structure level, is verified by a hardware emulator, and the other portions are verified by a software simulator. It is an object of the present invention to obtain a logic verification device that performs verification by using the following.

That is, for example, in the development of a large-scale LSI, the whole logic is divided into a plurality of modules, and each module is developed by a plurality of designers. Therefore, the design phase is generally different for each module, and an object of the present invention is to provide a logic verification device capable of executing logic verification even in such a situation.

[0026]

A logic verification apparatus according to the present invention includes a reconfigurable hardware emulator for performing verification on a predetermined first part of a logic to be verified,
A software simulator having storage means for storing a simulation program describing a simulation of the logic to be verified, and arithmetic processing means for executing the simulation program and verifying the remaining second part of the logic to be verified; A communication unit is provided between the emulator and the software simulator for transmitting and receiving the operation result of the verification of the verified logic.

According to the logic verification apparatus of the present invention, a first part for verifying a logic to be verified by a hardware emulator and a second part for verifying the logic by a software simulator are provided according to the level of abstraction of the logic to be verified. Is to be divided.

The logic verification apparatus according to the present invention divides data transmitted and received between the first part and the second part in units of the same number of bits as the bus width of the interface with the communication unit. It is like that.

[0029] In the logic verification device according to the present invention, the software simulator transmits the operation result of the verification to the communication unit,
The communication unit supplies the calculation result of the verification from the software simulator to the hardware emulator, and the hardware emulator executes the verification using the calculation result of the verification by the software simulator as data.

In the logic verifying apparatus according to the present invention, the software simulator performs verification at a timing at which the transfer time of the verification calculation result is shorter among timings at which the value of the verification calculation result changes and timings at each clock. Is transmitted to the communication unit.

In the logic verification apparatus according to the present invention, when a calculation result of verification by a software simulator is supplied, a hardware emulator executes verification for one event.

In the logic verification apparatus according to the present invention, when the operation result of the verification by the software simulator is supplied, the hardware emulator executes the verification from time 0 to the time corresponding to the operation result of the verification. Things.

The logic verification device according to the present invention has a communication unit having a buffer memory for storing the operation result of the logic to be verified from the software simulator until it is supplied to the hardware emulator.

The logic verification apparatus according to the present invention has the communication unit having first control means for controlling the timing of supplying the operation result of the logic to be verified from the software simulator to the hardware emulator.

The logic verification apparatus according to the present invention has a communication unit having second control means for controlling the clock of the hardware emulator to synchronize the processing in the software simulator and the processing in the hardware emulator. is there.

In the logic verification apparatus according to the present invention, the communication unit controls a predetermined external device connected to the hardware emulator, and synchronizes the processing in the predetermined external device with the processing in the hardware emulator. Control means.

The logic verification apparatus according to the present invention transmits all input data to the verified logic to the communication unit when all of the verified logic is the first part to be verified by the hardware emulator. Accumulates data from a software simulator and supplies it to a hardware emulator, and the hardware emulator uses the data to execute verification of all of the logic to be verified.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a logic verification apparatus according to Embodiment 1 of the present invention, and FIG.
FIG. 2 is a block diagram illustrating a detailed configuration example of the communication device in FIG. 1. In FIG. 1, reference numeral 1 denotes a software simulator such as a workstation or a personal computer that stores a simulation program in a memory 12 and executes the program by a CPU 11. 2 is FPGA
It is a hardware emulator that has a processor and the like in addition to a programmable device such as an FPGA and an FPID, and executes emulation of logic based on supplied structural-level logic information. Reference numeral 3 denotes a communication device (communication unit) that executes communication such as a calculation result of verification between the software simulator 1 and the hardware emulator 2 while buffering a difference in processing speed. Reference numeral 4 denotes a recording medium that holds logical information of the logic to be verified. Reference numeral 5 denotes a CPU 31, a memory 32, and other LSIs 33, which are components related to a logic LSI to be verified by the hardware emulator 2.
It is an external device provided with the above. Reference numeral 6 denotes a computer network such as Ethernet (registered trademark).

In the software simulator 1, 1
1 is a CPU that executes a simulation program
(Arithmetic processing means), 12 is a memory (storage means) such as a RAM for temporarily storing a simulation program and logic information, and 13 is connected to the computer network 6 and executes transmission and reception of data as required 14 is a recording medium 4
An interface 15 reads and writes data from and to a CPU (Peripheral Component Interface) that connects the CPU 11, the memory 12, the network interface 13 and the interface 14 to each other.
ect) A system bus such as a bus. The system bus 15 is not limited to the PCI bus, but may be another higher-speed bus (interface).

In the hardware emulator 2, 2
Reference numeral 1 denotes a logic operation unit having an FPGA, an FPID, a processor, and the like, which can be reconfigured under the control of the control unit 22. And a control unit 23 for setting the logical configuration of the logical operation unit 21. A network interface 23 is connected to the computer network 6 and executes transmission and reception of data as necessary.

In the communication device 3 (FIG. 2), reference numeral 41 denotes a bus control unit for reading / writing data from / to the buffer memory 42 and controlling transmission / reception of data to / from the software simulator 1; And a buffer memory 43 for temporarily storing data from the hardware emulator 2 and for storing operation results from the hardware emulator 2.
An emulator control unit (first control unit) that controls the timing at which the data stored in the buffer memory 42 is supplied to the hardware emulator 2 and 44 is a bus control unit 41, a buffer memory, 42, a clock to be supplied to the emulator control unit 43, and a clock to be supplied to the external device control unit 45, respectively, buffer the difference in processing speed between the software simulator 1 and the hardware emulator 2 to synchronize them, and A clock control unit (second control unit) that buffers the difference in processing speed between the external device 5 and the hardware emulator 2 and synchronizes the two with each other. Is an external device control unit (third control means) that controls the processing speed of the external device.

In the buffer memory 42, the difference in processing speed between the software simulator 1 and the hardware emulator 2 and the test pattern to be executed are specified in consideration of the bus width of the system bus 15 connected to the software simulator 1. It is preferable to use one having a capacity taking into consideration the number and the like.

Since the external device 5 is the same as the actual device, it can operate at the same speed as the actual device. However, in the hardware emulator 2, the logical operation unit 21 emulates the target logic. Since it is difficult to operate at the same speed as the actual device, control is performed so that the external device 5 is synchronized with the hardware emulator 2 as described above.
Similarly, since the processing speed of the software simulator 1 is lower than the processing speed of the hardware emulator 2, the calculation result of the verification is temporarily stored in the buffer memory 42 to synchronize them.

Next, the operation will be described. FIG. 3 is a flowchart illustrating an operation of the logic verification device according to the first embodiment.

First, in step ST1, the software simulator 1 reads logical information held in the recording medium 4. This logical information is created for each predetermined module by a designer. The abstraction level of the logical information of each module is the above-described abstraction level, function level, structure level, and the like, and may be different levels.

Next, in step ST2, the software simulator 1 includes a module (first part) for verifying the logic information by the hardware emulator 2 according to the level of abstraction of each module of the logic information, 1 and a module to be verified (second part). That is, a module whose structural level logical information is determined is verified by the hardware emulator 2, and a module whose structural level logical information is not determined is verified by the software simulator 1. When the logical information is determined up to the structure level, the hardware emulator 2 performs the verification at high speed. However, when it is desired to observe the details of the behavior, the verification may be executed by the software simulator 1. Even when the logic information of a module is described at an abstract level, if the hardware emulator 2 is provided with the actual components of the module, the hardware emulator 2 can execute the verification of the module. .

After the division of the logical information, in step ST3, the software simulator 1 executes the reconstruction of the divided logical information. That is, the connection relationship between the module verified by the software simulator 1 and the module verified by the hardware emulator 2 is set. At the time of verification, transmission and reception of input data for logical operations and operation results are executed between the software simulator 1 and the hardware emulator 2 via the communication device 3 in accordance with the connection relationship.

In step ST4, the software simulator 1 allocates input / output signals between modules exchanged between the software simulator 1 and the hardware emulator 2 based on the specifications of the system bus 15 and the like. That is, when the system bus 15 is, for example, a 32-bit PCI bus, the software simulator 1 transmits an input / output signal between modules (between the module of the first part and the module of the second part) to 32 bits. For each transmission, the order of transmission and reception is determined.

FIG. 4 is a diagram showing an example of a module verified by the software simulator 1. In the figure, 101 to 103 are output signals of the hardware emulator 2, that is, input signals to the software simulator 1, 110 to 112 are output signals of the software simulator 1, 104 to 108 are registers, and 150 are other , And 120 and 121 are combinational circuits. Output signals 110 to 112 of the software simulator 1 are stored in registers 106 to 108
Is output from each. Clock 1 of register 106
09 is generated by the internal logic 150 and the register 10
The clocks 7 and 108 are the input signal 103. The output signal 111 is delayed by the combination circuit 120.

Therefore, since the output timings of the output signals 110 to 112 are different from each other, in step ST4, the signals output at the same timing are divided into the same group as much as possible to Should be reduced.

Next, in step ST5, the software simulator 1 executes setup of the hardware emulator 2. That is, the software simulator 1 controls the control unit 2 of the hardware emulator 2 via the communication device 3 or the computer network 6.
2, the logic information of the module to be verified by the hardware emulator 2 is supplied, and the logic structure of the logic operation unit 21 is set based on the logic information.

After the preparation for verification is completed as described above,
Start verification. That is, at this point, the simulation program is started in the software simulator 1 to start verification, and the software simulator 1
Executes a simulation (step ST6).
Then, the operation result (output signal) by the software simulator 1 is transmitted to the hardware emulator 2 via the communication device 3 (step ST7), and the hardware emulator 2 receives the signal and executes a logical operation (step ST8). The calculation result (output signal) is transmitted to the software simulator 1 via the communication device 3 (step ST9). Hereinafter, the software simulator 1 and the hardware emulator 2 alternately execute logical operations until the simulation is completed (step ST10).

For example, the system bus 15 and the bus between the communication device 3 and the hardware emulator 2 are PCI buses, and input / output signals between the modules are 100 buses.
If it is a book (ie, 100 bits), the time required for communication is several hundred nanoseconds. Software simulator 1 processing speed (simulation progress speed) is 10
0 Hertz (1 clock cycle is 10 ms),
When the processing speed of the hardware emulator 2 is 10 megahertz (one clock cycle is 100 nanoseconds), the communication speed is sufficiently higher than the processing speed of the software simulator 1, so that the delay due to communication does not cause any particular problem.

Next, the operation of the communication device 3 will be described in detail. When receiving the data (output signal) from the software simulator 1, the bus control unit 41 writes the data (output signal) in the buffer memory 42. Then, the emulator control unit 43 reads the data and supplies the data to the hardware emulator 2 at a predetermined timing. For example, the output signal 111 in FIG. 4 is delayed by the combinational circuit 120, but the data transfer is performed simultaneously with the other output signals 112. Therefore, the emulator control unit 43 shifts the output signal 111 by shifting the timing by the delay by the combinational circuit 120. It is supplied to the hardware emulator 2. It should be noted that such information on the delay of each signal is calculated by the software simulator 1 at the time of the reconfiguration in step ST3, for example, and is supplied in advance before performing the verification.

On the other hand, when the emulator control unit 43 receives the data (output signal) from the hardware emulator 2, it writes it into the buffer memory 42. Bus control unit 41
Transmits the data to the software simulator 1.

The clock control unit 44 controls the clock of the hardware emulator 2 in order to synchronize the hardware emulator 2 and the software simulator 1, and during the period when the software simulator 1 is performing a logical operation, Then, the logical operation by the hardware emulator 2 is stopped. That is, in the above-described step ST8, when data is supplied, the arithmetic processing in the hardware emulator 2 is started, but when the operation for one event by the supplied data is completed,
The clock is stopped after the transfer of the operation result.

As described above, according to the first embodiment, the hardware emulator 2 verifies the part of the logical information determined to the structure level, and verifies the other part with the software simulator 1. Is executed, the effect that the emulator can be used efficiently and the time required for logic verification can be reduced even when the design phase differs for each module.

According to the first embodiment, the hardware emulator 2 is provided with a reconfigurable circuit such as an FPGA or an actual component such as a processor. The effect that the verification can be performed is obtained.

Further, according to the first embodiment, the use of a general-purpose simulation program as the simulation program in the software simulator 1 has an effect that the cost of the apparatus can be reduced.

Embodiment 2 The logic verification apparatus according to the second embodiment of the present invention is different from the logic verification apparatus according to the first embodiment in the step S
The processing of data transfer (transmission of output signals) from the software simulator 1 to the hardware emulator 2 in T7 is changed, and the other parts are the same as those in the first embodiment, so only the processing will be described. The description of the other parts is omitted.

In the logic verification apparatus according to the second embodiment, the data transfer process is executed only when an event occurs, that is, when the value of data to be communicated (the value of the output signal of software simulator 1) changes. Is performed (event driven format) or is executed every clock cycle in the software simulator 1 (cycle based format). As the processing format to be actually executed, the one that requires less time for data transfer overall is selected before the start of verification.

In this way, the data transfer format is determined to be the event-driven format or the cycle-based format. When the data value does not change at all in the cycle-based format, the data transfer process may not be performed to reduce the number of transfers.

As described above, according to the second embodiment, the data transfer format is determined to be one of the event-driven format and the cycle-based format, whichever reduces the time required for data transfer comprehensively. Therefore, the transfer time can be optimized and the time required for the verification can be further reduced.

Embodiment 3 The logic verification apparatus according to the third embodiment of the present invention is different from the logic verification apparatus in the first embodiment in the step S
This is a modification of the operation of the hardware emulator 2 at T8, and the other parts are the same as those of the first embodiment. Therefore, only the processing will be described, and the description of the other parts will be omitted.

In the logic verification device according to the third embodiment, when the operation cannot be interrupted, for example, when the operation is not interrupted, for example, when connected to an external device 5 whose execution cannot be interrupted, the hardware emulator 2 Each time the operation for the supplied data and the transfer of the operation result are completed, the logical operation unit 21 of the hardware emulator 2 is set to the initial state (that is, the state at time 0), and then the data is supplied from the software simulator 1. At this time, the processing is executed until the time when the software simulator 1 completes the processing. in this case,
All data supplied from the software simulator 1 up to that point is stored in the buffer memory 42, and the hardware emulator 2 sequentially reads out the data and executes processing up to that point.

As described above, according to the third embodiment, when data is supplied from the software simulator 1 by the hardware emulator 2, the verification from the time 0 to the time corresponding to the data is executed. Thus, when the number of cycles required for verification is smaller than the ratio between the processing speed of the hardware emulator 2 and the processing speed of the software simulator 1, the simulation can be executed faster than the software simulator 1 alone. The effect is obtained. Further, there is an effect that the entire system having a CPU or the like without a simulation model can be verified.

Embodiment 4 The logic verifying apparatus according to the fourth embodiment of the present invention includes the processing according to the first embodiment,
This is a modification of the processing when the logical information is all at the structure level, and the other parts are the same as in the first embodiment. Therefore, only the processing will be described, and the description of the other parts will be omitted.

In general, when verifying a logic circuit, a test bench for evaluating the validity of the target logic is created. The test bench includes input data for a target logic and an expected value of an output result of the logic when the input data is applied. Since no specific logical structure is assumed in the test bench, if all the logical information is at the structural level in the final stage of design, all the logical operations are executed by the hardware emulator 2. Therefore, in this case, all of the supplied input data of the test bench is accumulated in the buffer memory 42 of the communication device 3 before the start of the verification, and the input data is supplied from the buffer memory 42 to the hardware emulator 2. To

As described above, according to the fourth embodiment, when all the logical information is at the structural level, the verification is started after all the input data to the target logic is stored in the communication device 3. As a result, the data transfer time can be reduced, and the time required for verification can be reduced.

[0070]

As described above, according to the present invention, a reconfigurable hardware emulator that executes verification of a predetermined first part of a logic to be verified, and a simulation that describes a simulation of the logic to be verified. A software simulator having storage means for storing the program, and arithmetic processing means for executing the simulation program and executing the verification of the remaining second part of the logic to be verified; and And a communication unit for transmitting and receiving the operation result of the verification for the verified logic.
Even when the design phase differs for each module, there is an effect that the time required for logic verification can be reduced by using the emulator efficiently.

According to the present invention, data transmitted and received between the first part and the second part is divided in units of the same number of bits as the bus width of the interface with the communication unit. Therefore, there is an effect that the number of times of data transfer by the interface can be optimized.

According to the present invention, the software simulator provides the verification operation result at the timing at which the value of the verification operation result changes and the timing of each clock, whichever is shorter in the transfer time of the verification operation result. Is transmitted to the communication unit, so that the transfer time can be optimized and the time required for verification can be further reduced.

According to the present invention, when the operation result of the verification by the software simulator is supplied, the hardware emulator performs the verification from time 0 to the time corresponding to the operation result of the verification. When the number of cycles required for verification is smaller than the ratio between the processing speed of the hardware emulator and the processing speed of the software simulator, there is an effect that the simulation can be executed faster than the software simulator alone. In addition, C with no simulation model
There is an effect that the entire system having a PU or the like can be verified.

According to the present invention, when all of the logic to be verified is the first part to be verified by the hardware emulator, all the input data to the logic to be verified is transmitted to the communication unit, and the communication unit is connected to the software simulator. The data transfer time can be reduced by accumulating data from the HMI and supplying it to the hardware emulator, and the hardware emulator is configured to use that data to perform verification on all of the logic under test. And the time required for verification can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic verification device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration example of the communication device in FIG. 1;

FIG. 3 is a flowchart illustrating an operation of the logic verification device according to the first embodiment;

FIG. 4 is a diagram showing an example of a module verified by a software simulator.

FIG. 5 is a diagram showing a conventional hardware logic emulation system.

FIG. 6 is a flowchart illustrating an operation of the management computer of FIG. 5;

FIG. 7 is a block diagram showing a configuration of a first conventional logic verification device.

FIG. 8 is a block diagram showing a configuration of a second conventional logic verification device.

[Explanation of symbols]

1 software simulator, 2 hardware emulator, 3 communication device (communication section), 5 external device, 1
1 CPU (arithmetic processing means), 12 memory (storage means), 42 buffer memory, 43 emulator control section (first control means), 44 clock control section (second control means), 45 external device control section ( 3 control means).

Claims (12)

[Claims] 1. A reconfigurable hardware emulator that executes verification of a predetermined first part of logic to be verified, storage means for storing a simulation program describing a simulation of the logic to be verified, and the simulation A software simulator having an arithmetic processing unit for executing a program and executing a verification of the remaining second part of the logic to be verified; and a software simulator between the hardware emulator and the software simulator. A logic verification device comprising: a communication unit configured to transmit and receive a calculation result of verification. 2. A method according to claim 1, wherein said verification target logic is divided into a first part to be verified by a hardware emulator and a second part to be verified by said software simulator according to an abstraction level of the verification target logic. The logic verification device according to claim 1, wherein 3. The software simulator according to claim 1, wherein the software simulator divides the data transmitted and received between the first part and the second part in units of the same number of bits as the bus width of the interface with the communication unit. The logic verification device according to claim 1, wherein 4. The software simulator transmits a calculation result of the verification to a communication unit. The communication unit supplies the calculation result of the verification from the software simulator to a hardware emulator. 2. The logic verification device according to claim 1, wherein the verification is performed by using a calculation result of the verification by the software simulator as data. 5. The software simulator communicates the operation result of the verification at a timing at which a transfer time of the operation result of the verification is shorter among timings at which a value of the operation result of the verification changes and timing at each clock. 5. The logic verification device according to claim 4, wherein the data is transmitted to a unit. 6. The logic verification device according to claim 4, wherein the hardware emulator executes the verification for one event when supplied with the operation result of the verification by the software simulator. 7. The hardware emulator according to claim 4, wherein, when supplied with the operation result of the verification by the software simulator, the hardware emulator executes the verification from time 0 to a time corresponding to the operation result of the verification. Logic verification device. 8. The logic verification device according to claim 1, wherein the communication unit has a buffer memory for storing the operation result of the verification of the logic to be verified from the software simulator until the operation result is supplied to the hardware emulator. . 9. The communication unit according to claim 1, wherein the communication unit has a first control unit that controls a timing at which a calculation result of verification of the verified logic from the software simulator is supplied to the hardware emulator. Logic verification device. 10. The communication unit according to claim 1, further comprising second control means for controlling a clock of a hardware emulator to synchronize the processing in the software simulator with the processing in the hardware emulator. 2. The logic verification device according to 1. 11. The communication unit controls a predetermined external device connected to a hardware emulator, and includes a third control unit that synchronizes processing in the predetermined external device with processing in the hardware emulator. 2. The logic verification device according to claim 1, further comprising: 12. The software simulator transmits all input data to the logic to be verified to a communication unit when all of the logic to be verified is a first part to be verified by a hardware emulator. Accumulating the data from the software simulator and supplying the data to a hardware emulator, wherein the hardware emulator uses the data to execute verification of all of the verified logic. 2. The logic verification device according to 1.