JP2000209124A - Correlation circuit for spread spectrum communication - Google Patents

Abstract

(57) [Problem] A conventional sliding correlator has a problem that it takes a long time to obtain a correlation, and a matched filter has a problem that power consumption increases. And a correlation circuit for spread spectrum communication that can obtain a correlation. An A / D converter converts a received spread-spectrum signal into a digital signal.
, One symbol is written into the memory circuit 14 at a clock higher by the CDMA chip rate or oversampling, and the multi-tap F / F 15 reads information from the memory circuit 14 at high speed with multiple taps to perform parallel / serial conversion (time This is a correlation circuit for spread-spectrum communication that performs high-speed correlator 16 and delay F / F 17 to perform a spread code and a product-sum operation at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication correlator used on the receiver side of a spread spectrum communication system in mobile communication, wireless LAN, etc., and more particularly to a simple and small-scaled spread spectrum communication system. The present invention relates to a communication correlator.

[0002]

2. Description of the Related Art In a spread spectrum (SS) communication system generally used for mobile communication or wireless LAN, a transmission side performs narrow band modulation (primary modulation) on transmission data and further performs spread modulation. (Secondary modulation), two-stage modulation is performed, and data is transmitted. On the receiving side, the received data is despread to return to primary modulation, and then the baseband signal is sent to a normal detection circuit. Playback.

Conventionally, a correlator for spread spectrum communication for obtaining a correlation for demodulating a received signal subjected to spectrum spreading is composed of a despreading circuit and a demodulation circuit for a code division multiplex modulation wave. A correlator for spread spectrum communication uses a sliding correlator (SC) composed of a logic circuit to acquire synchronization and obtain a correlation with a synchronous phase detected thereafter.

The sliding correlator shifts the local oscillation code sequence (spreading code) one bit at a time using a 1-bit correlator, and calculates the correlation with the received code sequence each time. If a correlation is obtained for the number, a synchronization phase at which the correlation has a peak is obtained, and synchronization acquisition is performed.

Here, a sliding correlator, which is one of the conventional despreading circuits, will be described with reference to FIG. FIG. 9 is a configuration block diagram of a part of a conventional sliding correlator. The part for obtaining the correlation output in the conventional sliding correlator includes an A / D converter 31, a multiplier 32, a PN code register 33, an adder 34, and a delay circuit 35.

The components of the conventional sliding correlator will be described. The A / D converter 31 performs code division multiplexing (Co
This is a high-precision analog / digital converter that converts an analog signal transmitted after being demultiplexed (CDMA) modulated and received by an antenna (not shown) into a digital signal. The PN code register 33 is a register that outputs a PN (Pseudo Random Noise) code code, which is the same spreading code used for CDMA modulation on the transmitting side.

[0007] The multiplier 32 adds the PN code register 3 to the digital reception data output from the A / D converter 31.
3 is a multiplier for multiplying the PN code output from the P.3.
The adder 34 and the delay circuit 35 accumulatively add the multiplication result output from the multiplier 32 for one symbol period and output the integrated value as a correlation output.

The operation of the conventional sliding correlator is such that an analog signal of received data received by an antenna is converted into a digital signal by an A / D converter 31,
The PN code output from the code register 33 is multiplied by the multiplier 32, accumulated and added by the adder 34 and the delay circuit 35, and the addition result for one symbol is output as a correlation output. The multiplication and the cumulative addition are repeated while changing the phase by shifting the timing of the multiplication in the multiplier 32 by one chip, and the synchronous phase at which the correlation output reaches a peak is detected.

The configuration using a sliding correlator as this despreading circuit is relatively simple, has a small number of gates, and therefore consumes little power. However, the time required for synchronization acquisition is generally one symbol. Since it takes time for the number of minutes × the number of chips in one symbol, it takes a long time to obtain a correlation output.

In order to solve the problem that it takes time to obtain a correlation output, a matched filter (matched filter or matching filter) is used instead of a sliding correlator.
It has been considered that a matched filter (MF) is used for a correlator for spread spectrum communication. The matched filter performs synchronization acquisition within one symbol time by simultaneously taking correlations when the phases are shifted.

Here, a matched filter which is another example of the conventional despreading circuit will be described with reference to FIG.
FIG. 10 is a block diagram showing a configuration example of a conventional matched filter. The conventional matched filter includes an A / D converter 41, a multiplier 42, a PN code register 43,
It comprises an adder 44 and a sample and hold (S / H) circuit 45.

Each part of the above-mentioned conventional matched filter will be described. The A / D converter 41 is a converter that converts a CDMA modulated analog input signal into a digital signal. A plurality of sample-and-hold (S / H) circuits 45 are provided and sequentially take in and hold digital signals from the A / D converter 41.

The PN code register 43 is a register that outputs a PN code (code) that is a spreading code. The multiplier 42 applies a PN signal from the PN code register 43 to the digital signal held by each sample and hold circuit 45.
It is a multiplier that multiplies the sign. The adder 44 includes the multiplier 4
This is an adder for simultaneously adding outputs from the two.

[0014] The operation of the conventional matched filter is A / D
The input signal digital-converted by the converter 41 has a plurality of S / S
The output from the S / H circuit 45 and the PN code output from the PN code register 43 are successively multiplied by the H circuit 45 and multiplied by the multiplier 42, and the result of the multiplication by the multiplier 42 is multiplied by the adder 44. The addition is performed all at once, and the addition result is output. A correlation output is obtained from the addition result.

However, in a general matched filter, in order to obtain a correlation when the phases are simultaneously shifted, for example, the above-described sliding correlator needs to be
The number of gates is required to be twice as many as the number of chips in one symbol, and the gate size is increased, leading to an increase in LSI price and power consumption, which is practically difficult to use for a receiver of a mobile terminal.

[0016]

As described above, in the conventional sliding correlator, there is a problem that it takes time until a correlation output is obtained. In the conventional matched filter, the number of gates increases, and the price of LSI increases. There is a problem that the power consumption increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a correlation circuit for spread spectrum communication capable of reducing the cost of an LSI by reducing the number of constituent elements and obtaining a correlation output. With the goal.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention is directed to a method of writing a spread spectrum received signal to a memory, and writing the written signal from the memory to a multi-tap according to a time conversion amount. A plurality of times of processing for performing a time conversion by performing parallel / serial conversion in the logic unit at a speed higher than the writing speed of the memory and performing a time conversion by performing the parallel / serial conversion at a speed higher than the writing speed of the memory, a plurality of times. Since this is a repetition spread spectrum communication correlation circuit, the number of constituent elements can be reduced and a correlation output can be obtained.

[0019]

Embodiments of the present invention will be described with reference to the drawings. The correlation circuit for spread spectrum communication according to the embodiment of the present invention is a circuit for processing a spread spectrum signal transmitted from a receiving unit, which is usually processed by a spread code at a so-called chip time interval. The time-shifted logic section reads the stored spectrum-spread signal from the memory section at high speed with a plurality of taps, and performs a product-sum operation on the read signal and the spread code. Is repeated a plurality of times, and the correlation output can be obtained by reducing the number of constituent elements.

More specifically, the spectrum-spread signal is stored in the memory for at least one symbol, stored in the time conversion logic unit, and is read out at a high speed, and the product-sum operation with the spreading code is performed at a high speed. Thus, time conversion of the spread spectrum signal input from the receiving unit is realized.

At present, the so-called W-CDMA (Wideband CDMA) proposed by ARIB (Radio Industry Association) in IMT2000 has a chip speed of 4M (mega) cps.
(Chipper second). In contrast, W-CDM
The CMOS (complementary MO) is manufactured by using the manufacturing process of the LSI (Large Scale Integrated Circuit) in 2001, in which A is practically used.
In the case of S), the line width is about 0.18 μm, and the clock frequency used is from 500 MHz to 2 G (giga) Hz.
Is expected.

That is, processing much higher than the frequency of the input signal can be performed in the circuit. Since the chip speed is 4 Mcps, it is necessary to divide the signal by about four times the sampling from the signal processing and observe the matching with the spreading code more precisely, but the clock used for processing the received signal is still 16 MHz. On the other hand, if 1.6 GHz can be used as the clock speed of the clock used for the internal processing of the circuit,
The internal processing has a processing capacity 100 times that of the processing of the received signal.

In order to achieve the same function as the matched filter, for example, 16 MHz
The spectrum-spread signal received in increments is stored in memory, read at a high speed of, for example, 1.6 GHz, and can be processed at a speed of 100 times by performing a product-sum operation at a high speed by a high-speed sliding correlator. It is. Therefore, if the number of chips (spreading factor) is 25, 100 samples exist with 4 times oversampling, so that it is possible to obtain the correlation of one symbol in the same one symbol time as the matched filter. .

In this case, the spreading code is used 100 times repeatedly without changing one symbol.
The spread spectrum signal needs to be slid at intervals of one sample, and the memory needs to be prepared for at least two symbols.

First, after one symbol is written to the first memory at 16 MHz, the next one symbol is written to the second memory for each sample, and 1.6 GHz is written from the first and second memories. , The data for one symbol is slid one sample at a time and read out 100 times.

That is, the data of one symbol is slid one sample at a time from the first memory in which the data for one symbol is written and the second memory in which the data is written for each sample by 100 samples at 1.6 GHz. Performing the reading twice means that writing and reading are performed simultaneously in the second memory, and the signal that has been subjected to the spectrum spreading for the next one symbol is transmitted at the time of reading the data for one symbol. 2 will be read into memory. If this operation is alternately performed between the first memory and the second memory, it is possible to continuously write and read the spread spectrum signal to and from the memory. Therefore, as in the case of the matched filter, the correlation output can always be transmitted.

In the case of W-CDMA, the spreading factor varies depending on the physical channel, but is at least 4 chips and 256 at the maximum.
Chips are required. However, in this case, the chip speed is 4.
It may be considered constant at 096 Mcps. In the future, there is a possibility that the variable rate will increase to 16.384 Mcps, which is assumed. Therefore, if a maximum of 256 chips is required, it cannot actually be processed by one high-speed sliding correlator (high-speed SC). In that case, a plurality of high-speed SCs may be prepared, and the same operation may be performed by shifting one sample at a time.

Specifically, in the case of 256 chips, 102
4 samples (256 chips x 4 oversampling)
Therefore, if a 1.6 GHz clock can be used as a clock for reading data from the memory, 1.
To perform 100 times processing with a 6 GHz clock, 11
Requires high-speed SCs. 110 with 11 high-speed SCs
It can correspond to 0 samples (100 samples × 11). Even in this case, it can be realized with a hardware scale much smaller than the hardware scale constituting the 1024-tap matched filter (MF).

However, in the above circuit, although the speed is 100 times, the hardware scale is larger than 1/100, so that the power consumption is larger than that of the MF. However, since the hardware scale is reduced to about 1/10, W-CD
The fact that the MF section occupying most of the demodulation section of the MA is reduced to about 1/10 has the effect of reducing LSI cost.

In the above example, the case where the spread code is not replaced has been described. However, if the signal is fixed and the spread code is replaced, the spread code is specified in a short time and the correlation output is obtained. It is possible to obtain.

If a multiply-accumulate unit having an MF configuration is prepared in place of the high-speed SC, and reading from the memory is performed by multiple taps in symbol units, the correlation output can be obtained in a very short time, for example, in the case of a 1 GHz clock. , 1 ns (nanosecond). This is effective when a large number of memories are prepared, a large number of symbol units of information are stored in the memories, and their correlation outputs are obtained. That is, even if a plurality of MFs are originally required, one M
F enables processing.

In the W-CDMA system, the MF operation is required as a mobile terminal when capturing the long mask symbol of the first perch in the initial synchronization, that is, when establishing symbol synchronization and slot synchronization. In other cases, intermittent operation is allowed. In the initial synchronization, after capturing the long mask symbol of the first perch, a long code group is specified by the long mask symbol of the second perch. This can be achieved by demodulating the same input signal with another short code. Further, the long code is specified at the position of the pilot symbol of the first perch. Thereby, the initial synchronization can be approximately achieved.

The time required to complete these operations is set within three seconds after performing these operations for a plurality of base stations. Of these, the time required to capture the initial long mask symbol is extremely short (at least within one second), and the above operation is performed for the entire talk time even if the power consumption is large. Considering that only when is turned on, it can be said that there is almost no effect on the battery. That is, normally, only the SC operation needs to be performed intermittently, and reduction of power consumption can be achieved comprehensively.

In the above-described circuit, it is necessary to read data from the memory at a higher speed than the writing speed. In the correlation circuit for spread spectrum communication according to the embodiment of the present invention, the reading speed from the memory is the same as the writing speed, but the reading is performed simultaneously with multiple taps (multiple samples).

This is stored in a logic unit for time conversion of an F / F configuration (flip-flop configuration), and reading from this is performed at high speed, thereby implementing the same function as a high-speed read memory.

Next, a correlation circuit for spread spectrum communication according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of a correlation circuit for spread spectrum communication according to an embodiment of the present invention. Here, the operation after the symbol synchronization, the radio slot synchronization, and the frame synchronization are established, which are relatively simple operations (during normal communication), will be described first. As shown in FIG. 1, a correlation circuit for spread spectrum communication (this circuit) according to the present embodiment includes a code generator 13 for generating a time-series PN code (PN code), and a spread spectrum modulated by the PN code. An A / D converter 11 for inputting a signal and converting the analog signal into a digital signal; a memory unit 14 for holding the digital signal; a multi-tap F / F 15 for reading and holding data from the memory unit 14; A high-speed correlator 16 for performing a high-speed product-sum operation on the output from the tap F / F 15 and the PN code output from the code generator 13, the memory unit 14, the multi-tap F / F 15, the code generator 13, and the high-speed correlator 16 And a control unit 12 for controlling the input and output of data and the like to and from the computer.

The operation of this circuit during normal communication will be described. The memory section 14 plays a role of a memory for temporarily storing an input digital signal, and can store data for one symbol. And the control unit 12
, The data of one symbol of the signal is taken into the memory unit 14 while being sequentially shifted from the first sample. Here, since it is assumed that symbol synchronization, radio slot synchronization, and frame synchronization have been established, it is known at which phase the leading sample of a specific symbol exists.

The control unit 12 supplies the memory unit 14 with the same fetching speed as before, that is, at the same speed as the sampling speed (approximately 16 MHz in the case of normal four-times oversampling, exactly four times 4.096 MHz). Multi-tap F / F
15 is made to perform reading with multiple taps (multiple samples).

The multi-tap F / F 15 performs parallel / serial conversion at a speed higher than the speed read by the multi-tap, and outputs it to the high-speed correlator 16. This parallel / serial conversion means time conversion, and the conversion output speed is determined by the accuracy of the multi-tap F / F 15, the number of oversampling, and the number of high-speed correlators 16. The example of FIG. 1 shows a case where the number of the high-speed correlators 16 is one, and the number of taps N of the multi-tap F / F 15 is shown.
Is 1024.

For example, when outputting at 16 times the speed of the signal input to the multi-tap F / F 15,
The number of taps N is 16, and when the input signal is input at 16 Mcps, the output signal is 16 Mcps × N (16) = 2
It is output at a speed of 56 Mcps. In this case, if the oversampling number is 4, 256 Mcps / 4 = 6
The number becomes 4, and 64 high-speed correlators 16 are required.

Upon receiving the output, the high-speed correlator 16
The product-sum operation is performed using a clock having the same speed as the read speed of the multi-tap F / F 15. At this time, spread codes (PN codes) are sequentially received from the code generator 13 at the above-mentioned clock speed. Here, the code generator 13 may be a code register. The generation and reading of this code are also controlled by the same control unit 12. The multiplication operation performed by the high-speed correlator 16 outputs the data (multi-bit) from the memory unit as it is when the spreading code is “1”, and inverts the multi-bit when the spreading code is “0”. Output.

Next, a case where a plurality of high-speed correlators 16 are provided will be described with reference to FIG. FIG. 2 is a configuration block diagram of a complex type spread spectrum communication correlation circuit according to the embodiment of the present invention. Although the control unit 12 and the code generator 13 shown in FIG. 1 are omitted for the sake of simplicity, the control unit 12 includes a memory unit 14, a multi-tap F / F 15, High-speed correlator 16,
The input / output timing to the delay F / F 17 is controlled, and the code generator 13 outputs a spread code to the high-speed correlator 16.

As shown in FIG. 2, the complex type circuit is an A / D converter for converting a Q signal of a received signal from analog to digital.
A converter 11a, an A / D converter 11b for converting an I signal of the received signal from analog to digital, and an A / D converter 1
Memory unit 1 for storing digital signals from 1a and 11b
4 and multi-tap F / Fs 15a and 15b for parallel / serial conversion of a digital signal input from the memory unit 14.
A plurality of delay F / Fs 17 for sequentially delaying and outputting digital signals from the multi-tap F / F 15;
It comprises a plurality of high-speed correlators 16 which receive the output of the F15 and the output of the delay F / F 17 and perform a correlation operation. The delay F / F 17 constitutes a delay unit.
The high-speed correlator 16 includes a multiplication unit that performs multiplication with a spreading code (spreading code). Further, all outputs from the plurality of high-speed correlators 16 are added to obtain an overall correlation output. Has become. However, in FIG.
An adder for obtaining the entire correlation output is not shown.
Here, two multi-tap F / Fs 15 are provided because
When writing in a book, the other is for reading, and this operation is performed alternately.

The reading speed in the memory unit 14 is the same as the writing speed, but when reading, a large number of samples are read. Multi-tap F / F
Reference numeral 15 denotes a unit for inputting a large number of samples in parallel from the memory unit 14, converting the serial number into serial data, and then outputting the serial data to the high speed correlator 16 or the delay F / F 17. By performing parallel / serial conversion (time conversion) by the multi-tap F / F 15, only a portion configured by a digital circuit operates at high speed.

With the configuration as shown in FIG.
A full-scale memory such as an AM or an SRAM can be used, so that a chip area and a chip price can be reduced. Also, as shown in FIG. 7, high-speed correlators (SC) can be arranged in a matrix to enable demodulation of information of a plurality of users. FIG. 7 is a configuration block diagram of a correlation circuit for spread spectrum communication capable of demodulating a plurality of users according to the embodiment of the present invention. In this case, SC
Can be operated only at the timing of necessary reception information, and the SC column can also have a function as a searcher. In this case, the number of operation bits can be reduced.

The conversion time (multiple) in the correlation circuit for spread spectrum communication according to the embodiment of the present invention is as follows:
Operating clock frequency (Hz), high-speed correlator (SC)
[Table 1] shows the relationship among the number of F / Fs, the number of memories when the memory section is configured by F / F, the number of delay F / Fs, and the number of multi-tap F / Fs (time conversion F / Fs).

[0047]

[Table 1]

In practice, there are quite a lot of symbols to be processed at the same time as a mobile terminal of a W-CDMA system, and a signal that must be stored in a memory unit in a symbol unit as a received signal has two antennas. If there are, there are a total of six complex modulated signals (I / Q) and delayed wave components, and a total of 24 when considering a plurality of control and traffic channels.
~ 48.

Incidentally, DHO (Thailand diversity handoff)
Sometimes, it is necessary to catch another base station at the same time, so that the number becomes one to two times as large. The term "one time" means that the DHO is executed without increasing the hardware by omitting a part of the signal reproduction of the base station that is currently executing communication and reducing the number of paths, for example. .

The spreading code is also subjected to complex modulation.
Further, in the case of a multicode transmitted at the same time by changing the spreading code, or in the case of a long code mask symbol of the first perch and the second perch, the input signal is made the same and only the code is changed to output the correlation. Must be obtained.

Therefore, when trying to obtain a correlation using a normal SC, the number of SCs is at least 96 to 4
Approximately 500 times, which is up to 5 times. Furthermore, in addition to this, a searcher for obtaining synchronization is required, but a matched filter (MF) method is usually used for the searcher.
The hardware scale is about 100 to 300 times that of the SC.

Specifically, the number of gates of the SC needs to be about 200, and the number of gates of the MF having the same operation accuracy needs to be about 60 k. However, in searcher operation, WC
Since no calculation accuracy is required for DMA data demodulation, about 10 k gates are sufficient. In addition, a searcher is required for each antenna, and another one may be required to cope with DHO.

In the above situation, if this circuit is used, it is necessary to newly install a memory section and a multi-tap F / F. However, the number of high-speed correlators can be reduced, and the hardware scale is greatly reduced. Is possible. As will be described later, a searcher for synchronization acquisition is not required, so that the hardware scale is further greatly reduced.

The memory section is a 2-port DRAM (Dynami
c Random Access Memory) and the like can be sufficiently used, and a large reduction in chip occupation area and low power consumption can be achieved as compared with a circuit formed by digital F / F (Flip-Flop).

In the above, the operation after the symbol synchronization, the radio slot synchronization, and the frame synchronization are established (during normal communication) has been described. Next, the initial synchronization when these synchronizations have not been established will be described. At the time of initial synchronization, symbol synchronization, radio slot synchronization, and frame synchronization have not yet been established with the power switch of the mobile device turned on, and synchronization must be specified in that state. According to the ARIB specification, the initial synchronization is established as follows.

As a first step, chip synchronization, symbol synchronization, and radio slot synchronization are established. First, a long code mask symbol of the first perch is detected to establish chip synchronization, symbol synchronization, and radio slot synchronization. Hereinafter, as a condition of the description, the chip rate of the first perch is 4 Mcps, the spreading factor is 256, and the signal input from the A / D converter 11 is 4 times oversampling (1
6 Mcps) and 6 bits.

The configuration and operation at the time of initial synchronization will be described in the following (A) to (N). Although the description will be made based on the example of FIG. 2, a case where the time conversion is 16 times will be specifically described.

(A) The memory section 14 has 1024 taps (an image in which 1024 6 bits are arranged side by side) + α
(Several taps). (B) The output from the A / D converter 11 is sequentially written into the memory unit 14. The writing speed uses a clock of 16 MHz.

(C) If just 1024 taps (just one symbol of the perch channel) are written, 1
Multi-tap F / F for 6 taps at once (F / F for time conversion)
15 is transferred using a 16 MHz clock. Simultaneously with the transfer, the sample data for the first 63 symbols is transferred to the 63 delay F / Fs 17.
At this time, a multi-tap F / F with a clock speed of 256 MHz
15 and the delay F / F 17 and the high-speed correlator 16 are operated. Further, writing to the memory unit 14 at 16 MHz continues. It is described that the sample data is transferred from the beginning of the symbol to the delay F / F 17, but this is a simple assumption and is not always the beginning of the symbol.

(D) The high-speed correlator 16 is 256 MHz
The product-sum operation is performed at the clock of z. The spreading code at this time is a common short code.

It takes just 16 MHz for all data of 16 taps of the multi-tap F / F 15a to be transferred. During this time, 16 data have been transferred from the memory unit 14 to another multi-tap F / F 15b. Therefore, the seventeenth data is transmitted from the multi-tap F / F 15b.

When this operation is repeated 64 times, correlation outputs at 64 sample points are simultaneously obtained from the 64 high-speed correlators (SC) 16. Hold this,
If the output is switched and output every time (16 MHz) in a time-division manner, an output equivalent to the MF can be obtained.

Further, here, the accumulator in the SC 16 is reset and the operation is restarted from the above (C). At this time, the first 64 sample data have been discarded, and 65
The data is transferred from the memory unit 14 to the delay F / F 17 and the multi-tap F / F 15 having 16 taps from the second data.

By repeating this large motion 16 times, 64 (sample data for each) × 16 (times) = 10
It becomes 24, and a correlation output for 1024 samples can be obtained within one symbol time. Information in the memory unit 14 is also 6
When 4 samples are discarded, 64 samples are newly stored and completely updated.

The spreading codes input to the high speed correlator (SC) 16 are all common, and are input from the beginning of the symbol. In case of 4 times over sample, the first tap is 4
The input is common for the samples.

(E) Since the speed of the high-speed correlator 16 operates at 16 times the sample speed, it takes exactly 64 sample times when 64 correlations for one sample have been acquired. At the end of this, 1 is stored in the memory unit 14.
Since writing is performed at a speed of 6 MHz, new input data for 64 samples is taken in.

(F) Since the long code symbol spread by the short code is inserted only once in 10 symbols, it must be repeated for at least 10 symbols in order to search for the nearest base station (0. 62
5 ms / 10 symbols). The required time is the usual M
It is no different from using F. (G) Although the memory section 14 has 1024 taps in principle, it is sufficient, but there is a case where the memory section 14 cannot be erased due to a delay in signal processing. After writing 1025 taps, it is sufficient to return to the first tap and update.

(H) In this way, when at least 10 symbols are viewed, it is possible to synchronize the radio slot with the chip synchronization and the symbol synchronization of the enrolled base station including the adjacent base station and the position of the long code mask symbol. . This process is performed by a profiler, and the logic for comparing and detecting the strongest correlation output and the time of the detection are specified. Of course, if the communication condition is bad, if the determination cannot be made only by the data of these 10 symbols (corresponding to one radio slot), the determination is made by combining the next 10 symbols. In the profiler, the determination is made by adding the results at the same phase sample interval in one radio slot. In any case, the above arithmetic processing may be continuously repeated.

Next, regarding the power consumption in the correlation circuit for spread spectrum communication according to the embodiment of the present invention,
[Table 2] [Table 3] and FIG.
Conversion time 1x, 4x, 16x, 64x, 256x, 10
Assuming that 24 × is an example of a to f, the clock frequency (M
Hz), the number of gates of the high-speed correlator (SC), the number of F / F gates in the memory section, the number of delay F / F gates, the number of multi-tap (for time conversion) F / F gates, and the total number of gates. Is shown.

[0070]

[Table 2]

For the examples a to f, the CMOS process level (gate length) is 0.35 μm, 0.25 μm,
Power consumption for the case of 0.18 μm is shown.
Power consumption (W) = number of gates × frequency × unit power consumption value. Unit power consumption is μW / gate / MHz
And provided by each manufacturer. still,
Table 3 also shows the power consumption of the 600k gate full MF for reference.

[0072]

[Table 3]

The gate length of 0.25 in [Table 3]
When the power consumption of μm is displayed in Log, in the examples of a to f,
-0.08449, -0.01825, -0.0219
8, 0.188364, 2.194013, and the change is shown in FIG. FIG. 3 shows a gate length of 0.25 μm.
It is a figure showing Log display of power consumption of m. In FIG. 3, it can be seen that the cases of a to c (conversion time 1 to 16 times) have low power consumption.

Next, the specification of the long code group will be described as a second step. If the synchronization of the radio slot can be established, it is known where the long code mask symbol of the second perch exists, so that information is taken into the memory. Actually, the information is obtained at the same position as the long code mask symbol of the first perch, so that the information to be obtained is obtained at the same position.

The information fetched into the memory may be subjected to, for example, operations (A) to (C) at the time of initial synchronization.
In this case, since the symbol synchronization has been established, the first sample taken into the memory unit 14 is always the head of the symbol. Therefore, if the information read from the memory unit 14 is processed by replacing the same spreading code with the 16 kinds of spreading codes instead of the same spreading code in the high-speed correlator, a correlation can be obtained in any one of them. it can.

It is extremely easy to specify the long code group within one symbol time. As described in the previous example, since the correlation output of 64 digits is simultaneously obtained within 64 sample times, the delay F / F1 is not necessarily required in this case.
7 is not needed. The same signal is converted into 64 high-speed correlators (S
C) It is more preferable to supply to 16.

Next, as a third step, specification of a long code and establishment of frame synchronization will be described. If the synchronization of the radio slot can be established, it is known where the pilot symbol of the first perch exists, and the information is taken into the memory unit. This time, information for two symbols may be fetched, or if there is idle memory, four symbols of all pilot symbols may be fetched.

When the information has been taken in, the operation is performed in the same manner as in the second step. There are a total of 32 types of long codes including a phase difference in one long code group, and there are 16 types of phases since 16 radio slots are repeated. Therefore, even if the long code is replaced by one correlator, 32 ( 32 types) x 16 (16 phases) x 4
(Pilot for 4 symbols) × 4 (4 μs: 256M
64 samples for 1 Hz clock [1 sample is 16M
Hz]) ÷ 64 (since 64 correlation outputs are obtained simultaneously) = 128 μs.

When a long code is specified in real time using a normal correlator, one symbol time (64 μm) is used.
s) × 32 (32 types) × 16 (16 phases) = 3276
In 8 μs (approximately 33 ms), since the pilot symbol exists only four times in 10 symbols, 2.5 (10/4)
Since it takes twice as long, that is, 80 ms or more (about 33 ms × 2.5), the use of this circuit as compared with the conventional correlator can greatly reduce the time.

Hereinafter, the required time in each step in the ideal state will be described. The condition is that a 1 GHz clock can be used. First step: 0.625 ms (same as the conventional method) Second step: 0.001 ms (0.625 ms for one radio slot in the conventional method) Third step: 0.2 ms (80 ms in the conventional method)

In reality, one radio slot is inevitable for one process. First step: 1 (same as the conventional method) Second step: 1 (same as the conventional method) Third step: 1 (32 × 16 = 512 (51 in the conventional method)
(2 radio slots × 0.625 ms = 320 ms), and it takes 4 to 5 times for more accurate processing. In any case, since the time of the third step is mainly used and the time of the third step is greatly reduced in the present circuit, even if the time of the first step is increased by one digit, compared with the conventional method, It will still be winning.

Next, the operation at the time of DHO (diversity handover or diversity handoff) will be described. Base station currently communicating (current base station)
When the communication environment with the base station deteriorates (in many cases, the base station moves away from the base station with which communication is performed and approaches a base station that is close to the base station (proximity base station)), communication with the adjacent base station is performed. If a better communication environment can be obtained, first search for a nearby base station and start communication with the nearby base station, but ask the nearby base station to send the same information as the information from the current base station. Receive. That is, cell diversity reception is performed, and the reception is continued until the levels of both received signals become equal to or higher than a predetermined value. This is called soft handover or soft handoff, and enables seamless communication. As described above, DHO is to perform soft handover or soft handoff by performing cell diversity reception.

According to the ARIB specification, all base stations operate asynchronously. Therefore, chip synchronization of adjacent base stations,
The process of establishing symbol synchronization and radio slot synchronization requires the same processing as in the case of the initial synchronization. Therefore,
Usually, new hardware is added for DHO. Specifically, measures have been taken to separately use one antenna and direct it to a nearby base station. Here, a method of performing DHO using the idle time of hardware will be described.

Note that, even in a hardware configuration that does not support the present DHO, as described above, a large number of memories and a large number of sliding correlators for inversely converting (demodulating) the information are provided. The maximum of these numbers is when the mobile unit captures a perch channel when it is switched on, and when its operation is completed, both the memory and the sliding correlator are mostly in the idle state. If this is used at the time of DHO, it is possible to demodulate information from the base station at the handover destination without any problem.

Next, a case where the present circuit is used as an interference canceller will be described with reference to FIGS. FIG.
FIG. 3 is a block diagram illustrating a configuration in which the correlation circuit according to the embodiment of the present invention is used in an interference canceller unit. FIG. 5 is a configuration block diagram of an interference canceller using the interference canceller unit according to the present embodiment. The interference canceller unit (ICU) includes an MF as shown in FIG. 4 and the interference canceller is composed of a large number of ICUs as shown in FIG.
This leads to an increase in the number of SIs.

Specifically, an MF of the number of users × the number of stages × an integer multiple is required, and the number of users is 300 or 600;
The number of stages is at least three, the integer is at least four or eight, and thus 3,000 to 10,000 MFs are required. In the present embodiment, this circuit capable of high-speed arithmetic processing is implemented in the MF section, and the number of MFs is greatly reduced.

As shown in FIG. 5, the receiving unit (RX)
And a multi-tap F /
F, a receiving unit and a delay circuit (Delay) or a plurality of I
Time conversion of the processing speed is performed between the CU, the adder and the delay circuit or between the ICUs, and between the adder and the plurality of ICUs. Accordingly, the matched filter (MF) shown in FIG. 4 performs a process of a high-speed product-sum operation as compared with a normal MF.

The basic concept of the present invention is that CDMA is stored in the memory.
After storing the modulation information, it is provided in a correlator that reads out the data with multiple taps and performs time conversion with a logic circuit (F / F). Even if the following concept is incorporated, the effect remains unchanged. (1) Clock speed is reduced by a multi-layer clock at the time of high-speed reading and calculation using a high-speed correlator. In this case, since the number of high-speed correlators increases, it does not directly reduce power consumption. (2) Variable oversampling multiples. The initial state is, for example, doubled, roughly determined, and then quadrupled. (3) When the configuration of the high-speed correlator and the MF (product-sum operation unit) are complex. Complex high-speed correlator (complex type high-speed S
As shown in FIG. 8, C) is composed of four high-speed correlators in principle, but by devising, the hardware scale can be reduced to less than four times and can be configured to be about twice as large. FIG. 8 is a circuit configuration block diagram in the case where the high-speed correlator is a complex type in the spread spectrum communication circuit according to the embodiment of the present invention. However, in FIG. 8, the number of correlators is two in one complex type high-speed SC. This is because, before the correlator, addition and subtraction of I and Q signals multiplied by a spreading code are performed. Therefore, it is not necessary to use four correlators for four I and Q signals, and the processing can be performed by two correlators.

That is, in the case of complex multiplication, time addition is performed as shown in the following equation. (A _I + jA _Q ) (C _I + jC _Q ) = A _I C _I −A _Q C
In one correlator when _{Q + j (A I C Q} + A Q C I) is not a complex, is performed the time addition of the AC, for complex, inherently, with four correlators, A _I C _I, A _Q C _Q, a _I C _Q, when to perform the addition and subtraction after performing temporal addition of a _Q C _I, although theoretically requires four correlators, in the example shown in FIG. 8, a _I C _I the -A _Q C _Q and _{a I C Q + a Q C} I from the computation, by performing the temporal addition, and makes it possible reduce the hardware scale.

In the case of the complex type, the configuration of the complex type is a 6-bit A / D converter 8 which receives a spread spectrum signal and converts an analog signal into a digital signal.
1 are provided corresponding to the I-phase signal and the Q-phase signal.
A memory unit 82 for holding a digital signal output from the bit A / D converter 81 and a multi-tap F / F 84 for reading data from the memory unit 82 with multiple taps (multiple samples) and performing parallel / serial conversion are provided. And
Further, there are provided a plurality of latch circuits 83 for adjusting the timing of data, codes, and other signals input to the complex SCs 80a, 80b, 80c by a clock (CLK).

According to the correlation circuit for spread spectrum communication according to the embodiment of the present invention, the received signal subjected to the spread spectrum is A / D-converted by a 16 MHz clock of 4 times oversampling, and is stored in the memory unit for about one symbol. Write, read it out to multi-tap F / F with multiple taps, 10
One symbol data is transmitted a plurality of times by a clock of 1.6 GHz to 16 GHz which is 0 to 1000 times, and the data of one symbol read out is written by a high-speed correlator while the data of the next one symbol is written in the memory unit. Since high-speed arithmetic processing is performed, there is an effect that a correlation output can be obtained by reducing the number of constituent elements.

[0092]

Next, a concrete and basic circuit configuration of a demodulation unit using this circuit will be described with reference to FIG. FIG.
FIG. 3 is a specific configuration block diagram of a demodulation unit of the correlation circuit for spread spectrum communication according to the embodiment of the present invention. As shown in FIG. 6, the demodulation unit of the present embodiment includes an antenna 51 and an RF
Unit 52, A / D converter 53, memory unit 54, multi-tap F / F 63, first high-speed correlator 55, spreading code generator 56, profiler 57, and second high-speed correlator 58. , A RAKE synthesizer 59, a data and voice processing unit 60, a control unit 61, and a finger memory 62.

Next, each section of the demodulation section shown in FIG. 6 will be specifically described. Usually, two antennas 51 are prepared and perform diversity reception. In the diversity reception, the same transmission signal is received by two antennas and the result of demodulation is combined to improve the reception sensitivity.

An RF (Radio Frequency) unit 52 creates (demodulates) a baseband (BB) signal, performs quadrature detection, and separates an I component (in-phase component) and a Q component (quadrature component). I do.

The A / D converter 53 outputs the B signal from the RF
The B analog signal is converted into a digital signal. The number of conversion bits requires 4 to 6 bits. If the conversion frequency is 4 times oversampling, W-CDMA (wideband CDM
In the case of A), the frequency is 16 MHz. One A / D converter is required for each I / Q signal and each antenna, but if high-speed processing is possible, time-division processing is performed so that one A / D converter can be used. Will be enough.

The memory section 54 holds the digital signal converted by the A / D converter 53 for at least one symbol. Write speed is 1 to 4 of chip speed
The reading speed may be the same, but the reading is performed with multiple taps. The multi-tap F / F 63 converts data input in parallel from the multi-tap from the memory unit 54 into serial data and outputs the data to the subsequent high-speed correlator. Here, time conversion is performed. When an MF (matched filter) is used instead of the high-speed correlator, simultaneous reading is required in symbol units. Further, a memory unit 54 'is provided for DHO.

First high-speed correlator (Digital SC) 55
Fetches the spread spectrum signal stored in the memory unit 54 and the spread code from the spread code generator 56, and performs a product-sum operation for each symbol. High-speed operation is performed as compared with the chip rate. The second high-speed correlator (Digital SC) 58 performs the same operation as the first high-speed correlator 55, but the operation result of the second high-speed correlator is output to the profiler 57.
Note that a matched filter (MF) may be used instead of the second high-speed correlator 58. Also, D
A high-speed correlator 58 'is provided for HO.

[0098] Spread code generator 56 sends out the specified spread code at the specified phase in accordance with an instruction from control unit 61. Note that a register for storing a spread code may be used instead of the spread code generator. In the case of a spread code generator having a normal speed, the data may be taken into the memory unit and time-converted by the multi-tap F / F in the same manner as in the processing of the CDMA modulation signal, or may be taken directly into the multi-tap F / F to perform high-speed processing. May be performed. Rather, since the number of bits is small, the same code is often used repeatedly.
/ F is better.

The profiler 57 takes in the output from the second high-speed correlator 58 (or MF), performs an arithmetic operation, and specifies a path. With this, during the initial synchronization stage,
Chip synchronization, symbol synchronization, radio slot synchronization, and frame synchronization can be achieved, and base stations can be specified.
In a communication state in which the connection destination base station is determined, a path is detected. These pieces of information are sent to the control unit 61,
From the control unit 61 to the first high-speed correlator 55, the memory unit 5
4. An instruction is output to the spreading code generator 56. Also, D
For HO, a profiler 57 'is provided, and at the time of DHO, an adjacent base station is specified and its path is specified.

The MF used in place of the second high-speed correlator 58 takes in the spread-spectrum signal and the spread code, and performs a product-sum operation for each symbol. High-speed operation is performed as compared with the chip rate. By operating at high speed, information from a plurality of memories can be processed at an extremely high speed, so that application to an interference canceller becomes possible.

The RAKE synthesizing section 59 includes the finger memory 6
The phase correction using the pilot symbols is performed on the correlation output from the first high-speed correlator 55 taken into the second, and thereafter, a plurality of paths are combined (RAKE combining). In addition, the RAKE combining section 59 includes an AFC for matching the frequency with the received signal, an SIR measuring section for measuring the ratio of the received signal to noise (including interference from other signals) or the current state, and the like. Or included.

The data and voice processing section 60 performs inverse conversion (demodulation) of various signal processings performed on the transmission side in order to perform error correction. This includes deinterleaving, Viterbi decoding, C
There are an RC decoder, Reed-Solomon decoding (or turbo decoding), and audio CODEC.

As described above in detail, according to the correlation circuit for spread spectrum communication according to the embodiment of the present invention, a CDMA demodulation circuit can be constructed with a small gate scale, and a small-scale correlation is expected in the near future. There is an effect that the obtained LSI for mobile terminal can be developed.

[0104]

According to the present invention, there is provided a memory unit capable of simultaneously performing writing and reading of a received spread spectrum signal, and a logic unit which takes in the signal from the memory unit and performs time conversion at high speed. (Time conversion F /
F: multi-tap F / F) and a plurality of delay F / Fs,
Since the correlation circuit is used for spread spectrum communication in which a high-speed correlator performs a product-sum operation at a high speed, there is an effect that correlation can be obtained by reducing the number of constituent elements.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a correlation circuit for spread spectrum communication according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of another spread spectrum communication correlation circuit according to the embodiment of the present invention.

FIG. 3 is a graph showing a state of power consumption in the present invention.

FIG. 4 is a block diagram showing a configuration when the present circuit is used in an interference canceller unit.

FIG. 5 is a block diagram showing a configuration when the present circuit is used for an interference canceller.

FIG. 6 is a configuration block diagram showing a specific example of a circuit for spread spectrum communication according to an embodiment of the present invention.

FIG. 7 is a configuration block diagram of another correlation circuit for spread spectrum communication according to the embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration in which a high-speed correlator is a complex type in the spread spectrum communication correlation circuit according to the embodiment of the present invention.

FIG. 9 is a configuration block diagram of a part of a conventional sliding correlator.

FIG. 10 is a configuration block diagram of a conventional matched filter.

[Explanation of symbols]

11, 31, 41 ... A / D converter, 12 ... control unit,
13 code generator, 14 memory unit, 15 multi-tap F / F, 16 high-speed correlator, 32, 42 multiplier, 33, 43 PN code register, 34, 4
4 Adder, 35 Delay circuit, 45 Sample hold (S / H) circuit, 51 Antenna, 52 RF
Unit, 53: A / D converter, 54: memory unit, 55
... the first high-speed correlator, 56 ... the spreading code generator,
57: a profiler, 58: a second high-speed correlator,
59: RAKE synthesis unit, 60: Data and voice processing unit, 61: Control unit, 62: Finger memory, 63
… Multi-tap F / F

Continuation of the front page (72) Inventor Kenjiro Anari 3-14-20 Higashinakano, Nakano-ku, Tokyo International Electric Co., Ltd. F term (reference) 5K022 EE02 EE32 EE36 5K047 AA16 BB01 GG34 HH15 LL04 MM11 MM24 MM36 MM45 MM53

Claims (9)

[Claims] 1. A spectrum-spread received signal is written to a memory, the written signal is read out from the memory in multiple taps according to a time conversion amount, and stored in a logic unit for performing time conversion. A correlation circuit for spread-spectrum communication, characterized in that it performs a parallel / serial conversion to perform time conversion by operating at a speed higher than a writing speed of a memory, and repeats a process of performing a spreading code and a product-sum operation at a high speed a plurality of times. 2. One or more receiving units for receiving a spread spectrum signal, one or more memory units for holding the received spread spectrum signal, and a high speed signal read from the memory. A logic unit for performing time conversion for performing arithmetic processing, one or more multiplication units for multiplying a signal held in the memory unit with a spreading code, and one or more addition units for adding the multiplication results And time-divides the spread-spectrum signal input from the one or more receiving units in a chip time or a time shorter than the chip time, and holds the time-divided signal in the memory unit for about one symbol. The logic section performs time conversion by reading out the signal held in the memory section by multiple taps according to the time conversion amount and performs high-speed parallel / serial conversion, and performs time conversion by the multiplication section. Performs multiplication of distributed codes,
A correlator for spread spectrum communication, wherein the multiplication result is added by the adder to obtain a correlation. 3. The correlator for spread spectrum communication according to claim 2, wherein the memory unit is a two-port memory capable of simultaneously writing and reading. 4. A multiplying unit for multiplying a 1-bit spreading code by a multi-bit spectrum-spread signal. If the spreading code is "1", the multiplying unit outputs the multi-bit as it is, 4. The correlator for spread spectrum communication according to claim 2, wherein the multiplier is a multiplier that operates by a logic that outputs a multi-bit inversion if is "0". 5. The adder is a cumulative adder having a multi-bit adder, and a delay element that receives an output from the adder as an input, delays the signal by one interval, and returns the delay to the adder. 3. The correlator for spread spectrum communication according to claim 2, wherein 6. A plurality of delay units for sequentially delaying an output from a logic unit and outputting the output while holding the output for each of a plurality of specific bits, wherein the multiplying unit includes a plurality of specific units input from the plurality of delay units. A multiplier that multiplies a bit and a one-bit spreading code by a logic that outputs multi-bits as they are when the spreading code is “1” and outputs multi-bit inversions when the spreading code is “0” 3. The spread spectrum apparatus according to claim 2, wherein the adder is a plurality of multipliers, and the adder is a plurality of multi-bit adders, and the adder is a adder for adding a result of multiplication performed by the multiplier. Correlator for communication. 7. A first A / D converter for performing analog / digital conversion of a quadrature component (Q) in a quadrature detection signal of a received spread spectrum signal, and a quadrature conversion of the received spread spectrum signal. The second A / A which performs analog / digital conversion of the in-phase component (I) in the detection signal
A D converter, a memory unit for storing signals from the first and second A / D converters, and reading data stored from the memory unit in multiple taps according to a time conversion amount, and performing parallel / serial conversion. 1st and 2nd that perform the operation of output
A time conversion logic unit, and a plurality of delay units for sequentially delaying data output from the first and second time conversion logic units,
A correlation circuit for spread spectrum communication, comprising: a plurality of high-speed correlators for calculating a correlation between outputs from the first and second time conversion logic units and outputs from the plurality of delay units at high speed. 8. A correlator for spread spectrum communication according to claim 1, wherein two sets of correlators are provided, wherein the correlator has a common receiving unit, and an in-phase component of a quadrature detection signal of the spread spectrum signal detected by the receiving unit. A correlator for spread spectrum communication, wherein (I) and a quadrature component (Q) are multiplied by different spreading codes, and the respective multiplication results are added. 9. Four sets of correlators for spread spectrum communication according to claim 1, wherein two sets are paired, a common receiving unit is used for the correlators of the pair, and the spread spectrum signal detected by the receiving unit is used. Are multiplied by the first and second different spreading codes in each pair of the in-phase component (I) and the quadrature component (Q) of the quadrature detection signal, and four multiplication results obtained by adding the multiplication results are obtained. A correlator for spread-spectrum communication, wherein results obtained by calculating correlation outputs with the first spreading code and results obtained by calculating with the second spreading code are added and combined.