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JP2000206560A - Active matrix type liquid crystal display - Google Patents

Active matrix type liquid crystal display

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Publication number
JP2000206560A
JP2000206560A JP956399A JP956399A JP2000206560A JP 2000206560 A JP2000206560 A JP 2000206560A JP 956399 A JP956399 A JP 956399A JP 956399 A JP956399 A JP 956399A JP 2000206560 A JP2000206560 A JP 2000206560A
Authority
JP
Japan
Prior art keywords
signal line
pixel electrode
electrode
liquid crystal
shield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP956399A
Other languages
Japanese (ja)
Inventor
Kohei Nagayama
耕平 永山
Yasuyuki Hanazawa
康行 花澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP956399A priority Critical patent/JP2000206560A/en
Publication of JP2000206560A publication Critical patent/JP2000206560A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To prevent a display defect such as cross talk and to obtain high display quality by constituting so that a length of a first part superimposing only on an edge side of a first pixel electrode side of a shield electrode is different from that of a second part superimposing only on the edge side of a second pixel electrode side. SOLUTION: The shield electrode 17 is formed by a shifted area 17B to one pixel electrode 162 side and the shifted area 17A to the adjacent pixel electrode 161 side for a central axis 13a of a signal line 13 so that the effects of one pixel electrode 162 and two adjacent signal lines 13, 13 become equal. Then, the lengths L1, L2 of two areas of the shield electrode 17 are made so as to become L1<L2 as an example. By such a constitution, the high display quality reducing a difference between capacity between the signal line and the pixel electrode and the capacity between the adjacent signal line and the pixel electrode, and eliminating a picture quality defect such as the cross talk and luminance unevenness is obtained while suppressing the increase of the load capacity of the signal line by light shielding a liquid crystal alignment defect area with wiring.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、アクティブマトリ
クス型液晶表示装置に関わる。
The present invention relates to an active matrix type liquid crystal display device.

【0002】[0002]

【従来の技術】近年、高密度かつ大容量でありながら、
高機能、高精細な表示が得られる液晶表示装置の実用化
が進められている。この液晶表示装置には、各種方式が
あるが、中でも隣接画素間のクロストークが小さく、高
コントラストの表示が得られ、透過型表示が可能かつ大
面積化も容易などの理由から、互いに交差する方向に設
けられた複数本の走査線と複数本の信号線により区画さ
れ画素領域となる複数個の領域に薄膜トランジスタ(T
FT)をスイッチング素子とする画素電極がマトリクス
状に設けられたアレイ基板を備えるアクティブマトリク
ス型液晶表示装置が多く用いられている。
2. Description of the Related Art In recent years, while having a high density and a large capacity,
Practical use of liquid crystal display devices capable of obtaining high-performance and high-definition display has been promoted. There are various types of this liquid crystal display device. Among them, the liquid crystal display devices intersect with each other because of small crosstalk between adjacent pixels, high-contrast display, transmission-type display, and easy area enlargement. The thin film transistor (T) is provided in a plurality of regions which are partitioned by a plurality of scanning lines and a plurality of signal lines provided in
An active matrix type liquid crystal display device including an array substrate in which pixel electrodes each having FT) as a switching element are provided in a matrix is widely used.

【0003】画素は開口率の高い構造が望ましく、高開
口率の得られる構造として、信号線と画素電極を重ねる
配線BM(ブラックマトリクス)構造などがある。この
構造は、信号線上に絶縁層を介して画素電極を重ね配線
に遮光体を兼ねさせる構成であり、信号線と画素電極間
の寄生容量が大きい。
[0003] A pixel desirably has a structure with a high aperture ratio. As a structure with which a high aperture ratio can be obtained, there is a wiring BM (black matrix) structure in which a signal line and a pixel electrode are overlapped. This structure has a configuration in which a pixel electrode is overlapped on a signal line via an insulating layer so that the wiring also functions as a light shield, and a parasitic capacitance between the signal line and the pixel electrode is large.

【0004】TFT液晶ディスプレイの表示品位は、信
号線と画素電極との寄生容量によって左右され、この寄
生容量の影響は、補助容量を形成したり一定の電位に固
定されたシールド電極を、層間絶縁膜を介して画素電極
と信号線に重なるように配置することにより抑制するこ
とができる。
[0004] The display quality of a TFT liquid crystal display depends on the parasitic capacitance between a signal line and a pixel electrode. The influence of the parasitic capacitance is caused by forming an auxiliary capacitance or shielding a shield electrode fixed at a constant potential with an interlayer insulating film. This can be suppressed by arranging the pixel electrode and the signal line so as to overlap with each other via the film.

【0005】[0005]

【発明が解決しようとする課題】また、配線BM構造で
は、ラビング方向の下流側の信号線の端部付近に、液晶
の配向不良領域が発生することが知られており、この領
域から光漏れが発生して不良の原因になっている。その
ため、液晶の配向不良領域を配線で遮光するために、信
号線と画素電極の重ね幅を大きくする必要があり、信号
線と画素電極間の寄生容量が増加するといった問題が発
生する。
Further, it is known that, in the wiring BM structure, a liquid crystal misalignment region is generated near the end of the signal line on the downstream side in the rubbing direction. Is occurring and causing a defect. Therefore, it is necessary to increase the overlap width of the signal line and the pixel electrode in order to shield the liquid crystal misalignment region with the wiring, which causes a problem that the parasitic capacitance between the signal line and the pixel electrode increases.

【0006】そこで、信号線と画素電極間の寄生容量の
増加をできるだけ抑えるために、信号線と画素電極の重
ね幅を、液晶の配向不良が発生する部分のみを大きくす
るという方法がある。しかしこの方法では、当該信号線
と画素電極間の容量と、隣接信号線と画素電極間の容量
のバランスがくずれるため、クロストークなどの表示不
良が発生しやすくなる。
In order to suppress the increase in the parasitic capacitance between the signal line and the pixel electrode as much as possible, there is a method in which the overlap width of the signal line and the pixel electrode is increased only in the portion where the liquid crystal alignment failure occurs. However, according to this method, the balance between the capacitance between the signal line and the pixel electrode and the capacitance between the adjacent signal line and the pixel electrode is lost, so that display defects such as crosstalk are likely to occur.

【0007】本発明は、このような不具合を改善するも
のであり、高い表示品位を有するアクティブマトリクス
型液晶表示装置を提供することを目的とする。
An object of the present invention is to improve such a problem and to provide an active matrix type liquid crystal display device having high display quality.

【0008】[0008]

【課題を解決するための手段】本発明は、共通電極を有
する対向基板とこの対向基板とともに液晶層を挟持する
アレイ基板と、このアレイ基板上に形成された複数の走
査線と、前記走査線と交差して形成された複数の信号線
と、前記走査線と前記信号線との交点部近傍に形成され
た薄膜トランジスタと、前記走査線と前記信号線とに囲
まれたそれぞれの領域に形成され相互に隣接する第1画
素電極と第2画素電極を含む複数の画素電極と、前記信
号線に対して交差して形成された補助容量線と、前記補
助容量線から延在し前記信号線に沿って形成されたシー
ルド電極とを有し、前記信号線と前記シールド電極が遮
光体を兼ね、前記遮光体と前記第1画素電極の重畳する
幅と、前記遮光体と前記第2画素電極の重畳する幅が異
なる液晶表示装置において、前記シールド電極は、前記
信号線の縁辺のうち前記第1画素電極側の縁辺のみに重
畳する第1の部分と、前記信号線の縁辺のうち前記第2
画素電極側の縁辺のみに重畳する第2の部分とを有し、
前記第1の部分と前記第2の部分の長さが異なることを
特徴とする液晶表示装置を得るものである。
According to the present invention, there is provided an opposing substrate having a common electrode, an array substrate sandwiching a liquid crystal layer together with the opposing substrate, a plurality of scanning lines formed on the array substrate, and the scanning line. A plurality of signal lines formed to intersect with each other, a thin film transistor formed near an intersection of the scanning line and the signal line, and a thin film transistor formed in each region surrounded by the scanning line and the signal line. A plurality of pixel electrodes including a first pixel electrode and a second pixel electrode adjacent to each other; an auxiliary capacitance line formed to intersect the signal line; And the signal line and the shield electrode also function as a light shield, and the width of the light shield and the first pixel electrode overlap, and the width of the light shield and the second pixel electrode. Liquid crystal display devices with different overlapping widths Oite, the shield electrode has a first portion overlapping only the edge of the first pixel electrode side of the edge of the signal line, the second of edge of the signal line
A second portion overlapping only the edge on the pixel electrode side,
A liquid crystal display device characterized in that the first portion and the second portion have different lengths.

【0009】本発明によれば、液晶配向不良領域を配線
で遮光することによる信号線の負荷容量の増加を抑えな
がら、当該信号線と画素電極間の容量と、隣接信号線と
画素電極間の容量の差が少なく、高い表示品位のアクテ
ィブマトリクス型液晶表示装置を実現することができ
る。
According to the present invention, the capacitance between the signal line and the pixel electrode and the capacitance between the adjacent signal line and the pixel electrode are reduced while suppressing an increase in the load capacitance of the signal line caused by shielding the defective liquid crystal alignment region with wiring. An active matrix liquid crystal display device with a small difference in capacitance and high display quality can be realized.

【0010】[0010]

【発明の実施の形態】以下、この発明の実施の形態につ
いて図面を参照して説明する。図1に本発明の第1の実
施の形態のアクティブマトリクス型液晶表示装置のアレ
イ基板の平面図を示し、図2にその一部拡大図、図3に
図2のAB線に沿って切断した断面図、図4に図2のD
EFGH線に沿う液晶表示装置の一部断面図を示す。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an array substrate of an active matrix type liquid crystal display device according to a first embodiment of the present invention, FIG. 2 is a partially enlarged view thereof, and FIG. 3 is a sectional view taken along line AB in FIG. FIG. 4 is a sectional view, and FIG.
FIG. 2 shows a partial cross-sectional view of the liquid crystal display device along the EFGH line.

【0011】図において、透明ガラスでできた絶縁性基
板11上に、行方向に並行配列された複数の走査線12
と、これに直交するように列方向に平行に配列された複
数の信号線13とが格子状に配置される。これらの走査
線12間に信号線13に直交するように補助容量線14
が設けられる。走査線と信号線が交差する近傍の図示の
下端部にポリシリコンやアモルファスシリコンの活性層
をもつTFT15が配置され、走査線12と信号線13
とで囲まれた領域に、相互に隣接する画素電極16すな
わち161、162、163・・・を配置する。
In FIG. 1, a plurality of scanning lines 12 arranged in parallel in a row direction on an insulating substrate 11 made of transparent glass.
And a plurality of signal lines 13 arranged in parallel in the column direction so as to be orthogonal to the above. A storage capacitor line 14 is provided between these scanning lines 12 so as to be orthogonal to the signal line 13.
Is provided. A TFT 15 having an active layer of polysilicon or amorphous silicon is arranged at the lower end in the drawing near the intersection of the scanning line and the signal line.
Are arranged in the region surrounded by.

【0012】信号線13の縁辺と一つの画素電極162
の周辺部の縁辺の少なくとも一部の切り欠いた部分16
a、16bに重畳するように配設された補助容量線14
の一部を延在させて設けた静電遮蔽性を有するシールド
電極17が、一画素ピッチ内で信号線と交差し、隣接す
る画素電極161の周辺部の縁辺とも図3の幅bで一部
重なるように配設されている。図2中矢印38aは画素
電極162を覆って形成される配向膜38の配向ベクト
ルを示す。以降の図では配向ベクトルを省略する。さら
に、信号線13とシールド電極17は遮光体を兼ねてお
り、配向ベクトルの上手側となる液晶の配向不良領域N
Aが発生する場所(図2においては画素の左側の信号線
に沿った部分)だけ、遮光体(13、17)と画素電極
162の重畳する幅aを大きくしている。シールド電極
17は、1つの画素電極162と隣り合う2つの信号線
13、13の影響が等しくなるように、信号線13の中
心軸13aに対して一つの画素162側のずれ領域17
Bと隣接画素161側へのずれ領域17Aとで形成し
て、そのシールド電極14の領域の長さL1、L2が調
整されて形成されている。一例としてL1<L2とな
る。各ずれ領域に相当する画素電極の縁辺に切り欠け1
6a、16aが設けられ、この部分で信号13は重畳し
ていない。従って、液晶の配向不良領域を隠すことによ
る信号線容量の増加および、信号線13、13と画素電
極162間容量の増加を最小限に抑え、さらに画素電極
162に対してTFT15の接続されている信号線13
の影響と接続されていない信号線13の影響はほぼ同程
度であるため、信号線と画素電極との間の寄生容量の影
響を最小限に抑えることができる。
The edge of the signal line 13 and one pixel electrode 162
At least a part of the peripheral edge of the notch 16
a, the auxiliary capacitance line 14 disposed so as to overlap the 16b
Of the pixel electrode 161 intersects the signal line within one pixel pitch, and the edge of the peripheral portion of the adjacent pixel electrode 161 has a width b in FIG. They are arranged to overlap. In FIG. 2, an arrow 38a indicates an alignment vector of the alignment film 38 formed to cover the pixel electrode 162. In the following figures, the orientation vector is omitted. Further, the signal line 13 and the shield electrode 17 also serve as a light shield, and the liquid crystal misalignment region N which is on the upper side of the alignment vector.
Only at the location where A occurs (the portion along the signal line on the left side of the pixel in FIG. 2), the width a where the light shields (13, 17) and the pixel electrode 162 overlap is increased. The shield electrode 17 is shifted from the central axis 13a of the signal line 13 by one pixel 162 so that the influence of the two signal lines 13 adjacent to one pixel electrode 162 becomes equal.
The shield electrode 14 is formed by adjusting the lengths L1 and L2 of the region of the shield electrode 14 with B and the shift region 17A toward the adjacent pixel 161 side. For example, L1 <L2. Notch 1 at the edge of the pixel electrode corresponding to each shift area
6a and 16a are provided, in which the signal 13 is not superimposed. Therefore, an increase in the signal line capacitance due to hiding the liquid crystal misalignment region and an increase in the capacitance between the signal lines 13 and 13 and the pixel electrode 162 are minimized, and the TFT 15 is connected to the pixel electrode 162. Signal line 13
And the effect of the unconnected signal line 13 is substantially the same, so that the effect of the parasitic capacitance between the signal line and the pixel electrode can be minimized.

【0013】以下図4に基づき上記のアクティブマトリ
クス型液晶表示装置の製造方法について説明する。ま
ず、高融点ガラス基板や石英基板などの透明絶縁性基板
11上にCVD法などによりa−Si膜を50nm程度
被着する。450℃で1時間炉アニールを行った後、X
eClエキシマレーザを照射し、a−Siを多結晶化す
る。その後に、多結晶Siをフォトエッチング法により
パターニングして、表示領域内のTFT15のチャネル
層となる半導体層20を形成した。次に、CVD法によ
り絶縁基板11の全面にゲート絶縁膜21となるSiO
x膜を100nmから150nm程度被着する。続い
て、ゲート絶縁膜21上にTa,Cr,Al,Mo,
W,Cuなどの単体又はその積層膜あるいは合金膜を2
00nmから400nm程度被着し、フォトエッチング
法により、ゲート電極22、ゲート線12、補助容量電
極14を形成した。
A method of manufacturing the above active matrix type liquid crystal display device will be described below with reference to FIG. First, an a-Si film of about 50 nm is deposited on a transparent insulating substrate 11 such as a high melting point glass substrate or a quartz substrate by a CVD method or the like. After furnace annealing at 450 ° C. for 1 hour, X
Irradiation with an eCl excimer laser is performed to polycrystallize a-Si. After that, the polycrystalline Si was patterned by a photoetching method to form a semiconductor layer 20 to be a channel layer of the TFT 15 in the display region. Next, a SiO film to be a gate insulating film 21 is formed on the entire surface of the insulating substrate 11 by CVD.
An x film is deposited on the order of 100 nm to 150 nm. Subsequently, on the gate insulating film 21, Ta, Cr, Al, Mo,
Simple substance such as W or Cu, or a laminated film or alloy film thereof
Then, the gate electrode 22, the gate line 12, and the auxiliary capacitance electrode 14 were formed by photoetching.

【0014】その後、このゲート電極22をマスクとし
てイオン注入やイオンドーピング法により不純物の注入
を行い、画素部のTFT15のドレイン電極23とソー
ス電極24を形成した。不純物の注入は、例えば加速電
圧80kevで5x1015atoms/cmのドー
ズ量で、PH/Hによりリンを高濃度注入した。そ
の後、基板をアニールすることにより不純物を活性化す
る。その後、更にNch型LDD(Lightly D
oped Drain)25、26を形成するための不
純物注入を行い、基板をアニールすることにより不純物
を活性化する。
Thereafter, using the gate electrode 22 as a mask, impurities are implanted by ion implantation or ion doping to form a drain electrode 23 and a source electrode 24 of the TFT 15 in the pixel portion. For the impurity implantation, for example, phosphorus was implanted at a high concentration of PH 3 / H 2 at an acceleration voltage of 80 keV and at a dose of 5 × 10 15 atoms / cm 2 . Then, impurities are activated by annealing the substrate. Thereafter, an Nch-type LDD (Lightly D
The impurities are implanted to form the O.Drains 25 and 26, and the substrate is annealed to activate the impurities.

【0015】更に、例えばPECVD法を用いて絶縁基
板の全面に層間絶縁膜SiO27を500nmから7
00nm程度被着する。続いて、フォトエッチング法に
より、画素部のTFT15のドレイン電極23とソース
電極24に至るコンタクトホール28(図2)を形成し
た。次に、Ta,Cr,A1,Mo,W,Cuなどの単
体又はその積層膜あるいは合金膜を500nm〜700
nm程度被着し、フォトエッチング法により所定の形状
にパターンニングし、信号線13、補助容量電極14、
TFT15のドレイン電極23と信号線13の接続の各
種配線等を行った。次に、PECVD法により絶縁基板
の全面にSiNxからなる透明保護絶縁膜29を成膜
し、フォトエッチング法により第1のスルーホール30
を形成する。次に有機絶縁層31を全面に2μmから4
μmほど塗布し、補助容量素子の上部電極14に至る第
2のスルーホール32を形成する。次に、ITOをスパ
ッタ法により100nm程度成膜し、フォトエッチング
法により所定の形状にパターンニングして、画素電極1
6を形成した。以上の工程により、アクティブマトリク
ス型液晶表示素子のアレイ基板33が得られる。
Further, an interlayer insulating film SiO 2 27 is formed on the entire surface of the insulating substrate from 500 nm to 7
Deposit about 00 nm. Subsequently, a contact hole 28 (FIG. 2) reaching the drain electrode 23 and the source electrode 24 of the TFT 15 in the pixel portion was formed by photoetching. Next, a simple substance such as Ta, Cr, A1, Mo, W, Cu, or a laminated film or an alloy film thereof is formed to a thickness of 500 nm to 700 nm.
and then patterned into a predetermined shape by a photo-etching method to form a signal line 13, an auxiliary capacitance electrode 14,
Various wirings for connection between the drain electrode 23 of the TFT 15 and the signal line 13 were performed. Next, a transparent protective insulating film 29 made of SiNx is formed on the entire surface of the insulating substrate by PECVD, and the first through hole 30 is formed by photoetching.
To form Next, an organic insulating layer 31 is coated on the entire surface from 2 μm to 4 μm.
A second through hole 32 is formed to reach the upper electrode 14 of the auxiliary capacitance element by applying a thickness of about μm. Next, ITO is deposited to a thickness of about 100 nm by a sputtering method, and is patterned into a predetermined shape by a photo etching method.
6 was formed. Through the above steps, the array substrate 33 of the active matrix type liquid crystal display element is obtained.

【0016】一方、透明性絶縁基板35として例えばガ
ラス基板上に、スパッタ法により例えばITOからなる
透明性電極である対向電極36を形成することにより、
対向基板37が得られる。続いて、アレイ基板33と対
向基板37の画素電極16側と対向電極36側全面に低
温キュア型のポリイミドからなる配向膜38、39、を
印刷塗布し、両基板33、37、の対向時に配向軸が9
0°となるようにラビング処理をした後、両基板33、
37を対向して組み立て、セル化し、その間隙にネマテ
ィック液晶層40を注入し封止する。そして、両基板3
3、37の絶縁基板11、35側に偏光板41、42を
貼り付けることにより液晶表示装置が得られる。
On the other hand, a counter electrode 36 which is a transparent electrode made of, for example, ITO is formed on a glass substrate, for example, as a transparent insulating substrate 35 by a sputtering method.
The counter substrate 37 is obtained. Subsequently, alignment films 38 and 39 made of low-temperature curing type polyimide are applied by printing on the entire surface of the array substrate 33 and the counter substrate 37 on the pixel electrode 16 side and the counter electrode 36 side, and the alignment is performed when the substrates 33 and 37 face each other. Axis 9
After performing a rubbing process so as to be 0 °, both substrates 33,
37 are assembled facing each other to form a cell, and a nematic liquid crystal layer 40 is injected into the gap and sealed. And both substrates 3
By attaching the polarizing plates 41 and 42 to the insulating substrates 3 and 37 on the side of the insulating substrates 11 and 35, a liquid crystal display device is obtained.

【0017】このようにして出来上がったアレイ基板3
3では、液晶の配向不良が発生する領域だけ、遮光体
(13、17)と画素電極16の重なり幅を大きくする
ので、信号線13の容量の増加と、信号線13と画素電
極16間容量の増加を最小限に抑えることができる。ま
た、当該信号線13と画素電極16間の容量と、隣接信
号線13と画素電極16間の容量がほぼ等しくなるの
で、クロストークや輝度むらといった画質不良の無い良
好な表示が得られた。また、本発明は種々変形が可能で
ある。以下図1と同符号の部分は同様部分を示す。
The array substrate 3 thus completed
In No. 3, since the overlap width of the light shields (13, 17) and the pixel electrode 16 is increased only in the region where the liquid crystal alignment failure occurs, the capacity of the signal line 13 is increased, and the capacity between the signal line 13 and the pixel electrode 16 is increased. Can be minimized. In addition, since the capacitance between the signal line 13 and the pixel electrode 16 and the capacitance between the adjacent signal line 13 and the pixel electrode 16 are substantially equal, a good display without image quality defects such as crosstalk and uneven brightness was obtained. Further, the present invention can be variously modified. Hereinafter, the same reference numerals as those in FIG. 1 indicate the same parts.

【0018】図5に示す第2の実施の形態は、図1に示
す実施の形態において、シールド電極17ではなく信号
線130の両画素電極側に切込み51、52を設けて、
このシールド電極17の中心17aに対して非直線の鍵
型に形成した場合である。この様な構成にしても、上記
実施例と同様の効果が得られる。
The second embodiment shown in FIG. 5 is different from the embodiment shown in FIG. 1 in that notches 51 and 52 are provided on both pixel electrode sides of the signal line 130 instead of the shield electrode 17.
This is a case where the shield electrode 17 is formed in a non-linear key shape with respect to the center 17a. Even with such a configuration, the same effect as in the above embodiment can be obtained.

【0019】図6に示す第3の実施の形態は、図1に示
す実施例において、シールド電極170を前段のゲート
線120から延在させて形成した場合である。このよう
な構成では、補助容量線が不要になり、高い開口率を得
ることができる。
The third embodiment shown in FIG. 6 is a case where the shield electrode 170 is formed so as to extend from the previous gate line 120 in the embodiment shown in FIG. In such a configuration, a storage capacitor line is not required, and a high aperture ratio can be obtained.

【0020】図7に示す第4の実施の形態は、液晶の配
向不良領域が発生する信号線131の端部、すなわち、
信号線131と画素電極16の重畳する幅の大きい側の
みにシールド電極170を補助容量線14から延在させ
て形成した場合である。このシールド電極170の長さ
L1は、画素電極16と隣り合う2つの信号線131、
132の影響が等しくなるように、シールド電極の長さ
が調整されて形成されている。この様な構成にしても、
上記実施の形態と同様の効果が得られる。図8に示す第
5の実施の形態は、第1のシールド電極171と第2の
シールド電極172を信号線13の両側に補助容量線1
4から延在させて形成した場合であり、第1のシールド
電極171の長さL1と第2のシールド電極172の長
さL2が異なっている。
In the fourth embodiment shown in FIG. 7, the end portion of the signal line 131 where a liquid crystal misalignment region occurs, that is,
This is a case where the shield electrode 170 is formed to extend from the auxiliary capacitance line 14 only on the wide side where the signal line 131 and the pixel electrode 16 overlap with each other. The length L1 of the shield electrode 170 is determined by two signal lines 131 adjacent to the pixel electrode 16,
The length of the shield electrode is adjusted so that the effects of 132 are equal. Even with such a configuration,
The same effects as in the above embodiment can be obtained. In the fifth embodiment shown in FIG. 8, the first shield electrode 171 and the second shield electrode 172 are provided on both sides of the signal line 13 in the auxiliary capacitance line 1.
4, the length L1 of the first shield electrode 171 and the length L2 of the second shield electrode 172 are different.

【0021】図9は、図8をAB線に沿って切断した断
面図であり、第1のシールド電極171と画素電極16
2の重畳する幅cと第2のシールド電極172と隣の画
素電極161の重畳するdが異なっている。この様な構
成にしても上記実施の形態と同様の効果が得られる。
FIG. 9 is a cross-sectional view of FIG. 8 taken along the line AB, showing the first shield electrode 171 and the pixel electrode 16.
2 and the overlapping width c of the second shield electrode 172 and the adjacent pixel electrode 161 are different. Even with such a configuration, the same effect as in the above embodiment can be obtained.

【0022】また、本実施の形態は半導体層としてポリ
シリコン層を用いたアクティブマトリクス型液晶表示装
置に関して記述したが、本発明は半導体層として例えば
アモルファスシリコン層等の他の半導体層を用いたアク
ティブマトリクス型液晶表示装置についても同様の効果
が得られる。
Although this embodiment has been described with reference to an active matrix type liquid crystal display device using a polysilicon layer as a semiconductor layer, the present invention relates to an active matrix liquid crystal display device using another semiconductor layer such as an amorphous silicon layer as a semiconductor layer. Similar effects can be obtained for a matrix type liquid crystal display device.

【0023】[0023]

【発明の効果】以上詳述したように、この発明による
と、液晶の配向不良が発生する領域だけ遮光体と画素電
極の重なり幅を大きくするので、信号線容量の増加及び
信号線と画素電極間容量の増加を最小限に抑えることが
できる。また、当該自信号線と画素電極間の容量と、隣
接信号線と画素電極間の容量をほぼ等しくすることがで
きるので、クロストークや輝度むらといった画質不良の
無いアクティブマトリクス型液晶表示装置を実現するこ
とができる。
As described above in detail, according to the present invention, the overlap width between the light shield and the pixel electrode is increased only in the region where the liquid crystal alignment defect occurs, so that the signal line capacitance is increased and the signal line and the pixel electrode are not increased. The increase in the inter-volume can be minimized. In addition, since the capacitance between the signal line and the pixel electrode can be substantially equal to the capacitance between the adjacent signal line and the pixel electrode, an active matrix liquid crystal display device free from poor image quality such as crosstalk and uneven brightness can be realized. be able to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態におけるアクティブ
マトリクス型液晶表示装置の一画素平面図
FIG. 1 is a plan view of one pixel of an active matrix liquid crystal display device according to a first embodiment of the present invention.

【図2】図1における一部拡大平面図FIG. 2 is a partially enlarged plan view of FIG.

【図3】図2をAB線で切断したアレイ基板の断面図FIG. 3 is a cross-sectional view of the array substrate taken along a line AB in FIG. 2;

【図4】図2におけるDEFGH線で切断したアレイ基
板およびこれと対応する対向基板を含んだ液晶表示装置
の一部断面図
FIG. 4 is a partial cross-sectional view of a liquid crystal display device including an array substrate and a counter substrate corresponding thereto taken along the line DEFGH in FIG. 2;

【図5】本発明の2の実施の形態の一画素平面図FIG. 5 is a plan view of one pixel according to a second embodiment of the present invention.

【図6】本発明の第3の実施の形態の一画素平面図FIG. 6 is a plan view of one pixel according to a third embodiment of the present invention.

【図7】本発明の第4の実施の形態の一画素平面図FIG. 7 is a plan view of one pixel according to a fourth embodiment of the present invention.

【図8】本発明の第5の実施の形態の一画素平面図FIG. 8 is a plan view of one pixel according to a fifth embodiment of the present invention.

【図9】図8におけるAB線で切断したアレイ基板の断
面図
FIG. 9 is a sectional view of the array substrate taken along line AB in FIG. 8;

【符号の説明】[Explanation of symbols]

12:走査線 13:信号線 14:補助容量線 15:TFT 16、161、162、・・・:画素電極 17:シールド電極 33:アレイ基板 37:対向基板 40:液晶層 12: scanning line 13: signal line 14: storage capacitance line 15: TFT 16, 161 162,...: Pixel electrode 17: shield electrode 33: array substrate 37: counter substrate 40: liquid crystal layer

フロントページの続き Fターム(参考) 2H092 JA25 JA29 JA35 JA38 JA39 JA42 JA44 JB13 JB23 JB32 JB33 JB42 JB52 JB57 JB63 JB69 KA04 KA07 KA12 KA16 KA18 KB14 KB23 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA28 MA35 MA37 MA41 NA01 NA23 NA24 NA25 QA07 Continued on the front page F-term (reference) 2H092 JA25 JA29 JA35 JA38 JA39 JA42 JA44 JB13 JB23 JB32 JB33 JB42 JB52 JB57 JB63 JB69 KA04 KA07 KA12 KA16 KA18 KB14 KB23 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 NA25 QA07

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 共通電極を有する対向基板とこの対向基
板とともに液晶層を挟持するアレイ基板と、このアレイ
基板上に形成された複数の走査線と、前記走査線と交差
して形成された複数の信号線と、前記走査線と前記信号
線との交点部近傍に形成された薄膜トランジスタと、前
記走査線と前記信号線とに囲まれたそれぞれの領域に形
成され相互に隣接する第1画素電極と第2画素電極を含
む複数の画素電極と、前記信号線に対して交差して形成
された補助容量線と、前記補助容量線から延在し前記信
号線に沿って形成されたシールド電極とを有し、前記信
号線と前記シールド電極が遮光体を兼ね、前記遮光体と
前記第1画素電極の重畳する幅と、前記遮光体と前記第
2画素電極の重畳する幅が異なる液晶表示装置におい
て、前記シールド電極は、前記信号線の縁辺のうち前記
第1画素電極側の縁辺のみに重畳する第1の部分と、前
記信号線の縁辺のうち前記第2画素電極側の縁辺のみに
重畳する第2の部分とを有し、前記第1の部分と前記第
2の部分の長さが異なることを特徴とする液晶表示装
置。
1. A counter substrate having a common electrode, an array substrate sandwiching a liquid crystal layer together with the counter substrate, a plurality of scanning lines formed on the array substrate, and a plurality of lines formed intersecting the scanning lines. And a thin film transistor formed near the intersection of the scanning line and the signal line, and a first pixel electrode formed in each region surrounded by the scanning line and the signal line and adjacent to each other And a plurality of pixel electrodes including a second pixel electrode, an auxiliary capacitance line formed crossing the signal line, a shield electrode extending from the auxiliary capacitance line and formed along the signal line. A liquid crystal display device, wherein the signal line and the shield electrode also serve as a light shield, and a width at which the light shield and the first pixel electrode overlap is different from a width at which the light shield and the second pixel electrode overlap. In the above, the shield electrode A first portion overlapping only the first pixel electrode side edge of the signal line edge, and a second portion overlapping only the second pixel electrode side edge of the signal line edge. Wherein the first portion and the second portion have different lengths.
【請求項2】 前記信号線は略直線状の中心軸を有し、
前記信号線に沿って形成されるシールド電極は、前記中
心軸に対して前記第1画素電極側にずれて形成された部
分と、前記第2画素電極側にずれて形成された部分とを
有する非直線形状であることを特徴とする請求項1記載
の液晶表示装置。
2. The signal line has a substantially linear center axis,
The shield electrode formed along the signal line has a portion formed to be shifted toward the first pixel electrode with respect to the central axis and a portion formed to be shifted toward the second pixel electrode. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device has a non-linear shape.
【請求項3】 前記信号線はその中心軸に対して前記第
1画素電極側にずれて形成された部分と、前記第2画素
電極側にずれて形成された部分とを有する非直線形状で
あることを特徴とする請求項1記載の液晶表示装置。
3. The signal line has a non-linear shape having a portion shifted toward the first pixel electrode and a portion shifted toward the second pixel electrode with respect to a center axis thereof. 2. The liquid crystal display device according to claim 1, wherein:
【請求項4】 前記信号線の少なくとも一部が、前記第
1の部分において前記第1画素電極と、かつ前記第2の
部分において前記第2の画素電極と重畳しないことを特
徴とする請求項1記載の液晶表示装置。
4. The signal line according to claim 1, wherein at least a part of said signal line does not overlap with said first pixel electrode in said first part and with said second pixel electrode in said second part. 2. The liquid crystal display device according to 1.
【請求項5】 前記信号線と前記シールド電極で形成さ
れる遮光体が直線状であることを特徴とする請求項1記
載の液晶表示装置。
5. The liquid crystal display device according to claim 1, wherein the light shield formed by the signal line and the shield electrode is linear.
【請求項6】 基板上に形成された複数の走査線と、前
記走査線と交差して形成された複数の信号線と、前記走
査線と前記信号線との交点部近傍に形成された薄膜トラ
ンジスタと、前記走査線と前記信号線とに囲まれたそれ
ぞれの領域に形成された複数の画素電極と、前記信号線
に対して交差して形成された補助容量線と、前記補助容
量線から延在し前記信号線に沿って形成されたシールド
電極とを有し、前記信号線と前記シールド電極が遮光体
を兼ね、前記遮光体と前記画素電極のうちの第1画素電
極に重畳する幅と、前記遮光体と前記が疎電極のうちの
前記第1画素電極に隣接する第2画素電極に重畳する幅
とが異なる液晶表示装置において、前記シールド電極
は、前記信号線の縁辺のうち前記第2画素電極側の縁辺
のみに重畳する第2の部分を有することを特徴とする液
晶表示装置。
6. A plurality of scanning lines formed on a substrate, a plurality of signal lines formed to intersect with the scanning lines, and a thin film transistor formed near an intersection of the scanning lines and the signal lines. A plurality of pixel electrodes formed in respective regions surrounded by the scanning lines and the signal lines; an auxiliary capacitance line formed to intersect with the signal line; And a shield electrode formed along the signal line, the signal line and the shield electrode also function as a light shield, and a width overlapping the light shield and a first pixel electrode of the pixel electrodes. A liquid crystal display device having a light-shielding body and a width overlapping the second pixel electrode adjacent to the first pixel electrode of the sparse electrode, wherein the shield electrode is the first of the edges of the signal line. The second superimposed only on the edge on the two pixel electrode side A liquid crystal display device having a portion.
【請求項7】 基板上に形成された複数の走査線と、前
記走査線と交差して形成された複数の信号線と、前記走
査線と前記信号線との交点部近傍に形成された薄膜トラ
ンジスタと、前記走査線と前記信号線とに囲まれたそれ
ぞれの領域に形成された複数の画素電極と、前記信号線
に対して直交して形成された補助容量線と、前記補助容
量線から延在し前記信号線に沿って形成されたシールド
電極とを有し、前記信号線と前記シールド電極が遮光体
を兼ね、前記遮光体と第1画素電極の重畳する幅と、前
記遮光体と第2画素電極の重畳する幅が異なる液晶表示
装置において、前記補助容量線から延在し前記信号線に
沿って形成された第1のシールド電極と第2のシールド
電極が、前記信号線の両辺に重畳する部分を有し、前記
第1のシールド電極と前記第2のシールド電極の長さが
異なることを特徴とする液晶表示装置。
7. A plurality of scanning lines formed on a substrate, a plurality of signal lines formed crossing the scanning lines, and a thin film transistor formed near an intersection of the scanning lines and the signal lines. A plurality of pixel electrodes formed in respective regions surrounded by the scanning lines and the signal lines; an auxiliary capacitance line formed orthogonal to the signal lines; And a shield electrode formed along the signal line, wherein the signal line and the shield electrode also serve as a light shield, and the width of the light shield and the first pixel electrode overlapping each other; In a liquid crystal display device in which two pixel electrodes have different overlapping widths, a first shield electrode and a second shield electrode extending from the auxiliary capacitance line and formed along the signal line are provided on both sides of the signal line. The first shield electrode having an overlapping portion; And a length of the second shield electrode is different.
【請求項8】 前記走査線は前記補助容量線を兼ね、前
記シールド電極は前記走査線から延在していることを特
徴とする請求項1、6および7のいずれかに記載の液晶
表示装置。
8. The liquid crystal display device according to claim 1, wherein the scanning line also serves as the auxiliary capacitance line, and the shield electrode extends from the scanning line. .
【請求項9】 基板上に形成された複数の走査線と、前
記走査線と交差して形成された複数の信号線と、前記走
査線と前記信号線との交点部近傍に形成された薄膜トラ
ンジスタと、前記走査線と前記信号線とに囲まれたそれ
ぞれの領域に形成された複数の画素電極と、前記信号線
に対して直交して形成された補助容量線と、前記補助容
量線から延在し前記信号線に沿って形成されたシールド
電極とを有し、前記信号線と前記シールド電極が遮光体
を兼ね、前記遮光体と第1画素電極の重畳する幅と、前
記遮光体と第2画素電極の重畳する幅が異なる液晶表示
装置において、前信号線に隣接する画素電極の縁辺に前
記信号線と重畳しない欠け部を形成してこの欠け部を覆
ってその周囲の前記信号線と前記画素電極に重畳するよ
うにシールド電極を配置してなる液晶表示装置。
9. A plurality of scanning lines formed on a substrate, a plurality of signal lines formed to intersect with the scanning lines, and a thin film transistor formed near an intersection of the scanning lines and the signal lines. A plurality of pixel electrodes formed in respective regions surrounded by the scanning lines and the signal lines; an auxiliary capacitance line formed orthogonal to the signal lines; And a shield electrode formed along the signal line, wherein the signal line and the shield electrode also serve as a light shield, and the width of the light shield and the first pixel electrode overlapping each other; In a liquid crystal display device in which two pixel electrodes overlap with each other in different widths, a notch that does not overlap with the signal line is formed at an edge of a pixel electrode adjacent to a previous signal line, and the notch is covered with the signal line around the notch. A shield electrode is superimposed on the pixel electrode. Liquid crystal display device arranged.
JP956399A 1999-01-18 1999-01-18 Active matrix type liquid crystal display Pending JP2000206560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP956399A JP2000206560A (en) 1999-01-18 1999-01-18 Active matrix type liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP956399A JP2000206560A (en) 1999-01-18 1999-01-18 Active matrix type liquid crystal display

Publications (1)

Publication Number Publication Date
JP2000206560A true JP2000206560A (en) 2000-07-28

Family

ID=11723773

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004038041A (en) * 2002-07-05 2004-02-05 Chi Mei Electronics Corp Image display element and image display device
JP2005215341A (en) * 2004-01-29 2005-08-11 Sharp Corp Display device
JP2007094261A (en) * 2005-09-30 2007-04-12 Epson Imaging Devices Corp Semi-transparent liquid crystal display panel
US7394513B2 (en) 2004-02-04 2008-07-01 Sharp Kabushiki Kaisha Display device having particular signal lines
US7773049B2 (en) 2004-05-13 2010-08-10 Sharp Kabushiki Kaisha Crosstalk elimination circuit, liquid crystal display apparatus, and display control method
US8253872B2 (en) 2004-01-29 2012-08-28 Sharp Kabushiki Kaisha Liquid crystal display device having source-drain parasitic capacitances of a delta arrangement

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004038041A (en) * 2002-07-05 2004-02-05 Chi Mei Electronics Corp Image display element and image display device
JP2005215341A (en) * 2004-01-29 2005-08-11 Sharp Corp Display device
US8253872B2 (en) 2004-01-29 2012-08-28 Sharp Kabushiki Kaisha Liquid crystal display device having source-drain parasitic capacitances of a delta arrangement
US7394513B2 (en) 2004-02-04 2008-07-01 Sharp Kabushiki Kaisha Display device having particular signal lines
US7773049B2 (en) 2004-05-13 2010-08-10 Sharp Kabushiki Kaisha Crosstalk elimination circuit, liquid crystal display apparatus, and display control method
JP2007094261A (en) * 2005-09-30 2007-04-12 Epson Imaging Devices Corp Semi-transparent liquid crystal display panel

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