JP2000201299A - Amplification type solid-state image pickup device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate the scatter of the threshold voltage of intra-pixel amplification transistors. SOLUTION: This device is provided with pixels each of which having a photodiode capable of being shifted from a 1st potential state (reset state) to a 2nd potential state corresponding to incident light quantity. A unit compensating circuit is provided with 1st and 2nd accumulation elements 35 and 41 each of which is composed of a MOS capacitor. The element 35 accumulates the charge of quantity being proportional to the difference between signal potential ϕs corresponding to the 2nd potential state of the pixel and reference potential ϕ0. The element 41 accumulates the charge of quantity being proportional to the difference between fixed potential ϕd and reference potential ϕ0. The both accumulation elements are made to be short-circuited when reset potential ϕr is supplied from the pixel, the charge of quantity being proportional to potential difference (ϕs-ϕr) is accordingly transferred between both accumulation elements. After separating both accumulation elements electrically, the potential difference (ϕs-ϕr) remaining on the element 41 is detected and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an amplification type solid-state imaging device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, the necessity of a device for detecting a one-dimensional / two-dimensional distribution of the amount of light has been increased, and in the field of solid-state imaging devices, so-called amplifying solid-state imaging devices have been attracting attention. Each of a plurality of pixels provided in the amplification type solid-state imaging device receives light irradiation, generates a signal charge by photoelectric conversion, generates a signal charge, accumulates the signal charge, and responds to the amount of the signal charge. And a detection circuit having an amplifying transistor for outputting the output signal. The storage section is connected to a control terminal section of the amplifying transistor (for example, a gate electrode of a MOS transistor, a base section of a bipolar transistor, or the like), and outputs an output value of the detection circuit by a potential of the storage section that changes according to a signal charge amount. Is controlled.

[0003]

The amplification type solid-state imaging device includes an amplification transistor functioning as a detection circuit for each pixel, but a plurality of amplification transistors in one device are mounted on the same substrate. Even when manufactured by the same process, they do not have completely uniform characteristics. For example, when the threshold voltage (Vt) of the transistor of the detection circuit varies, even when the light with a uniform amount of light enters the photoelectric conversion unit and the potential of the control terminal unit becomes equal, the output value of the transistor may be reduced. Will vary. As a result, the spatially fixed noise (FP
N: fixed pattern noise) occurs, which significantly impairs image quality.

SUMMARY OF THE INVENTION It is an object of the present invention to accurately compensate for the influence of the characteristics of the amplifying transistor of the detection circuit for each pixel regardless of the amount of received light and read out the information from the information storage section more accurately and at high speed. An object of the present invention is to provide an amplifying solid-state imaging device and a driving method thereof.

[0005]

In order to achieve the above object, the present invention provides a first and a second storage element each constituted by a MOS capacitor, and a switching element for connecting and disconnecting the two storage elements. The provided unit compensation circuit is employed for each pixel column.

More specifically, the amplification type solid-state imaging device according to the present invention includes: a photoelectric conversion unit that transitions from a first potential state according to a reset operation to a second potential state according to light intensity; An amplifying element for detecting the first potential state and the second potential state of the photoelectric conversion unit and outputting a first signal and a second signal, respectively; and An amplification type solid-state imaging device comprising: a compensation circuit that obtains one signal and the second signal and outputs a third signal. In addition, the compensation circuit includes a first storage element composed of a MOS capacitor having a first electrode and a second electrode, and a first storage element composed of another MOS capacitor having a first electrode and a second electrode. A second storage element; means for applying a fixed potential to a first electrode of the second storage element;
A switching element for connecting / disconnecting a second electrode of the storage element and a second electrode of the second storage element, and applying a signal potential corresponding to the second signal to the first electrode of the first storage element. Means for applying the same reference potential to the second electrode of the first storage element and the second electrode of the second storage element, and the second electrode of the first storage element and the second storage element. Charge supply means for supplying charge to the second electrode;
Means for applying a reset potential according to the first signal to the first electrode of the first storage element instead of the signal potential, and wherein the reset potential is applied to the first electrode of the first storage element. In the state where the fixed potential is applied to the first electrode of the second storage element, charge transfer occurs between the second electrode of the first storage element and the second electrode of the second storage element. Means for conducting the switching element such that the potential of the second electrode of the first storage element is equal to the potential of the second electrode of the second storage element; and the switching after the movement of the charge occurs. Means for outputting the third signal in accordance with the amount of charge stored in the second storage element in a state where the element is turned off.

In a preferred embodiment, the switching element is constituted by a MOS transistor having a gate electrode, and the gate electrode of the switching element is a first electrode of the first storage element and a first electrode of the second storage element. Partially overlap with each other. Preferably, the gate electrode of the switching element, the first electrode of the first storage element, and the first electrode of the second storage element are each formed of a polycrystalline silicon film deposited on a silicon substrate via an insulating film. Is formed.

In a preferred embodiment, the charge supply means supplies a charge to a second electrode of the second storage element through a second electrode of the first storage element when the switching element is in a conductive state. Means for supplying. Alternatively, the charge supply unit may be configured to perform the second operation of the second storage element while the switching element is in a conductive state.
Means for supplying charge to the second electrode of the first storage element through the electrode.

In a preferred embodiment, the amplifying element is an amplifying transistor whose current driving force changes according to a potential state of the photoelectric conversion unit, and outputs a potential signal according to a current flowing through the amplifying transistor to the second transistor. A load element for generating the first signal and the second signal is further provided.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an amplification type solid-state imaging device according to the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows a schematic configuration of an amplification type solid-state imaging device 1 according to the present invention. The device 1 in FIG. 1 includes a plurality of pixels 2 arranged in a matrix in an imaging area of a semiconductor substrate formed of single crystal silicon. Here, it is assumed that the number of rows is N and the number of columns is M (N and M are both integers of 2 or more). In the case of a solid-state imaging device, N is typically 50 to 2000, and M is 50 to 2000. Each pixel 2 includes a photoelectric conversion unit such as a photodiode (not shown) in FIG. 1 and a storage unit. Each storage unit is output from the photoelectric conversion unit according to the intensity of light incident on the photoelectric conversion unit. The stored information can be stored as a “potential or charge amount”. The photoelectric conversion unit is in the first potential state at the time of reset, and thereafter transitions to the second potential state due to light incidence. Second
Indicates different levels depending on the intensity of incident light. The level difference between the second potential state and the first potential state corresponds to the amount of light incident on the pixel 2 after the reset. The internal configuration of each pixel 2 will be described later.

The device 1 has a plurality of wirings and circuits for selecting a specific pixel from the plurality of pixels 2 and accessing the selected pixel. These wirings and circuits, transistor elements constituting each pixel, and the like are formed on a substrate by using a technique similar to a known technique for manufacturing a semiconductor integrated circuit.

In this embodiment, a vertical (row selection) shift register 3 is electrically connected to all the pixels 2 via a reset wiring 4 and a row selection line 5. One reset wiring 4 is connected to all of the plurality of pixels 2 in one corresponding row. Similarly, one row selection line 5
Are connected to all of the plurality of pixels 2 in one corresponding row. From the vertical shift register 3, a set of wirings 4 and 5 extends by a number equal to the number of rows of the pixels 2.

In order to select a specific row from a plurality of rows, the vertical shift register 3 changes the potential of the row selection line 5 assigned to the specific row from, for example, logic “Low” to logic “H”.
selectively "to" high ". At this time, the potential of a row selection line corresponding to another row is set to logic “Low”. As a result, a potential corresponding to the logic “High” is supplied to the control terminals of the switching elements (not shown in FIG. 1) in all the pixels 2 included in the specific row, and the switching elements are turned on. By the conduction of the switching element, a potential corresponding to the information stored in each storage unit in the selected row appears on the corresponding vertical signal line 6. At this time, in a row other than the selected row, the storage section in each pixel 2 and the corresponding vertical signal line 6 are non-conductive. The circuit for detecting such information and its operation will be described later in detail.

In this way, after the information in the storage section is read from all the pixels 2 included in a certain selected row to all the vertical signal lines 6, the information in each column is horizontally (column). Selection) The data is sequentially read out one by one by the operation of the shift register 7. Note that a first power supply terminal (V _dd ) 26, a load element 27 for each column, and a second power supply terminal (V _ss ) 28 are provided for reading information of each column.

The image pickup apparatus 1 of the present embodiment includes a compensation circuit 8 for compensating the potential information read from each pixel and reproducing more accurate information. The compensating circuit 8 is divided into M unit compensating circuits 18 assigned to each column. Each unit compensation circuit 18 can generate and hold a charge amount corresponding to the difference between the signal level of the read data and the signal level at the time of reset. As a result, even if the “signal level” of the signal potential on the vertical signal line 6 includes a “variation component”, the variation component is compensated by the reset signal potential including the variation component in the same manner. The information can be reproduced with offset and reduced variation.

The outputs of the M unit compensation circuits 18 are connected to one horizontal signal line 10 via the switching element 9. A control unit (for example, M
The gate electrode of the OS transistor) is connected to the horizontal shift register 7. The horizontal shift register 7 selectively conducts only one of the M switching elements 9. As a result, the information read out simultaneously from the M pixels 2 belonging to a certain selected row subsequently appears on the horizontal signal line 10 for each column via the compensation circuit 8. The information is finally output as potential information (pixel information) via an output buffer (output amplifier) 11.

Next, the configuration and operation of the unit compensation circuit 18 will be described in more detail with reference to FIG. The circuit diagram of FIG. 2 illustrates the unit compensation circuit 18 and other related main elements in the imaging device 1.

The unit compensation circuit 18 is connected to each pixel 2 belonging to a corresponding column. FIG. 2 shows a single pixel 2, but in reality, a plurality of pixels 2 arranged in one row are connected to one unit compensation circuit 18 assigned to that row ( (See FIG. 1). here,
For simplicity, the relationship between one representative pixel 2 and the corresponding unit compensation circuit 18 will be described.

As shown in FIG. 2, the pixel 2 includes a photodiode 21 and a MOS transistor 23 having a gate electrode 22 connected to the photodiode 21. The photodiode 21 is, for example, a pn junction diode or the like formed in a silicon substrate, and serves as both a photoelectric conversion unit that photoelectrically converts incident light to generate signal charges and a storage unit that stores the signal charges. It is. MOS transistor 23 has, for example, a normal MOS structure having a channel region and a source / drain region in a silicon substrate. The MOS transistor 23 functions as a driving element of the detection circuit, and the detection circuit plays an important role in amplifying and reading a small change in the potential state of the photodiode 21. In this embodiment, no special capacitance element is inserted between the gate electrode 22 of the MOS transistor 23 and the photodiode 21, but a capacitance element such as a capacitor may be inserted here. In this case, the inserted capacitive element functions as a storage unit for storing signal charges.

The pixel 2 further includes a reset element 24 and a switching element 25. Reset element 24
Is an M having a gate electrode connected to the reset wiring 4.
OS transistor. The drain of this MOS transistor is connected to a first power supply terminal (V _dd ) 26,
The source is connected to the photodiode 21. When the potential of the illustrated reset wiring 4 is selectively changed from logic “Low” to logic “High” by the vertical shift register 3, the reset element 24 becomes conductive,
As a result, from the first power supply terminal 26 to the photodiode 21
Is supplied with a power supply potential. The potential state of the photodiode 21, that is, the amplifying transistor 2
The potential state of the third gate electrode 22 is forcibly returned ("reset") to a certain value determined by the power supply potential (V _dd ) applied to the first power supply terminal 26. The photodiode 2 when such a reset operation is completed
Here, the 1 potential state is defined as a “first potential state”. After the reset operation is completed, the potential of the photodiode 21 gradually changes according to the intensity of light received by the pixel 2. The potential state of the photodiode 21 at this time is defined as “second potential state”. The light irradiation changes the potential state of the photodiode 21 because carriers are generated by the photoelectric conversion function of the photodiode 21 and the generated carriers are accumulated in the photodiode 21.

The switching element 25 in the pixel 2 is constituted by a MOS transistor having a gate electrode connected to the row selection line 5. The source of the MOS transistor is connected to the source of the amplification transistor 23, and the drain is connected to the vertical signal line 6. When the potential of the illustrated row selection line 5 is selectively changed from logic “Low” to logic “High” by the vertical shift register 3, the switching element 25 becomes conductive, and as a result, the first power supply terminal ( V _dd ) 26 flows to the second power supply terminal (V _ss ) 28 via the amplification transistor 23, the switching element 25, the vertical signal line 6, and the load element 27. At this time, the potential of the vertical signal line 6 changes depending on the potential state of the photodiode 21 (the potential of the gate electrode 22 of the amplification transistor 23) and the threshold voltage (Vt) of the amplification transistor 23. As a result, the potential of the vertical signal line 6 has a level corresponding to the second potential state of the photodiode 21. However, as described above, if the threshold voltage of the amplification transistor 23 varies for each pixel, the level of the potential appearing on the corresponding vertical signal line 6 varies even if the second potential state is the same. Would.

The unit compensation circuit 18 includes a switching element S
A first storage element 35 and a second storage element 41 are connected to each other via W1. The first storage element 35 of the present embodiment is a MOS capacitor having a pair of electrodes (a first electrode 36 and a second electrode 34). The first electrode 36 of the first storage element 35 is formed of, for example, a polycrystalline silicon (polysilicon) film deposited on a silicon substrate via an insulating film. The first electrode 36 is electrically connected to the vertical signal line 6, and the signal potential φs corresponding to the second potential state of the photoelectric conversion unit via the vertical signal line 6.
Can receive. In the present embodiment, the second electrode 34 of the first storage element 35 is a silicon substrate, receives charge from the charge supply unit 31 via the switching element (n-channel MOS transistor) SW2, and turns on the switching element SW2. When in the state, the reference potential φ0 can be set. The charge supply unit 31 includes an n-type diffusion layer and functions as a source region of the switching element SW2. The signal potential φ is applied to the signal input section 30 of the unit compensation circuit 18.
When s is given, when the first storage element 35 receives supply of charge from the charge supply unit 31 via the switching element SW2, the first storage element 35 causes the potential difference between the signal potential and the reference potential (φs− (0) will be accumulated.

The second storage element 41 of this embodiment is also an MO having a pair of electrodes (a first electrode 42 and a second electrode 40).
This is an S-type capacitor. First electrode 4 of second storage element 41
2 is also formed of, for example, a polysilicon film deposited on a silicon substrate via an insulating film, and has a fixed potential φd
Receive. The second electrode 40 of the second storage element 41 is also a silicon substrate in the present embodiment. The second electrode 40 is electrically connected to the power supply Vo via the switching elements SW3 and SW4.
And 9 are electrically connected to a horizontal signal line 10.

The second electrode 40 of the second storage element 41 is electrically connected to the second electrode 34 of the first storage element 35 when the switching element SW1 is in a conductive state, and exchanges charges between the two electrodes. It can be carried out. First storage element 35
When the switching element SW1 is turned on while the second electrode 34 receives the reference potential φ0 from the charge supply unit 31, the second electrode 40 of the second storage element 41 also
1 can be supplied with electric charge. Note that the second storage element 41 accumulates charges proportional to the potential difference (φd−φ0) between the fixed potential φd and the reference potential φ0.

When the reset operation potential φr corresponding to the first potential state of the photoelectric conversion unit is output onto the vertical signal line 6 in response to the reset operation, the reset operation potential φr becomes the first potential.
It is provided to the first electrode 36 of the storage element 35. At this time,
The switching element SW1 short-circuits the second electrode 34 of the first storage element 35 and the second electrode 40 of the second storage element 41, thereby causing a potential difference (φs−φ) between the signal potential φs and the potential φr during the reset operation. (r) can be transferred from the second storage element 41 to the first storage element 35 in an amount proportional to (φr). After that, the switching element SW1 operates to electrically separate the second electrode 34 of the first storage element 35 from the second electrode 40 of the second storage element 41.

In FIG. 2, reference numeral 29 denotes a load element 27.
, 33 represents a gate electrode of the switching element SW2, 39 represents a gate electrode of the switching element SW1, and 45 represents a gate electrode of the switching element SW3. Reference numeral 46 denotes an n-type diffusion layer that forms an output section of the unit compensation circuit 18. An operational amplifier (operational amplifier) 43 constitutes the output amplifier 11 together with the integration capacitor and the reset transistor. Reference numeral 42 denotes a positive input portion of the operational amplifier 43, and reference numeral 44 denotes an operational amplifier 43.
Output terminal.

Next, the operation of the unit compensation circuit 18 will be described in more detail with reference to FIG. FIG. 3 shows a cross section of a region of the silicon substrate where the unit compensation circuit 18 is formed,
The surface potential profile of that portion is schematically shown. The silicon substrate is p-type, and the n-type diffusion layer 31 and the switching element S
The gate electrode 33 of W2 and the first electrode 3 of the first storage element 35
6, the gate electrode 39 of the switching element SW1, the first electrode 42 of the second storage element 41, the gate electrode 45 of the switching element SW3, and the n-type diffusion layer 46, respectively.
Potentials Vi, Vig, Vc1, Vcc, Vc2, Vog and Vo are applied. The hatching in the figure indicates the presence of charges (electrons).

First, at or before time t1, the potential Vcc is set to logic "high" and the switching element SW
By electrically conducting 1, the second electrode of the first storage element 35 having the capacitance C <b> 1 is electrically connected to the second electrode of the second storage element 41 having the capacitance C <b> 2, and charges can flow between the two. To do. At this time, by maintaining the potentials Vig and Vog at the logic “Low”, the switching elements SW2 and SW3 are kept in a non-conductive state.

At time t1, a signal potential Vc1 is applied to the first electrode 36 of the first storage element 35 via the vertical signal line 6, and as a result, the first electrode of the first storage element 35 on the silicon substrate surface The portion facing 36 indicates the potential φs. At this time, the first electrode 42 of the second storage element 41
Is applied with a fixed potential Vc2, and a portion of the surface of the silicon substrate facing the first electrode 42 of the second storage element 41 indicates the potential φd. On the other hand, the fixed potential Vi is given to the n-type diffusion layer 31 constituting the charge supply unit,
The surface potential of n-type diffusion layer 31 is maintained at reference potential φ0. Note that the fixed potential Vi is applied to the charge supply unit 31 over the entire period from time t1 to time t6 described below.
The fixed potential Vc2 is applied to the first electrode 42 of the storage element 41 by n
The fixed potential Vo is continuously applied to the mold diffusion layer 46 via the switching element SW4.

Time t1 corresponds to a certain time before the reset pulse is applied within the horizontal retrace period. The signal potential Vc1 applied to the input unit of the unit compensation circuit 18 at time t1 is a value (output value) obtained by reading out the second potential state of the photodiode 21 in the corresponding pixel 2 using the detection circuit. If the threshold voltage of the MOS transistor 23 functioning as a driving element differs for each pixel,
In addition, even when light of the same intensity irradiates a plurality of pixels, the signal potential Vc1 appearing on the corresponding vertical signal line 6
May vary, for example, by about ± 10%.

At time t2, the potential Vig is changed to the logic "hig".
By setting "h", the switching element SW2 is changed from the non-conductive state to the conductive state. At this time, switching element SW1 is held in a conductive state, and switching element SW3 is held in a non-conductive state. as a result,
Charge is supplied from the charge supply unit 31 to both the first storage element 35 and the second storage element 41.

Next, at time t3, potentials Vcc and Vcc
ig is set to logic “Low”, and the switching elements SW1 and SW2 are changed from the conductive state to the non-conductive state. At this time, the switching element SW3 remains in the non-conductive state. Thus, the first storage element 35 stores the charge having the charge amount Q1 proportional to the potential difference (φs−φ0) between the signal potential φs and the reference potential φ0, and the second storage element 41 stores the fixed potential φd and the reference potential φ0. The charge of the charge amount Q2 proportional to the potential difference (φd−φ0) is accumulated.

Q1 = C1 (φs−φ0) (Equation 1) holds between the charge Q1 and the potential difference (φs−φ0), and the relationship between the charge Q2 and the potential difference (φd−φ0) is obtained. Between them, Q2 = C2 (φd−φ0) Expression 2 holds.

Time t4 corresponds to a certain time during (or immediately after) the application of the reset pulse within the horizontal retrace period. At time t4, the signal potential Vc1 applied to the input unit of the unit compensation circuit 18 is a value obtained by reading out the first potential state of the photodiode 21 in the corresponding pixel 2 using the detection circuit. When the signal potential Vc1 is applied to the first electrode 36 of the first storage element 35 via the vertical signal line 6, the potential of the portion of the silicon substrate surface facing the first electrode 36 of the first storage element 35 becomes φs
To φr. If the threshold voltage of the amplifying transistor 23 is different for each pixel, the signal potential Vc1 appearing on the corresponding vertical signal line 6 may vary by about ± 10% even if the first potential state is forced to the same level. There is.

At time t4, the switching element S
W1 to SW3 are kept in the non-conductive state. For this reason, the first storage element 35 does not receive the supply of electric charge from anywhere, only the potential of the first electrode 36 changes, and the electric charge Q1 is maintained.

At time t5, the potential Vcc is changed to logic "High".
h ", only the switching element SW1 is changed from the non-conductive state to the conductive state. As a result, the second storage element 41
Is supplied to the first storage element 35, and the surface potential of the silicon substrate becomes φf.

Next, at time t6, the switching element S
W1 returns to the non-conductive state. As a result, the charge of the charge amount Q1 'is stored in the first storage element 35, and the charge of the charge amount Q2' is stored in the second storage element 41.

The relationship of Q1 ′ = C1 (φr−φf) Equation 3 holds between the charge Q1 ′ and the potential difference (φr−φf), and the charge Q2 ′ and the potential difference (φd−φf). )
Q2 ′ = C2 (φd−φf) (Equation 4)

Since the charge conservation equation Q1 + Q2 = Q1 '+ Q2' holds, from equations 1 to 4, C1 (φs−φ0) + C2 (φd−φ0) = C1 (φr−φf) + C2 (φd−φf) ··· Equation 5 is obtained. By transforming Expression 5, φf = (φr−φs) · C1 / (C1 + C2) + φ0 Expression 6 is obtained. When the charge amount Q2 ′ is obtained from Equations 4 and 6, Q2 ′ = Q2− (φr−φs) · C1 · C2 / (C1 + C2) Equation 7

The second term on the right-hand side of the equation 7 is the amount of charge flowing into the first storage element 35 from the second storage element 41 at time t5 (Δ
Q). As is apparent from Equation 7, the charge amount ΔQ is proportional to (φr−φs) corresponding to the difference between the potentials output on the vertical signal lines 6, and the fluctuation component due to the variation in the transistor characteristics is It is proportional to the offset value. Therefore, if the amount of charge Q2 'stored in the second storage element 41 is detected by the output amplifier 11 by changing the switching elements SW3, SW5 and 9 to the conductive state, the output amplifier 11 is proportional to (φr−φs). Output can be generated. At this time, it is clear from the element structure that the second storage element 41 after the charge is read can be easily depleted, which is advantageous in that thermal noise is not generated.

FIG. 4 shows a unit compensation circuit 18 belonging to a certain column.
Switching elements SW1 to SW3, first storage element 3
5 schematically illustrates a planar layout example of the first electrode 36 of No. 5 and the first electrode 42 of the second storage element 41. FIG. 4 shows a line 50 extending in the vertical direction and lines 51 to 56 extending in the horizontal direction. The line 50 corresponds to the vertical signal line 6. Lines 51-56 interconnect the corresponding portions of each column and supply substantially the same potential at the same timing to the corresponding portions of unit compensation circuits 18 belonging to all columns. In contrast, a different potential appears on the line 50 for each column. The lines 50 to 56 are made of, for example, aluminum (A
1) and is in contact with the diffusion layers 31 and 46 and the like. The wiring made of aluminum is shown by a solid line in the figure for simplicity. As shown in FIG. 4, the electrodes 36 and 42 of each storage element are formed from a first-layer polysilicon film, and the gate electrodes 33, 39 and 45 of each switching element are formed from a second-layer polysilicon film.
In addition, the gate electrode 33 of the switching element SW2 and the first storage element of the first storage element are so arranged that the charge transfer is performed smoothly.
Between the first electrode 36 of the first storage element and the gate electrode 39 of the switching element SW1; between the gate electrode 39 of the switching element SW1 and the first electrode 42 of the second storage element; A structure having an overlap at each boundary between the first electrode 42 of the storage element and the gate electrode 45 of the switching element SW3 is employed.

Next, a method of driving the device 1 will be described with reference to FIGS. Here, the case where the n-th row (n is any integer from 1 to N) of the pixel array is selected by the vertical shift register 3 will be described. The timings of the above-mentioned times t1 to t6 are shown at the bottom of FIG.

First, the n-th row selection pulse RSn shown in FIG. 5A is applied to the n-th row selection line 5. By the application of the selection pulse, the potential of the row selection line 5 of the n-th row becomes logic “Hig” during the horizontal retrace period (for example, about 10 μsec).
h ", and the period other than that period is logic" Low ". As a result, the switching elements 25 of all the pixels 2 connected to the row selection line 5 of the n-th row are turned on. Each of the selected pixels 2 is connected to the corresponding vertical signal line 6. At this time, each photodiode 21 has accumulated an amount of carriers corresponding to the amount of light received so far, and is in the second potential state. The application of the n-th row selection pulse is performed in order to detect the second potential state in the accumulation units in all the pixels 2 belonging to the n-th row. The application of the n-th row selection pulse is performed on the n-th row and the m-th column (m is 1, 2, 3,... M).
M source follower circuits composed of the driving element 23 and the m-th row of load elements 27 are operated almost simultaneously. As a result, the output of each of the m source follower circuits (functioning as a detection circuit) is output via the corresponding vertical signal line 6 to the first storage element 35 of the first storage element 35 which is the input unit of the corresponding unit compensation circuit 18. One electrode 36 is provided. In addition,
The gate electrode 29 of the load element 27 has a voltage Vl having a waveform 74 shown in FIG.
Is always applied, and the load element 27 functions as a load of the detection circuit. Note that a voltage indicating the waveform 73 instead of the waveform 74 may be applied.

FIG.
A potential having a waveform 72 shown in (b) is applied to the reset wiring 4, the carriers accumulated in the photodiode 21 are reset, and the potential state of the photodiode 21 returns to the first potential state. Waveform 72 shown in FIG.
Before the reset pulse is applied to the reset wiring 4, a series of opening and closing operations of the switching elements SW1 to SW3 are executed at the timing described with reference to FIG. Hereinafter, this point will be described.

First, for the charge supply section 31 functioning as the source region of the switching element SW2, FIG.
The potential Vi of the waveform 75 shown in FIG.
The surface potential of No. 1 is maintained at φ0.

The potential Vig of the waveform 76 shown in FIG.
Is applied to the gate electrode of the switching element SW2. This potential Vig becomes “High” at time t2.

The first electrode 36 of the first storage element 35 is supplied with a potential Vc1 having a waveform 77 that changes as shown in FIG. The potential Vc1 corresponds to the signal potential φs corresponding to the amount of light applied to the pixel until the reset pulse 72 is applied to the gate of the reset element 24, but when the reset pulse 72 is applied to the gate of the reset transistor. The state transits to the reset potential φr.

Gate electrode 39 of switching element SW1
Is supplied with a potential Vcc of a waveform 78 shown in FIG. The potential Vcc is initially at the level of the logic “High” and makes the switching element SW1 conductive. However, before time t3, the potential Vcc changes to the level of the logic “Low” and the switching element SW1 changes to the non-conductive state. Let it. Further, before the time t5, the potential Vcc becomes the logic “High”.
After that, the switching element SW1 is turned on and the switching element SW1 is turned on. Before the time t6, the switching element SW1 is turned on and the switching element SW1 is turned off.

A fixed potential Vc2 having a waveform 79 shown in FIG. 5 (h) is applied to the first electrode 42 of the second storage element 41, and the first electrode 42 continues to apply a constant electric field to the opposing surface region. .

Gate electrode 45 of switching element SW3
Is supplied with the potential Vog of the waveform 80 shown in FIG. The potential Vog is initially at the “Low” level and keeps the switching element SW3 in the non-conducting state. However, after a series of operations from time t1 to t6 is completed, the potential Vog changes to the logic “High” level. Switching element SW
3 is changed to a conductive state.

After the horizontal retrace period ends, during the horizontal effective period (for example, about 50 microseconds), while the switching element SW3 is conducting, all information of the pixels 2 in the n-th row is changed from the first column to the first column. Output is performed one by one in order up to M columns. FIG. 5 (j) shows a selection pulse (pulse width: for example, about 50 to 500) for turning on the switching element 9 in the m-th column.
FIG. 5 (k) shows the (m +
1) shows a selection pulse (CSm + 1) 83 for turning on the switching elements 9 in a column. These selection pulses are sequentially output from the horizontal shift register 7. When the switching element 9 in a certain m-th column conducts, the electric charge accumulated in the n-type diffusion layer 46 which is the output of the unit compensation circuit 18 in the m-th column flows into the negative input part of the operational amplifier 43. As a result, a voltage corresponding to the amount of current flowing at that time is output as a signal to the output terminal 44 so that the potential of the negative input portion of the operational amplifier 43 becomes equal to the potential of the positive input portion. Note that the output terminal 44 of the operational amplifier 43 is connected to the negative input unit via the integration capacitance and the reset transistor. The output amplifier 11 having such a configuration is often used as current-voltage conversion means. As described above, when information is held as electric charges, the compensation operation is performed in the state of electric charges, and the output amplifier 11 is operated using the electric charges, the information is held as a “potential” and transmitted to the final stage. It is possible to execute the output at a higher speed as compared with.

After the necessary information has been output from all the columns included in one row as described above, the same operation is performed for the other rows.

The output amplifier 11 does not have a configuration using the operational amplifier 43 as shown in FIG.
0 may be a source follower configuration connected to the input gate electrode.

As can be understood from the above description, the first and second storage elements 35 and 41 are large enough to maintain and store charges at a sufficient level for about one horizontal effective period (about 50 microseconds). It is preferable to have a capacity. In the case of the present embodiment, the capacitance of each of the storage elements 35 and 41 is 0.1.
1 to 0.5 pF (picofarad). As the storage elements 35 and 41, for example, capacitors using an oxide film as a capacitance insulating film can be used. If a thermal oxide film is adopted as the oxide film, the variation in capacitance becomes very small.

As shown in the equations (1) to (4), as long as the electric charge (Q) is proportional to the potential difference (φs−φ0, φd−φ0, etc.),
Variations in the threshold voltage are eliminated. Output charge Δ
Q indicates that the capacitance C1 of the first storage element 35 is
When the capacitance C2 is equal to the capacitance C2.

According to the present embodiment, the switching element S
W1 to SW5 do not operate in the weak inversion state at the time of charge transfer, and can stably transfer charges even when the amount of light is small. As a result, according to the present embodiment, even if the characteristics of the storage unit vary, the influence of the variation can be accurately compensated for regardless of the amount of received light, and the information can be read from the storage unit more accurately and at high speed.

Each switching element in the unit compensation circuit 18 is preferably M, like other switching elements.
It is formed from an OS transistor.

Further, t = t3, t4 in FIGS. 3 and 5
In this case, the switching element SW1 may maintain the conductive state. This is shown in FIGS. 6 and 7. According to FIGS. 6 and 7, since the number of signal transitions is reduced, a series of driving times can be reduced.

(Second Embodiment) Next, another embodiment of the amplification type solid-state imaging device according to the present invention will be described with reference to FIG. FIG. 8 schematically shows a cross section of a region of the silicon substrate where the unit compensation circuit is formed, and a surface potential profile of the portion, and corresponds to FIG. 3 relating to the first embodiment. The imaging apparatus according to the present embodiment has substantially the same configuration as that of the first embodiment except for the unit compensation circuit, and a description of corresponding parts will be omitted.

The unit compensation circuit according to the present embodiment executes both supply and extraction of charges using the n-type diffusion layer 46. Therefore, the device according to the present embodiment includes the charge supply unit 3
1 and the switching element SW2 are not provided. First
In the vicinity of the storage element 35, a p-type diffusion layer 47 having the same conductivity type as that of the silicon substrate is formed. This p-type diffusion layer 47 is grounded. Therefore, the potential of the p-type diffusion layer 47 is maintained at a constant value at any time as shown in FIG.

Hereinafter, a method of driving the imaging apparatus according to the present embodiment will be described. First, by turning on the switching element SW1 at or before time t11, the second electrode of the first storage element 35 having the capacitance C1 and the capacitance C1
2 is electrically connected to the second electrode of the second storage element 41 having a surface region of the silicon substrate through the surface region of the silicon substrate so that electric charges can flow between the two. At this time, the switching element SW3 is kept in a non-conductive state.

At time t11, the portion of the silicon substrate surface facing the first electrode of the first storage element 35 has the potential φs
And the portion of the silicon substrate surface facing the first electrode of the second storage element 41 indicates the potential φd. On the other hand, a fixed potential is applied to the n-type diffusion layer 46 constituting the charge supply unit in the present embodiment via the switching element SW4. As a result, the surface potential of the n-type diffusion layer 46 is maintained at the reference potential φ0. You.

At time t12, switching element SW3
Are changed from the non-conductive state to the conductive state. At this time, the switching element SW1 is kept conductive, and as a result, electric charge is supplied from the n-type diffusion layer 46 to both the first storage element 35 and the second storage element 41. In this regard, the present embodiment shows an operation that is significantly different from the first embodiment.

Next, at time t13, the switching element S
W1 is changed from the conductive state to the non-conductive state. At this time, the switching element SW3 is kept in the conductive state. Thus, the first storage element 35 has the signal potential φs
And an electric charge of a charge amount Q1 proportional to a potential difference (φs−φ0) between the reference potential φ0 and the reference potential φ0.

At time t14, switching element SW3
Is changed from the conductive state to the non-conductive state. Thus, the second storage element 41 stores the charge having the charge amount Q2 proportional to the potential difference (φd−φ0) between the fixed potential φd and the reference potential φ0.

At time t15, within the horizontal retrace period,
While the reset pulse is being applied (or immediately after)
Corresponds to a certain time. At time t15, the signal potential applied to the input unit of the unit compensation circuit is a value obtained by reading out the first potential state of the photodiode 21 in the corresponding pixel 2 using the detection circuit. First storage element 35
When a signal potential is applied to the first electrode of the first storage element 35 on the surface of the silicon substrate,
The potential of the portion facing the electrode increases from φs to φr.
At time t15, switching elements SW1 and SW3 are kept in a non-conductive state. Therefore, the first storage element 35 does not receive the supply of the electric charge from anywhere, only the electric potential of the first electrode changes, and the electric charge Q1 is held.

At time t16, switching element SW1
Only the state changes from the non-conductive state to the conductive state. as a result,
Part of the charge Q2 stored in the second storage element 41
Is supplied to the storage element 35 and the surface potential of the silicon substrate is φ
f.

Next, at time t17, switching element SW1 returns to the non-conductive state. As a result, the charge of the charge amount Q1 'is stored in the first storage element 35, and the charge of the charge amount Q2' is stored in the second storage element 41. For the charge amount Q2 ', the above equation 7 holds. For this reason, the first embodiment will be described by changing the switching elements SW3, SW5, and 9 to the conductive state and detecting the amount of charge Q2 'stored in the second storage element 41 with the output amplifier 11. As we did, (φ
r-φs).

According to the present embodiment, the n-type diffusion layer 31, the gate electrode 33 and the wiring thereof in the first embodiment are not required, and the effect that the configuration is simplified can be obtained.

The switching element SW1 may be maintained in the conductive state at t = t13 to t15 in FIG. This is shown in FIG. According to FIG. 9, since the number of signal transitions is reduced, a series of driving times can be reduced.

In each of the above embodiments, a shift register is used as a selection circuit for accessing the pixel 2.
A selection circuit having an access function such as a decoder may be used instead of the shift register. Also, an example in which a reset pulse is output from a vertical shift register that outputs a selection pulse for selecting a row has been described. However, a shift register and a decoder for outputting a reset pulse and a shift register and a decoder for selecting a row are provided in an imaging area. May be separately arranged on different sides.

In the above embodiment, the control electrode and the electrode of the storage element have a structure in which they overlap each other at the boundary. However, the structure generally requires a two-layer polysilicon structure. However, it is possible to operate even if a structure in which a small gap is provided between the electrodes instead of the above-described overlap is used, and in this case, it is possible to further form a polysilicon structure. The operation may be stabilized by forming an n-type diffusion layer in the gap.

In the above embodiment, the present invention has been described with respect to the device in which pixels are arranged in a matrix, but the arrangement of pixels is not limited to this. The pixels may be arranged in a single line, or may be arranged while wobbling in a staggered manner. In addition, they may be arranged not only in a plane but also on a curved surface.

If, instead of the photoelectric conversion element, a conversion element whose potential state changes according to another physical quantity is provided in each unit area, a device for detecting the spatial distribution of the physical quantity can be provided. For example, by providing a pressure detecting element or an X-ray detecting element in the information storage unit, a pressure distribution detecting device or an X-ray distribution detecting device is provided.

[0076]

According to the amplification type solid-state imaging device of the present invention,
Since the compensation circuit performs the compensation operation in the state of electric charge, even if the characteristics of the storage unit vary from pixel to pixel, the effect can be compensated and information can be read from the photoelectric conversion unit more accurately and quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an amplification type solid-state imaging device according to the present invention.

FIG. 2 is a circuit diagram showing a partial configuration in FIG. 1 in detail.

FIG. 3 is an explanatory diagram showing one operation example of the unit compensation circuit in FIG. 2;

FIG. 4 is a plan view illustrating a layout example of a unit compensation circuit in FIG. 2;

5 (a) to 5 (k) are timing charts corresponding to FIG. 3 and showing waveforms of signals in FIG.

FIG. 6 is an explanatory diagram showing a modification of FIG. 3;

FIGS. 7A to 7K are timing charts corresponding to FIG. 6 and showing signal waveforms in FIG.

FIG. 8 is an explanatory diagram showing another operation example of the unit compensation circuit in FIG. 2;

FIG. 9 is an explanatory diagram showing a modification of FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Amplification type solid-state imaging device 2 Pixel 3 Vertical shift register 4 Reset wiring 5 Row selection line 6 Vertical signal line 7 Horizontal shift register 8 Compensation circuit 9 Switching element 10 Horizontal signal line 11 Output amplifier 18 Unit compensation circuit 21 Photodiode 23 Amplification transistor 24 reset element 25 switching element 26 first power supply 27 load element 28 second power supply 35 first storage element 41 second storage element SW1 switching element

Claims (10)

[Claims] A photoelectric conversion unit that transitions from a first potential state according to a reset operation to a second potential state according to light intensity; and the first potential state and the second potential state of the photoelectric conversion unit. And an amplifying element for outputting a first signal and a second signal, respectively, and obtaining the first signal and the second signal from the amplifying element. And a compensating circuit that outputs a signal of (a), wherein the compensating circuit comprises: a first storage element including a MOS-type capacitor having a first electrode and a second electrode; A second storage element composed of another MOS capacitor having an electrode and a second electrode; means for applying a fixed potential to a first electrode of the second storage element; and a second storage element of the first storage element. An electrode and a second of the second storage element
A switching element for connecting and disconnecting between the electrodes, means for applying a signal potential corresponding to the second signal to a first electrode of the first storage element, and a second electrode of the first storage element. The second of the second storage element
Charge supply means for supplying a charge to the second electrode of the first storage element and the second electrode of the second storage element so as to give the same reference potential to the electrode; Means for applying a reset potential according to the signal of 1 to the first electrode of the first storage element, wherein the reset potential is applied to the first electrode of the first storage element, and the reset potential is applied to the first electrode of the second storage element. In the state where the fixed potential is applied, charges move between the second electrode of the first storage element and the second electrode of the second storage element, and the second electrode of the first storage element is moved. Means for conducting the switching element so that the potential of the second storage element becomes equal to the potential of the second electrode of the second storage element; and a state in which the switching element is rendered non-conductive after the movement of the charge has occurred. And stored in the second storage element. Amplifying solid-state imaging device characterized by comprising a means for outputting said third signal corresponding to the amount of the charge was. 2. The amplification-type solid-state imaging device according to claim 1, wherein the switching element is configured by a MOS transistor having a gate electrode, and the gate electrode of the switching element is connected to a first electrode of the first storage element. An amplifying solid-state imaging device, wherein each of the first electrodes of the second storage element partially overlaps each other. 3. The amplifying solid-state imaging device according to claim 2, wherein the gate electrode of the switching element, the first electrode of the first storage element, and the first electrode of the second storage element are each formed on a silicon substrate. An amplifying solid-state imaging device, which is formed of a polycrystalline silicon film deposited via an insulating film. 4. The amplifying solid-state imaging device according to claim 1, wherein the charge supply unit is configured to connect the second storage element through a second electrode of the first storage element when the switching element is in a conductive state. An amplification type solid-state imaging device comprising: means for supplying a charge to a second electrode. 5. The amplifying solid-state imaging device according to claim 1, wherein the charge supply unit controls the charge of the first storage element through a second electrode of the second storage element when the switching element is in a conductive state. An amplification type solid-state imaging device comprising: means for supplying a charge to a second electrode. 6. The amplifying solid-state imaging device according to claim 1, wherein the amplifying element is an amplifying transistor whose current driving force changes according to a potential state of the photoelectric conversion unit. An amplification type solid-state imaging device further comprising a load element for generating a corresponding potential signal as the first signal and the second signal. 7. A plurality of pixels arranged in N rows and M columns (N and M are integers of 1 or more and at least one of them is 2 or more)
A photoelectric conversion unit that transitions from a first potential state according to a reset operation to a second potential state according to light intensity, and the first pixel of the photoelectric conversion unit An amplification element for detecting a potential state and the second potential state and outputting a first signal and a second signal, respectively, for selecting a predetermined row among the plurality of pixels; A row selection unit, a column selection unit for selecting a predetermined column among the plurality of pixels, and obtaining the first signal and the second signal corresponding to each selected pixel column from the amplification element. An amplification type solid-state imaging device further comprising: M unit compensation circuits for outputting a third signal, wherein each of the unit compensation circuits is a MOS capacitor having a first electrode and a second electrode. A first storage element, and a first electrode and a second electrode A second storage element configured by another MOS type capacitor having: a means for applying a fixed potential to a first electrode of the second storage element; a second electrode of the first storage element; and the second storage element. Second
A switching element for connecting and disconnecting between the electrodes, means for applying a signal potential corresponding to the second signal to a first electrode of the first storage element, and a second electrode of the first storage element. The second of the second storage element
Charge supply means for supplying a charge to the second electrode of the first storage element and the second electrode of the second storage element so as to give the same reference potential to the electrode; Means for applying a reset potential according to the signal of 1 to the first electrode of the first storage element, wherein the reset potential is applied to the first electrode of the first storage element, and the reset potential is applied to the first electrode of the second storage element. In the state where the fixed potential is applied, charges move between the second electrode of the first storage element and the second electrode of the second storage element, and the second electrode of the first storage element is moved. Means for conducting the switching element so that the potential of the second storage element becomes equal to the potential of the second electrode of the second storage element; and a state in which the switching element is rendered non-conductive after the movement of the charge has occurred. And stored in the second storage element. Amplifying solid-state imaging device characterized by comprising a means for outputting said third signal corresponding to the amount of the charge was. 8. A photoelectric conversion unit that transitions from a first potential state according to a reset operation to a second potential state according to light intensity; and the first potential state and the second potential state of the photoelectric conversion unit. And an amplifying element for outputting a first signal and a second signal, respectively, and obtaining the first signal and the second signal from the amplifying element. And a compensating circuit for outputting a signal of the following type. The compensating circuit includes a MOS having a first electrode and a second electrode.
A first storage element composed of a first capacitor, a second storage element composed of another MOS-type capacitor having a first electrode and a second electrode, a second electrode of the first storage element and the second storage element. A method for driving an amplifying solid-state imaging device comprising: a switching element for connecting and disconnecting between a second electrode of a storage element and a step of applying a fixed potential to a first electrode of the second storage element; A step of obtaining the second potential state in the photoelectric conversion unit by the amplification element; and obtaining the second potential state and storing the signal potential corresponding to the second signal output from the amplification element in the first accumulation state. Applying to a first electrode of the device, a second electrode of the first storage device and a second electrode of the second storage device.
Supplying a charge to the second electrode of the first storage element and the second electrode of the second storage element so as to give the same reference potential to the electrode; and setting the first potential state in the photoelectric conversion unit to: A step of obtaining the amplifying element; a step of obtaining the first potential state and applying a reset potential according to the first signal output from the amplifying element to a first electrode of the first storage element; When the reset potential is applied to the first electrode of the first storage element and the fixed potential is applied to the first electrode of the second storage element, the second electrode of the first storage element and the second storage element are connected to each other. The switching element is turned on so that charge transfer occurs between the second electrode of the element and the potential of the second electrode of the first storage element becomes equal to the potential of the second electrode of the second storage element. Causing the charge to move Outputting the third signal in accordance with the amount of electric charge stored in the second storage element in a state where the switching element is turned off later. How to drive the device. 9. The driving method for an amplification type solid-state imaging device according to claim 8, further comprising a step of depleting the second storage element after outputting the third signal. A method for driving an amplification type solid-state imaging device. 10. A plurality of pixels (N) arranged in N rows and M columns.
And M is an integer of 1 or more, at least one of which is 2 or more). Each of the plurality of pixels transitions from a first potential state according to a reset operation to a second potential state according to light intensity. And an amplifying element for detecting the first potential state and the second potential state of the photoelectric conversion unit and outputting a first signal and a second signal, respectively. A row selection unit for selecting a predetermined row among the plurality of pixels; a column selection unit for selecting a predetermined column among the plurality of pixels; and a row selection unit corresponding to the selected pixel column. Further comprising: M unit compensation circuits for obtaining the first signal and the second signal from the amplifying element and outputting a third signal, wherein each of the unit compensation circuits includes a first electrode and a second electrode A first storage element composed of a MOS capacitor having
A second storage element composed of another MOS type capacitor having a first electrode and a second electrode; and a second storage element of the first storage element.
A method for driving an amplification type solid-state imaging device, comprising: a switching element for connecting and disconnecting an electrode and a second electrode of the second storage element, wherein a fixed potential is applied to a first electrode of each of the second storage elements. And a step of selecting a row from the plurality of pixels by the row selecting means; and determining the second potential state in the M photoelectric conversion units belonging to the selected row by the selected A step of obtaining M amplifying elements belonging to each row; and a step of obtaining the second potential state on the first electrode of each of the first storage elements and obtaining the second signal output from each of the amplifying elements. Applying a corresponding signal potential; and applying the first reference potential to the second electrode of each first storage element and the second reference electrode to the second electrode of each second storage element.
Supplying a charge to a second electrode of a storage element and a second electrode of each of the second storage elements; and selecting the first potential state in the M photoelectric conversion units belonging to the selected row by the selection. Obtaining each of the M amplifying elements belonging to the selected row; and obtaining the first potential state on the first electrode of each of the first storage elements and outputting the first potential from each of the amplifying elements. Applying a reset potential according to the signal of (a), the reset potential being applied to a first electrode of each of the first storage elements,
In a state in which the fixed potential is applied to the first electrode of each of the second storage elements, the electric charge is transferred between the second electrode of each of the first storage elements and the second electrode of each of the second storage elements. A movement occurs so that the potential of the second electrode of each of the first storage elements is equal to the potential of the second electrode of each of the second storage elements.
A step of conducting each of the switching elements; and, in a state in which each of the switching elements is turned off after the movement of the electric charge occurs, the second one according to an amount of electric charge stored in each of the second storage elements. 3. A method for driving an amplification type solid-state imaging device, comprising the steps of: