JP2000200948A - Wiring structure of parallel circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure of a parallel circuit, wherein currents of parallel connected elements are made equal without increasing the wiring inductance. SOLUTION: In a wiring structure of a parallel circuit having parallel connected elements, the elements are so disposed that a first, and third conductors 1, 2, 3 have negative mutual inductances, so that the voltage drops due to self/ mutual inductances at parallel branches are equal, thereby equalizing the currents flowing in elements 4 connected between the second and third conductors 2, 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a parallel circuit for connecting active elements or passive elements (hereinafter simply referred to as elements) in parallel.

[0002]

2. Description of the Related Art In general, when elements are connected in parallel, the current flowing through each element becomes non-uniform, so that the tolerance of the elements or the number of parallel elements requires redundancy. However, in such a configuration,
Since it is uneconomical, there is a method of suppressing current imbalance by disposing a magnetic core to conductors connected in parallel in order to equalize the current flowing through each element.

As one example, Japanese Patent Application Laid-Open No. Hei 9-117125 discloses
The method described in Unexamined Japanese Patent Publication No. H10-260, No. 1 is cited. in this way,
As shown in FIG. 1 of the above publication, semiconductor elements 4 are respectively connected to parallel circuit wirings 2a, 2b, 2c, 2d branched from bus 1, and currents flowing through each semiconductor element 4 join at bus 5. Outflow. At this time, the parallel circuit wiring 2
A magnetic body 3 is provided in a and 2d through which the parallel circuit wirings 2a and 2d respectively penetrate.

When the magnetic body 3 is not provided, the magnetic field generated by the alternating current flowing through the bus 1 and the parallel circuit wirings 2a, 2b, 2c, 2d is more inward than the outer parallel wirings 2a, 2d. Of the parallel circuit wirings 2b and 2c. As a result, a counter-electromotive force is generated in the inner parallel circuit wirings 2b and 2c due to the above-described effect, and a loop current flows due to this.
The loop currents due to the counter-electromotive force flowing to b and 2c are canceled because the directions are opposite to each other. On the other hand, in the outer parallel circuit wirings 2a and 2d, since the direction of the loop current due to the influence of the magnetic field due to the alternating current flowing through the other parallel circuit wirings is the same as the direction of the current flowing from the bus 1, the parallel circuit wirings A large amount of current flows through 2a and 2d, and current imbalance occurs.

On the other hand, in the configuration in which the magnetic body 3 is provided,
By selecting the magnetic material 3 to have an appropriate sectional area and perimeter, the self-inductance of the parallel circuit wirings 2a and 2d increases,
The inductance components of the parallel circuit wirings 2a, 2d increase, the impedance of the parallel circuit wirings 2a, 2d increases, the increase of the alternating current in the parallel circuit wirings 2a, 2d is suppressed, and the current imbalance of each parallel circuit wiring is prevented. be able to.

[0006]

As described above, by arranging a magnetic core on conductors connected in parallel,
Although current imbalance can be suppressed, when a large current flows, there is a problem that saturation is likely to occur, and an increase in wiring inductance due to the magnetic core also increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a wiring structure of a parallel circuit in which the currents of the respective elements connected in parallel are equal without increasing the wiring inductance.

[0008]

To achieve the above object, a wiring structure for a parallel circuit according to claim 1 of the present invention comprises:
By arranging the first conductor, the second conductor, and the third conductor so as to have a negative mutual inductance and to equalize the voltage drop due to the self / mutual inductance of the parallel branch portion, the second conductor and the third conductor are arranged. The current flowing through each element connected between the three conductors can be equalized.

In the wiring structure for a parallel circuit according to a second aspect of the present invention, the first conductor and the second conductor are connected on the side opposite to the power supply side and the power reception side, so that the first conductor and the second conductor are connected to each other. The second conductor and the third conductor can have a negative mutual inductance.

[0010] In the wiring structure of the parallel circuit according to claim 3 of the present invention, the conductor width of the second conductor and the third conductor is made different in each parallel branch portion, so that the self / mutual inductance and resistance are used. The voltage drops can be adjusted to be equal.

In the wiring structure for a parallel circuit according to a fourth aspect of the present invention, the conductor spacing between the first conductor, the second conductor, and the third conductor is made different in each parallel branch portion, so that the self / The voltage drop due to mutual inductance and resistance can be adjusted to be equal.

In the wiring structure for a parallel circuit according to a fifth aspect of the present invention, the conductor path lengths of the second conductor and the third conductor are made different at each parallel branch portion, thereby providing self / mutual inductance and resistance. Can be adjusted to be equal.

In the wiring structure for a parallel circuit according to claim 6 of the present invention, the thickness of the second conductor and the thickness of the third conductor are made different in each parallel branch portion, so that the voltage drop due to the resistance becomes equal. Can be adjusted as follows.

In the wiring structure of the parallel circuit according to the present invention, a magnetic material is provided in a conductor gap between the first conductor, the second conductor, and the third conductor, so that a voltage due to self / mutual inductance is provided. The descent can be adjusted to be equal.

In the wiring structure for a parallel circuit according to claim 8 of the present invention, by providing an insulator in a conductor gap between the first conductor, the second conductor and the third conductor, a negative mutual inductance is increased. As a result, the inductance from the power supply side to the power receiving side can be reduced.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic perspective view of a first embodiment of the present invention, and FIG. 2 is a schematic circuit diagram thereof.

FIGS. 1 and 2 show, for example, a semiconductor chip such as an IGBT and a diode, a semiconductor module such as an IGBT module and a diode module, and two elements such as a capacitor and a resistor connected in parallel. And the second and third conductors 2 and 3 of the parallel branch portion
Are arranged so that they have a negative mutual inductance and equalize the voltage drop due to the self / mutual inductance of the parallel branch part.

A power supply terminal 6 is provided at one end of the first conductor 1, a connection conductor 5 is connected to the other end of the first conductor 1, and a connection with the second conductor 2 is made. I have. The second conductor 2 is arranged in parallel with the first conductor 1 and is connected via an element 4 to a third conductor 3 arranged on the opposite side of the first conductor 1. The third conductor 3 is arranged in parallel with the first conductor 1, and a power receiving terminal 7 is provided on the same side of the first conductor 1 as the power supply terminal 6.

In this configuration, the current flows through the power supply terminal 6, the first conductor 1, the connection conductor 5, the second conductor 2, the element 4, the third
Flows through the conductor 3 and the power receiving terminal 7. At this time, the current flowing through the first conductor 1 is I1, the inductance is L1, the resistance is R1, the current flowing through the second conductor 2 is I2, the inductance is L2, the resistance is R2, and the third conductor 3 is
, The inductance is L3, the resistance is R3, and the mutual inductances M12 (<0), M1
3 (<0) and M23 (> 0), the arrangement of the first conductor, the second conductor 2, and the third conductor 3 is determined so as to satisfy the following expression.

[0020]

(Equation 1)

That is, when there is a large change in current, the current flowing through each element 4 can be equalized by equalizing the voltage drop due to the self / mutual inductance of the parallel branch portion.

When there is no current change, the current flowing through each element 4 can be equalized by equalizing the voltage drop due to the self-resistance of the parallel branch portion. At this time, the eleventh conductor 1, the second conductor 2, and the third conductor 3 can have a negative mutual inductance by setting the connection conductor 5 on the opposite side of the power supply terminal 6 and the power reception terminal 7.

FIG. 3 is a schematic perspective view of a second embodiment of the present invention, and FIG. 4 is a schematic circuit diagram thereof. FIG.
FIG. 4 shows a configuration in which a semiconductor chip such as an IGBT or a diode, a semiconductor module such as an IGBT module or a diode module, or three elements such as a capacitor or a resistor are connected in parallel. The second and third conductors 2 and 3 of the branch portion are arranged so as to have a negative mutual inductance and to equalize the voltage drop due to the self / mutual inductance of the parallel branch portion.

A power supply terminal 6 is provided at one end of the first conductor 1, a connection conductor 5 is connected to the other end of the first conductor 1, and a connection with the second conductor 2 is made. I have. The second conductor 2 is arranged in parallel with the first conductor 1 and is connected via an element 4 to a third conductor 3 arranged on the opposite side of the first conductor 1. The third conductor 3 is arranged in parallel with the first conductor 1, and a power receiving terminal 7 is provided on the same side of the first conductor 1 as the power supply terminal 6.

In this configuration, the current flows through the power supply terminal 6, the first conductor 1, the connection conductor 5, the second conductor 2, the element 4, the third
Flows through the conductor 3 and the power receiving terminal 7. At this time, currents flowing through the first conductor 1 are I1a and I1b, inductances thereof are L1a and L1b, resistances are R1a and R1b, currents flowing through the second conductor 2 are I2a and I2b, and inductances thereof are L2a and L2b. The resistances are R2a and R2b, the current flowing through the third conductor 3 is I3a and I3b, the inductance is L3a and L3b, the resistance is R3a and R3b, and the mutual inductances M12a and M12b (<0).
M13a, M13b (<0), M23a, M23b (>)
0), the first conductor and the second conductor
Of the second conductor 3 and the third conductor 3 are determined.

[0026]

(Equation 2)

That is, when there is a large current change, the current flowing through each element 4 can be made uniform by equalizing the voltage drop due to the self / mutual inductance of the parallel branch portion.

When there is no change in current, the current flowing through each element 4 can be equalized by equalizing the voltage drop due to the self-resistance of the parallel branch portion. At this time, the eleventh conductor 1, the second conductor 2, and the third conductor 3 can have a negative mutual inductance by setting the connection conductor 5 on the opposite side of the power supply terminal 6 and the power reception terminal 7.

The same applies to a case where three or more elements are connected in parallel. FIG. 5 is a schematic perspective view of the third embodiment of the present invention. Here, only points different from FIG. 3 will be described.

In the present embodiment, by making the conductor widths of the second conductor 3 and the third conductor 3 different at each parallel branch portion, the voltage drop due to self / mutual inductance and the voltage drop due to resistance are equalized. It has been adjusted to be.

At this time, the conductor width and the conductor interval (conductor gap)
Is greater than about 2: 1, the voltage drop due to self / mutual inductance and resistance can be approximately equal by making the conductor width of each parallel branch proportional to the current flowing therethrough. . In addition, about 20: 1
Above, it can be made almost completely proportional. For example, in the case of three parallels, 2: 1, and in the case of five parallels,
4: 3: 2: 1.

This is because the self-inductance of a single conductor does not become っ て も even if the conductor width is doubled, but the ratio of the conductor width to the conductor interval (conductor gap) is about 2 in a round-trip line conductor. : 1 or more, the fact that the conductor width and the self / mutual inductance have a substantially inversely proportional relationship is used. In other words, if the conductor width is doubled, both the resistance and the self / mutual inductance will be almost halved.

FIG. 6 shows the calculation results of two types of conventional wiring structures and the wiring structure of the present invention, each showing the value of current flowing through three parallel elements. As is clear from the results, in the configuration in which the power supply terminal and the power receiving terminal are in the same direction as in (a), a large current flows through the element where the power supply terminal and the power receiving terminal are located, and the opposite side of the power supply terminal and the power receiving terminal. A small amount of current flows through the element. In the configuration in which the power supply terminal and the power receiving terminal are in different directions as in (b), a large amount of current flows through an element near the power supply terminal and an element near the power receiving terminal. In the configuration of the present invention (c), almost ideal current balance is achieved.

FIG. 7 is a schematic perspective view of a fourth embodiment of the present invention. Here, only points different from FIG. 3 will be described. In the present embodiment, the first conductor 1, the second conductor 2, and the third conductor 3 have different conductor spacings at the respective parallel branch portions, so that the voltage drop due to self / mutual inductance and the voltage due to resistance are caused. The descent is adjusted to be equal.

Although the conductor shapes of the second conductor 3 and the third conductor 3 are changed here, the same effect can be obtained by changing the conductor shape of the first conductor 1. FIG. 8 is a schematic perspective view of a fifth embodiment of the present invention. Here, only points different from FIG. 3 will be described.

In the present embodiment, the length of the conductor path of the second conductor 2 and the third conductor 3 is made different in each parallel branch portion by meandering the conductor path, so that the voltage due to self / mutual inductance is obtained. The voltage drop due to the drop and the resistance is adjusted to be equal.

FIG. 9 is a schematic perspective view of a sixth embodiment of the present invention. Here, only differences from FIG. 3 will be described. In the present embodiment, the conductor thicknesses of the second conductor 3 and the third conductor 3 are made different in each parallel branch portion, so that the voltage drop due to the resistance is adjusted to be equal.

FIG. 10 is a schematic perspective view of a seventh embodiment of the present invention. Here, only points different from FIG. 3 will be described. In the present embodiment, the differently shaped magnetic material 8 is provided in the conductor gap between the first conductor 1, the second conductor 2, and the third conductor 3.
, The voltage drop due to self / mutual inductance is adjusted to be equal.

FIG. 11 is a schematic perspective view of an eighth embodiment of the present invention. Here, only points different from FIG. 3 will be described. In the present embodiment, the presence of the insulator 9 in the conductor gap between the first conductor 1 and the third conductor 3 increases the negative mutual inductance, and reduces the inductance from the power supply terminal 6 to the power reception terminal 7. Has been reduced.

FIG. 12 is a schematic perspective view of a ninth embodiment of the present invention. FIG. 12 shows a power converter in which three semiconductor elements 10 are connected in parallel, wherein the first conductor 1 and the second and second conductors 2 and 3 of the parallel branch portion have a negative mutual inductance, and This is a power converter configured and arranged so that voltage drops due to self / mutual inductance of parallel branch portions are equalized.

As described above, what is important is to have a negative mutual inductance, equalize the self / mutual inductance of the parallel branch portion, and equalize the voltage drop due to the resistance. Although desirable, the positional relationship between the conductors is relatively free.

FIG. 13 is a configuration diagram of a tenth embodiment of the present invention, and FIG. 14 is a configuration diagram of a conductor used therein. FIG. 13 shows a power converter in which three semiconductor elements 10 are connected in parallel, wherein the first conductor 1 and the second and third conductors 2 and 3 of the parallel branch portion have negative mutual inductance, and This is a power converter configured and arranged so that voltage drops due to self / mutual inductance of parallel branch portions are equalized.

As described above, what is important is to have a negative mutual inductance, to equalize the self / mutual inductance of the parallel branch portion, and to make the voltage drop due to the resistance equal. Although desirable, the positional relationship between the conductors is relatively free.

FIG. 15 is a configuration diagram of an eleventh embodiment of the present invention, and FIG. 16 is a configuration diagram of a conductor used therein. FIG. 15 shows that, in a capacitor bank in which 3 × 4 capacitors 11 are connected in parallel, the first conductor 1 and the second and third conductors 2 and 3 of the parallel branch portion have a negative mutual inductance, and This is a capacitor bank configured so that the voltage drops due to the self / mutual inductance of the parallel branch portions are equalized.

Although the present embodiment is applied to four vertical capacitors, it is also applicable to three horizontal rows to equalize the voltage drop due to self / mutual inductance in the parallel branch portion of 12 capacitors. it can.

[0046]

As described above in detail, according to the wiring structure of the parallel circuit of the present invention, the currents of the respective elements connected in parallel can be made uniform without increasing the wiring inductance. This can contribute to reduction in size and cost of the device.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a first embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of the first embodiment of the present invention.

FIG. 3 is a schematic perspective view of a second embodiment of the present invention.

FIG. 4 is a schematic circuit diagram of a second embodiment of the present invention.

FIG. 5 is a schematic perspective view of a third embodiment of the present invention.

FIG. 6 shows a calculation result of a current value flowing through an element having a conventional wiring structure and an element having a wiring structure according to the present invention.

FIG. 7 is a schematic perspective view of a fourth embodiment of the present invention.

FIG. 8 is a schematic perspective view of a fifth embodiment of the present invention.

FIG. 9 is a schematic perspective view of a sixth embodiment of the present invention.

FIG. 10 is a schematic perspective view of a seventh embodiment of the present invention.

FIG. 11 is a schematic perspective view of an eighth embodiment of the present invention.

FIG. 12 is a schematic perspective view of a ninth embodiment of the present invention.

FIG. 13 is a configuration diagram according to a tenth embodiment of the present invention.

FIG. 14 is a configuration diagram of a conductor used in the tenth embodiment.

FIG. 15 is a configuration diagram according to an eleventh embodiment of the present invention.

FIG. 16 is a configuration diagram of a conductor used in the eleventh embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st conductor 2 ... 2nd conductor 3 ... 3rd conductor 4 ... Element 5 ... Connection conductor 6 ... Feeding terminal 7 ... Power receiving terminal 8 ...・ Magnetic material 9 ・ ・ ・ Insulator 10 ・ ・ ・ Semiconductor element 11 ・ ・ ・ Capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E338 AA03 BB75 CC04 CC05 CC06 CD02 CD08 CD13 CD14 CD22 EE13 5H740 BA11 BB02 MM18 PP03 PP04

Claims (8)

[Claims] In a wiring structure of a parallel circuit in which elements are connected in parallel, a first conductor connected to a power supply side, a second conductor of a parallel branch portion, and a second conductor connected to a power receiving side at the parallel branch portion. 3 conductors, and the first conductor, the second conductor, and the third conductor are arranged so as to have a negative mutual inductance and to equalize the voltage drop due to the self / mutual inductance of the parallel branch portion. The wiring structure of a parallel circuit characterized by the above. 2. The power supply system according to claim 1, wherein the first conductor and the second conductor are connected on a power supply side and a power reception side.
The wiring structure of the described parallel circuit. 3. The wiring structure of a parallel circuit according to claim 1, wherein the conductor widths of the second conductor and the third conductor are different at each parallel branch portion. 4. The wiring structure of a parallel circuit according to claim 1, wherein the conductor spacing between the first conductor, the second conductor, and the third conductor is different at each parallel branch portion. 5. The wiring structure of a parallel circuit according to claim 1, wherein the conductor path lengths of the second conductor and the third conductor are different at each parallel branch portion. 6. The wiring structure of a parallel circuit according to claim 1, wherein the conductor thicknesses of the second conductor and the third conductor are different at each parallel branch portion. 7. The semiconductor device according to claim 1, wherein a magnetic material is provided in a conductor gap between the first conductor, the second conductor, and the third conductor.
The wiring structure of the described parallel circuit. 8. An insulator is provided in a conductor gap between the first conductor, the second conductor, and the third conductor.
The wiring structure of the described parallel circuit.