JP2000200874A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [PROBLEMS] To reduce the test cost of a large-scale integrated circuit device LSI or the like incorporating a random access memory RAM and a self-diagnosis circuit BIST. For example, in a large-scale integrated circuit device LSI including a random access memory RAM and a self-diagnosis circuit BIST, a self-diagnosis circuit BIST includes a test pattern generation circuit and a test data comparison circuit for a logic test of the random access memory RAM. In addition to the circuit, at the time of a power supply margin test or a data retention test, an internal voltage for selectively switching the potential of an internal voltage VMD supplied as an operation power supply of a memory cell constituting a memory array of a random access memory RAM according to a potential control signal VC. A switching circuit VMDS is provided to provide a function capable of performing a power supply margin test and a data retention test autonomously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a large-scale bipolar CMOS (complementary MOS) type which comprises a semiconductor memory such as a random access memory and a self-diagnosis circuit and constitutes a large computer system. The present invention relates to an integrated circuit device and a technique which is particularly effective for reducing the test cost.

[0002]

2. Description of the Related Art P-channel and N-channel MOSFs
A memory array in which CMOS memory cells formed of ET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is referred to as an insulated gate field effect transistor) is arranged in a lattice, and a bipolar transistor (hereinafter, referred to as a bipolar transistor). (In this specification, a bipolar transistor is abbreviated as a transistor.) A bipolar CMOS type random access including a bipolar circuit having a basic element and a peripheral circuit having a bipolar CMOS circuit formed by combining a CMOS circuit with a bipolar element having a basic element. There is memory. In addition, there is a large-scale integrated circuit device of a bipolar CMOS type which incorporates such a random access memory and constitutes, for example, a large-sized computer system.

On the other hand, a self-diagnosis (BIST: Build) for autonomously performing a logic test of a random access memory including a test pattern generation circuit and a test data comparison circuit in a large-scale integrated circuit device incorporating a random access memory or the like.
t In Self Test) circuit,
A method for reducing the test cost is known.

[0004]

Prior to the present invention, the present inventors engaged in the development of a large-scale integrated circuit device having a random access memory and a self-diagnosis circuit as described above. Noticed. That is, in this large-scale integrated circuit device, a logic test of a random access memory is autonomously performed by a built-in self-diagnosis circuit,
Although it is possible to reduce the test cost, in a random access memory or the like, as is well known, a power supply margin test for confirming an operation margin for a power supply fluctuation within an allowable range of a memory cell constituting a memory array, A data retention test or the like for confirming information retention characteristics under power supply fluctuation is required.

In the large-scale integrated circuit device, the self-diagnosis circuit does not have a function of performing a power margin test and a data retention test, and these tests are mainly performed by a probe tester or the like externally connected in a test process. I have no choice. Therefore, it is necessary for the probe tester to have a function for accurately changing the power supply voltage potential within an allowable range, which raises the price and requires several seconds for each test. In particular, an enormous test time is required in a mass production stage, and the test cost of a large-scale integrated circuit device increases.

An object of the present invention is to provide a self-diagnosis circuit having a new function. It is another object of the present invention to reduce the cost of testing a large-scale integrated circuit device or the like incorporating a random access memory and a self-diagnosis circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, for example, in a large-scale integrated circuit device incorporating a random access memory and a self-diagnosis circuit, the self-diagnosis circuit includes a power supply in addition to a test pattern generation circuit and a test data comparison circuit for a logic test such as a random access memory. At the time of a margin test or a data retention test, an internal voltage switching circuit for selectively switching the potential of an internal voltage supplied as an operating power supply of a memory cell forming a memory array in accordance with a potential control signal is provided, and a power supply margin test and a data retention test are performed. Provide functions that can be implemented autonomously.

According to the above-mentioned means, the power supply margin test and the data retention test can be performed autonomously and efficiently by the built-in self-diagnosis circuit.
As a result, the test cost of a large-scale integrated circuit device or the like can be reduced.

[0010]

FIG. 1 is a block diagram showing one embodiment of a large-scale integrated circuit device LSI (semiconductor integrated circuit device) to which the present invention is applied. First, an outline of the configuration and operation of the large-scale integrated circuit device LSI of this embodiment will be described with reference to FIG. The large-scale integrated circuit device LSI of this embodiment constitutes a predetermined large-scale computer system together with other various large-scale integrated circuit devices, although not particularly limited. The circuit elements constituting each block in FIG. 1 are formed on one semiconductor substrate CHIP surface such as single crystal silicon by a known bipolar CMOS integrated circuit manufacturing technique. Further, FIG. 1 shows a block configuration of a large-scale integrated circuit device LSI in the form of a board layout diagram. Also, in the following description of the substrate arrangement, the semiconductor substrate CH
Represents up, down, left, and right on the IP surface.

Referring to FIG. 1, a large-scale integrated circuit device LSI of this embodiment is not particularly limited, but includes a semiconductor substrate CH.
It includes a random access memory RAM (semiconductor memory) arranged to occupy most of the IP plane, and a self-diagnosis circuit BIST and an internal voltage generation circuit VG arranged on the left side of the random access memory RAM. The power supply voltage EVEE and the ground potential EGND are supplied to the internal voltage generation circuit VG from an external power supply device (not shown). The self-diagnosis circuit BIST includes a chip enable signal ECEB (here, a so-called inverted signal which is selectively set to a low level when the signal is enabled) from an external access device or a probe tester. , Its name is appended with B. The same applies hereinafter), a write enable signal EWEB and an output enable signal EOEB are supplied, and i + 1-bit X address signals EAX0 to EAXi and j + 1-bit Y address signal EAY0 are provided. ~ EAYj are supplied,
Further, storage data in units of 8 bits is input or output as input / output data EIO0 to EIO7.

The internal voltage generating circuit VG includes a power supply voltage EVEE supplied from an external power supply and a ground potential EGND.
Diagnostic circuit BIST and random access memory RAM as power supply voltage VEE and ground potential GND as they are.
And generates predetermined internal voltages VMD, VMS and VEE based on these power supply voltage and ground potential, and supplies them to the random access memory RAM.

Although not particularly limited, the power supply voltage EVEE
Is set to a negative potential such as -3.85 V (volt), and the ground potentials EGND and GND are set to 0V. The internal voltages VMD and VMS are, for example, −
Negative potentials such as 0.75 V and -2.7 V are used as their central potentials, and they are mainly used as high-potential-side and low-potential-side operation power supplies of CMOS memory cells constituting a memory array of a random access memory RAM. Further, the internal voltage V
The EE mainly serves as a low-potential-side operation power supply of the bipolar circuit with a negative potential such as -4.2 V as its central potential.

Next, when the large-scale integrated circuit device LSI is set in a normal operation mode, the self-diagnosis circuit BIST is provided with a chip enable signal ECEB, a write enable signal EWEB, and an output enable signal EOEB supplied from an external access device. , X address signals EAX0 to EAX
i, Y address signals EAY0-EAYj and input data EIO0-EIO7 are supplied to a chip enable signal CE.
B, the write enable signal WEB, the output enable signal OEB, the X address signals AX0 to AXi, the Y address signals AY0 to AYj and the input data IO0 to IO7 as they are transmitted to the random access memory RAM as they are, and the output read from the random access memory RAM. The data IO0 to IO7 are output data EIO0
The data is directly output to an external access device as .about.EIO7.

When the large-scale integrated circuit device LSI is set to the power margin test or the data retention test mode, a test chip enable signal, a write enable signal,
An output enable signal, an X address signal, a Y address signal and test data are generated and supplied to the random access memory RAM, and the output data IO0 to IO7 read from the random access memory RAM are
The data is fetched as read data RD0 to RD7 and compared with an expected value, that is, test data, to confirm its normality.

In this embodiment, a self-diagnosis circuit BIS
T includes a test control circuit, a test pattern generation circuit, and a test data comparison circuit, and has a function of autonomously performing a logic test of the random access memory RAM, as described later. In addition, the test control circuit of the self-diagnosis circuit BIST provides a potential control signal V for the internal voltage generation circuit VG.
The internal voltage generation circuit VG has a function of selectively generating C1 to VC3, and sets the potential of the internal voltage VMD for the random access memory RAM to the potential control signals VC1 to VC3.
And an internal voltage switching circuit for selectively switching according to the following.

On the other hand, the random access memory RAM is
A memory array in which CMOS memory cells are arranged in a lattice is used as a basic component thereof, and a chip enable signal CEB is provided.
, And selectively performs a write or read operation of storage data according to the write enable signal WEB and the output enable signal OEB.

In this embodiment, a CMOS memory cell forming a memory array of a random access memory RAM is provided with an internal voltage V supplied from an internal voltage generation circuit VG.
MD is the high-potential-side operation power supply. As described above, the potential of the internal voltage VMD is selectively switched according to the potential control signals VC1 to VC3 output from the self-diagnosis circuit BIST. As a result, in this embodiment, the function test regarding the potential fluctuation of the internal voltage VMD of the large-scale integrated circuit device LSI, that is, the power supply margin test and the data retention test are autonomously performed by using the logic test function of the self-diagnosis circuit BIST. It can be implemented efficiently and efficiently.

The specific configuration of the random access memory RAM, the self-diagnosis circuit BIST and the internal voltage generation circuit VG, and the specific contents of the power supply margin test and the data retention test will be described later in detail.

FIG. 2 shows the large-scale integrated circuit device LS of FIG.
A block diagram of one embodiment of a random access memory RAM included in I is shown. FIG. 3 is a partial circuit diagram of one embodiment of the memory array MARY included in the random access memory RAM of FIG.
Based on both figures, the large-scale integrated circuit device LSI of this embodiment
Of the random access memory RAM and the memory array MARY included in the RAM will be described. In FIG. 3, the MOSFET with an arrow at its channel (back gate) portion is a P-channel type, and an N-channel MOSFET without an arrow is attached.
Are shown separately from

In FIG. 2, a random access memory R
The AM has a memory array MARY arranged so as to occupy most of the required layout area as a basic component.

Here, the memory array MARY is not particularly limited, but as shown in FIG. 3, (m + 1) word lines W0 to Wm arranged in parallel in the horizontal direction of the drawing.
And n + 1 sets of complementary bit lines B0 * to Bn * (here, for example, the non-inverted bit lines B
0T and the inverted bit line B0B are indicated by asterisks like a complementary bit line B0 *. Further, a so-called non-inverted signal or the like which is selectively set to a high level when it is made valid is indicated by adding a T to the end of its name. The same applies hereinafter). At the intersections of these word lines and complementary bit lines, (m + 1) × (n + 1) CMOS memory cells MC are arranged in a lattice.

CMOS constituting memory array MARY
Each of the memory cells MC includes a P-channel MOSFET P1, an N-channel MOSFET N1, and a P-channel MOSFET
A pair of CMOS inverters including ETP2 and N-channel MOSFET N2 includes a cross-coupled latch. M + arranged in the same column of the memory array MARY
The non-inverting and inverting input / output nodes of the latch of one memory cell MC are a pair of N-channel selection MOSFETs N.
3 and corresponding complementary bit lines B0 * to Bn via N4
* Are commonly coupled to the non-inverted or inverted signal lines, respectively.
Also, n + arranged on the same row of the memory array MARY
Selection MOSFETs N3 and N4 of one memory cell MC
Are commonly coupled to corresponding word lines W0 to Wm, respectively.

In this embodiment, the memory array MAR
Each of the CMOS memory cells MC configuring Y uses the internal voltage VMD supplied from the internal voltage generation circuit VG as its high-potential-side operation power supply, and uses the internal voltage VMS as its low-potential-side operation power supply. As described above, the potential of the internal voltage VMD serving as the high-potential-side operation power supply of these CMOS memory cells MC is selectively switched according to the potential control signals VC1 to VC3 output from the self-diagnosis circuit BIST. As a result, the power margin test and the data retention test of the large-scale integrated circuit device LSI can be performed autonomously. This will be described later in detail.

Returning to FIG. The word lines W0 to Wm forming the memory array MARY are coupled to the X address decoder XD on the left side, and are alternatively set to a predetermined selection level. The X address decoder XD is supplied with i + 1-bit internal X address signals X0 to Xi from an X address buffer XB, and an unillustrated internal control signal XG from a timing generation circuit TG. Also, X
The address buffer XB includes the self-diagnosis circuit BIST.
, X address signals AX0 to AXi are supplied via an internal control signal CE, and an internal control signal CE is supplied from a timing generation circuit TG.

The X address buffers XB are provided with X address signals AX0 to AX supplied through a self-diagnosis circuit BIST.
Xi is fetched and held in accordance with the internal control signal CE, and based on these X address signals, internal X address signals X0 to Xi are formed to generate an X address decoder X.
D. X address decoder XD selectively operates according to internal control signal XG, and receives internal X address signals X0-X supplied from X address buffer XB.
i, and the corresponding word lines W0 to Wm of the memory array MARY are alternatively set to a predetermined selection level.

Next, the complementary bit lines B0 * to Bn * of the memory array MARY are connected to a Y switch circuit YS below the complementary bit lines B0 * to Bn *. * To CD7 *.

Here, the Y switch circuit YS is not particularly limited, but as shown in FIG.
N + 1 sets of P-channel switch MOSFETs provided corresponding to the complementary bit lines B0 * to Bn * of ARY
P3 and P4 are included. These switch MOSFETP
The upper terminals of P3 and P4 are coupled to the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory array MARY. ~ Covalently linked to CD7 *.
The gates of the switch MOSFETs P3 and P4 are
Eight sets are sequentially coupled in common, and corresponding bit line selection signals YS0 to YSp are supplied from the Y address decoder YD. It goes without saying that the bit number p + 1 of the bit line selection signals YS0 to YSp has a relationship of p + 1 = (n + 1) / 8 with respect to the set number n + 1 of the complementary bit lines B0 * to Bn *.

As a result, the switch MOSFETs P3 and P4 are selectively turned on eight sets at a time in response to the high level of the corresponding bit of the bit line select signals YS0 to YSp, and the complementary bit lines B0 * to B0 of the memory array MARY are turned on.
Bn * and the corresponding common data lines CD0 * to CDC
D7 * is selectively connected.

Returning to FIG. Complementary common data line CD0 *
CD7 * are coupled to the output terminals of the corresponding unit circuits of the write amplifier WA, and are also coupled to the input terminals of the corresponding unit circuits of the sense amplifier SA. The input terminal of each unit circuit of the write amplifier WA is connected to the data input buffer I
B is coupled to the output terminal of the corresponding unit circuit, and the output terminal of each unit circuit of the sense amplifier SA is coupled to the input terminal of the corresponding unit circuit of the data output buffer OB. An input terminal of each unit circuit of the data input buffer IB and an output terminal of each unit circuit of the data output buffer OB are commonly coupled to data input / output terminals IO0 to IO7, respectively.
The internal control signal WC is commonly supplied from the timing generation circuit TG to each unit circuit of the write amplifier WA, and the internal control signal OC is supplied to each unit circuit of the data output buffer OB.
Are commonly supplied.

Each unit circuit of the data input buffer IB has:
When the random access memory RAM is selected in the write mode, it takes in 8-bit write data supplied via the data input / output terminals IO0 to IO7, and transmits it to the corresponding unit circuit of the write amplifier WA. At this time, each unit circuit of the write amplifier WA outputs the internal control signal W
Upon receiving the high level of C, it selectively operates, converts write data transmitted from the corresponding unit circuit of the data input buffer IB into a predetermined write signal, and then converts the write data from the complementary common data lines CD0 * to CD7 * to Y. Switch circuit Y
The data is written to the selected eight memory cells of the memory array MARY via S.

On the other hand, each unit circuit of the sense amplifier SA
When the random access memory RAM is selected in the read mode, the selected 8 of the memory array MARY is selected.
The read signals output from the memory cells via the Y switch circuit YS and the complementary common data lines CD0 * to CD7 * are amplified, and the data output buffer OB is output.
To the corresponding unit circuit. At this time, each unit circuit of the data output buffer OB selectively operates in response to the high level of the internal control signal OC, and transfers read data transmitted from the corresponding unit circuit of the sense amplifier SA to the data input / output terminal IO0. ＩIO7 to the self-diagnosis circuit BIST.

The timing generation circuit TG selectively forms the various internal control signals based on the chip enable signal CEB, the write enable signal WEB, and the output enable signal OEB supplied from the self-diagnosis circuit BIST as a start control signal. And the random access memory R
Supply to each part of AM.

FIG. 4 shows the large scale integrated circuit device LS of FIG.
A block diagram of an embodiment of the self-diagnosis circuit BIST and the internal voltage generation circuit VG included in I is shown. Also,
FIG. 5 is a circuit diagram showing one embodiment of the internal voltage switching circuit VMDS included in the internal voltage generating circuit VG of FIG. With reference to these figures, a specific configuration and operation of the self-diagnosis circuit BIST and the internal voltage generation circuit VG included in the large-scale integrated circuit device LSI of this embodiment will be described. In FIG. 5, all the bipolar transistors shown are NPN transistors.

In FIG. 4, the self-diagnosis circuit BIST
Although not particularly limited, the selector SEL, the test pattern generation circuit TPG, and the test data comparison circuit TDCP
And a test control circuit TCTL which controls and controls the operation of these circuits.

Of these, one input terminal of the selector SEL is connected to the chip enable signal ECEB, write enable signal EWEB, output enable signal EOEB, and X address signals EAX0 to EA from an external access device.
Xi and Y address signals EAY0 to EAYj and input data EIO0 to EIO7 are supplied. A test chip enable signal TCEB, a write enable signal TWEB, and an output enable signal TOEB are supplied from the test control circuit TCTL to the other input terminal, and a test X address signal from the test pattern generation circuit TPG is supplied to the other input terminal. TX0 to TXi, Y address signals TY0 to TYj and test data TD0 to TD
D7 is supplied. The selector SEL is further supplied with a test control signal TST from the test control circuit TCTL, and a comparison result signal TR as an output signal from the test data comparison circuit TDCP.

The test control signal TST has a high level such as the ground potential GND when the large-scale integrated circuit LSI is set to the normal operation mode (hereinafter, the high level indicates a potential such as the ground potential GND). When the large-scale integrated circuit device LSI is selected in the power margin test or the data retention test mode, a low level such as the power supply voltage VEE (hereinafter, the low level indicates a potential such as the power supply voltage VEE). ). When the large-scale integrated circuit device LSI is subjected to the power margin test or the data retention test, the comparison result signal TR indicates that the comparison result between the test data TD0 to TD7 and the read data RD0 to RD7 by the test data comparison circuit TDCP is one. If both are normal, the signal is set to low level. If both bits do not match and become abnormal, the signal is set to high level.

When the large-scale integrated circuit device LSI is selected in the power margin test or the data retention test mode, the test pattern generation circuit TPG generates a test X address signal TX according to a predetermined algorithm.
0 to TXi, Y address signals TY0 to TYj and test data TD0 to TD7 are generated and supplied to the selector SEL, and the test data comparison circuit TDC uses the test data TD0 to TD7 as expected values for comparison and collation.
It is supplied to one input terminal of P.

The selector SEL is a large-scale integrated circuit device L
When the SI is in the normal operation mode and the test control signal TST is at the low level, the chip enable signal ECEB, the write enable signal EWEB, the output enable signal EOEB, and the X address signals EAX0 to EAXi, Y supplied from the external access device. Address signal EAY0
To EAYj and input data EIO0 to EIO7,
Chip enable signal CEB, write enable signal W
EB, output enable signal OEB, X address signal AX
0 to AXi and Y address signals AY0 to AYj and input data IO0 to IO7 to the random access memory RAM and
The output data IO0 to IO7 output from the AM is transmitted to an external access device as output data EIO0 to EIO7.

On the other hand, when the large-scale integrated circuit device LSI is set to the power margin test or the data retention test mode and the test control signal TST is set to the high level, the selector SEL outputs the test signal output from the test pattern generation circuit TPG. Chip enable signal TCEB, write enable signal TWEB, output enable signal TO
EB, X address signals TX0 to TXi, Y address signals TY0 to TYj and test data TD0 to TD7
To the random access memory RAM as the chip enable signal CEB, the write enable signal WEB, the output enable signal OEB, the X address signals AX0 to AXi, the Y address signals AY0 to AYj, and the input data IO0 to IO7. Output data IO0 to IO7 output from
The read data RD0 to RD7 are transmitted to the other input terminal of the test data comparison circuit TDCP.

When the large-scale integrated circuit device LSI is set to the power margin test or the data retention test mode, the test data comparison circuit TDCP tests the read data RD0 to RD7 output from the specified address of the random access memory RAM. Pattern generation circuit T
Test data TD0 supplied as expected values from PG
Compare with TD7 bit by bit. As a result, when all the bits match, the comparison result signal TR, which is the output signal, is set to low level, and when even one bit does not match, the comparison result signal TR is set to high level. The comparison result signal TR is supplied to the test control circuit TCTL, and is supplied to the determination of the test result, and is also supplied to the selector SEL, for example, the output data EIO0 to EI0.
It is output to an external probe tester or the like as a predetermined bit of O7.

Next, the internal voltage generating circuit VG includes, but is not limited to, voltage generating circuits VMDG and VMSG, and an internal voltage switching circuit VMDS receiving an internal voltage GVMD output from the voltage generating circuit VMDG. The voltage generation circuit VMDG is provided with a power supply voltage EV supplied from the outside.
A predetermined internal voltage GV based on EE and ground potential EGND
MD is generated and supplied to the internal voltage switching circuit VMDS.
Further, the voltage generation circuit VMSG also supplies the power supply voltage EVE.
E and a predetermined internal voltage VMS based on the ground potential EGND.
Is generated and supplied to the memory array MARY. The internal voltage switching circuit VMDS further receives a 3-bit potential control signal V from the test control circuit TCTL of the self-diagnosis circuit BIST.
C1 to VC3 are supplied.

Here, as shown in FIG. 5, the internal voltage switching circuit VMDS has a voltage generation circuit VMD
A transistor T1 receiving an output of G, that is, an internal voltage GVMD, and a transistor T2 having a base receiving the collector potential of the transistor T1 are included. Ground potential GN
A load resistor R1 is provided between D and the collector of the transistor T1, and its emitter is connected to the internal voltage supply point VEE.
Is provided with an emitter resistor R2. Further, the collector of the transistor T2 is coupled to the ground potential GND,
Its emitter is comprised of two diodes D in series form.
1 and D2, a transistor T3 receiving a constant voltage VB at its base, and an emitter resistor R3 of the transistor T3.
And to the internal voltage supply point VEE.

The emitter of the transistor T2 constituting the internal voltage switching circuit VMDS, ie, the anode of the diode D1, receives the high level of the potential control signal VC1 and is selectively turned on in response to the output terminal VM via the switch S1.
D. The cathode of the diode D1, that is, the anode of the diode D2 is coupled to the output terminal VMD via the switch S2 which is selectively turned on in response to the high level of the potential control signal VC2.
The cathode of the transistor T2, that is, the collector of the transistor T3 is coupled to the output terminal VMD via the switch S3 which is selectively turned on in response to the high level of the potential control signal VC3.

Needless to say, the internal voltage switching circuit VMD
The transistor T1 of the S acts as a constant current source together with the emitter resistor R2, passes a collector current having a value according to the internal voltage GVMD to the load resistor R1, and
Is given a predetermined constant potential. Transistor T2 lowers the constant potential at its base by the base-emitter voltage and transmits it to its emitter. Transistor T3 forms a constant current source together with emitter resistor R3, and has a collector according to constant voltage VB. Current flows through transistor T2 and diodes D1 and D2. further,
The diodes D1 and D2 sequentially lower the constant potential at the emitter of the transistor T2 by the forward voltage and transmit the same to the cathodes thereof.

In this embodiment, the potential at the emitter of the transistor T2, that is, at the anode of the diode D1, is designed to be the maximum value allowed as the operation power supply of the CMOS memory cells MC constituting the memory array MARY, for example, + 0.3V. . The diode D
1 is designed to be at its center value, for example, -0.75V, and the potential at the cathode of diode D2, that is, the collector of transistor T3, is at its minimum allowed value, for example, -1. It is designed to be 8V.

From these, the internal voltage switching circuit VM
The potential of the internal voltage VMD at the output terminal VMD of DS is the maximum value allowed as the operating power supply of the CMOS memory cell MC when the potential control signal VC1 supplied from the self-diagnosis circuit BIST is alternatively set to a high level. That is, for example, + 0.3V. Further, the potential control signal VC2
Is alternatively set to the high level, the center value thereof is, for example, -0.75 V. When the potential control signal VC3 is alternatively set to the high level, the allowable minimum value thereof, for example, -1. .8V.

FIG. 6 shows the large-scale integrated circuit device LS of FIG.
FIG. 7 shows a pattern diagram of an embodiment for explaining a test pattern at the time of a logic test of the random access memory RAM of I. FIG.
FIG. 5 is a flowchart of an embodiment for explaining a processing procedure at the time of a logic test of M. FIG. 8 is a time chart of one embodiment at the time of the power margin test of the large-scale integrated circuit device LSI of FIG. 1, and FIG. 9 is a time chart of one embodiment at the time of the data retention test. It is shown. With reference to these figures, specific operations and characteristics of the large-scale integrated circuit device LSI of this embodiment at the time of a logic test, a power supply margin test, and a data retention test by the self-diagnosis circuit BIST will be described. The logic test shown in FIGS. 6 and 7 is used for a function test for confirming an intended function of the large-scale integrated circuit device LSI, and a power margin test for the CMOS memory cells MC constituting the memory array MARY. Also, it is used for function confirmation at the time of data retention test.
In FIG. 6, the X address signal AX, that is, AX0
To AXi and the Y address signal AY, that is, AY0 to AY
Yj are both 16 bits, for example, so-called 16 bits.
Displayed as a decimal number.

In FIG. 6, a large-scale integrated circuit device LSI
In the logical test of the random access memory RAM, first, a predetermined test pattern, that is, test data TD0 to TD7 is sequentially written to all addresses of the random access memory RAM in the write mode and read in the read mode, and the read data RD0 to RD7 are read. This is realized by performing a comparison and collation operation with test data TD0 to TD7 that are expected values. The test pattern generating circuit TPG of the self-diagnosis circuit BIST changes the X address signal AX from "0000" to "FFFF" while changing the Y address signal AY in the range from "0000" to "FFFF" in each of the write mode and the read mode. FFF
F ". The test data TD0 to T0, which are write data or expected values, are adjusted accordingly.
D7 is alternately all-bit logic "0", that is, "0000".
Alternatively, all bit logic is “1”, that is, “1111”.

Test control circuit T of self-diagnosis circuit BIST
As shown in FIG. 7, the CTL first performs step ST1.
Thereby, the address, that is, both the X address signal AX and the Y address signal AY are initialized to “0000”. Next, in step ST2, the test data TD, that is, the first TD0 to TD7 is written to the head address, and in step ST3, this is read data RD, ie, R
Read as D0-RD7, and test data comparison circuit T
Compare and collate by DCP. As a result, when the read data RD matches the expected value of the test data TD with all the bits, and the comparison result signal TR, which is the output signal of the test data comparison circuit TDCP, is set to low level, the process proceeds to step ST5.
As a result, the test result of logic "0" is output to output data EIO0
所 定 EIO7 are output to the external probe tester as predetermined bits, and when any of the bits do not match and the comparison result signal TR is set to the high level, the test result of the logic “1” is output to the external probe tester in step ST6. Output.

Self-diagnosis circuit B that has finished outputting the test results
The IST updates the address, that is, the X address signal AX and the Y address signal AY in step ST7,
In step ST8, it is determined whether or not the address counter has overflowed, that is, whether or not the write / read test for all addresses has been completed. As a result, if the address counter has not overflown, the process returns to step ST2 and thereafter to repeat writing and reading of the test data TD. If the address counter overflows, the logic test is terminated.

On the other hand, when the large-scale integrated circuit device LSI is set to the power supply margin test mode, the self-diagnosis circuit BIS
As shown in FIG. 8, T is a state in which the potential control signal VC2 is alternatively set to the high level by the stage T11, that is, the internal voltage VMD which is the operation power supply of the memory cell MC of the memory array MARY is set at the center thereof. A write / read test is performed with the value, that is, for example, −0.75 V at a normal potential. Next, by the stage T12, the potential control signal VC1 is alternatively set to the high level, that is, the internal voltage VMD is set to the maximum value of the allowable range, that is, for example, to the state of + 0.3V, in other words, the high potential is set. After the writing / reading test is performed in a state where the stress is imposed, the potential control signal VC3 is alternatively set to the high level by the stage T13, that is, the internal voltage VMD is set to the minimum value of the allowable range.
That is, for example, the write / read test is performed in a state where the voltage is set to −1.8 V, in other words, in a state where a low potential stress is imposed. Then, the potential control signal VC2 is alternatively set to the high level again by the stage T14 to return the internal voltage VMD to the normal potential, that is, for example, -0.75V, and the test result is output to an external probe tester as a so-called bit map.

Next, when the large-scale integrated circuit device LSI is set to the data retention test mode, as shown in FIG.
21, the potential control signal VC2 is alternatively set to a high level, and the internal voltage VMD is set to its central value, for example,-.
With the voltage set to 0.75 V, the test data TD is written at the normal potential. Thereafter, by the stage T22, the potential control signal VC1 or VC3 is alternatively set to the high level, and the internal voltage VMD is set to the maximum value or the minimum value of the allowable range, that is, for example, + 0.3V or -1.8V. After performing a retention test while imposing a stress while keeping the predetermined time, the potential control signal VC2 is alternately set to the high level again by the stage T23, and the internal voltage VMD is set to the normal potential, that is, for example, −0.7.
The voltage is returned to 5 V, a read test is performed, and the result is output as a bit map to an external probe tester.

As described above, the large-scale integrated circuit device LSI of this embodiment is provided with the self-diagnosis circuit BIST which can autonomously execute the logic test of the random access memory RAM, and has its internal voltage generation circuit VG Is a potential control signal VC generated by the self-diagnosis circuit BIST.
C constituting the memory array MARY in accordance with 1 to VC3
An internal voltage switching circuit VMDS capable of selectively switching the potential of an internal voltage VMD as a high-potential-side operation power supply of the MOS memory cell MC is provided. As described above, the internal voltage switching circuit VMDS has a relatively simple circuit configuration, and the potential switching operation is performed relatively quickly. In addition, a series of processes related to the power margin test and the data retention test are autonomously controlled by the test control circuit TCTL of the self-diagnosis circuit BIST, and there is no need to involve an external probe tester. As a result of these,
In the large-scale integrated circuit device LSI of this embodiment, the function test of the built-in random access memory RAM, including the power margin test and the data retention test, can be performed autonomously and efficiently. The test cost of the circuit device LSI can be reduced.

The functions and effects obtained from the above embodiment are as follows. (1) For example, in a large-scale integrated circuit device incorporating a random access memory and a self-diagnosis circuit, the self-diagnosis circuit includes a test pattern generation circuit and a test data comparison circuit for a logic test of a random access memory and the like. In addition, at the time of a power margin test or a data retention test, an internal voltage switching circuit that selectively switches the potential of an internal voltage supplied as operating power of a memory cell forming a memory array in accordance with a potential control signal is provided. The effect is obtained that the function test of the random access memory RAM including the test and the data retention test can be performed autonomously and efficiently.

(2) According to the above item (1), while suppressing an increase in the chip size, the number of test steps for a large-scale integrated circuit device and the like and a random access memory RAM incorporated therein is reduced, and the time required for the test is reduced. Can be shortened. (3) According to the above items (1) and (2), an effect is obtained that the test cost of a large-scale integrated circuit device or the like incorporating a random access memory RAM and a self-diagnosis circuit can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is. For example, in FIG. 1, the large-scale integrated circuit device LSI can include a plurality of random access memories RAM, and can also include various other functional blocks. The storage data input or output from an external access device including a probe tester is, for example, 16 bits or 3 bits.
An arbitrary number of bits such as two bits can be used as a unit, and the names and combinations of the activation control signal and the address signal and the effective level thereof can be arbitrarily set. The large-scale integrated circuit device LSI does not always require a bipolar CMOS circuit as a basic element. The block configuration of the large-scale integrated circuit device LSI can take various embodiments, and the semiconductor substrate CHIP
The same applies to the shape of. The polarity and absolute value of the power supply voltage EVEE, the internal voltages VMD and VMS, and the VEE can take various embodiments.

In FIGS. 2 and 3, the memory array MARY of the random access memory RAM can be divided into a plurality of sub memory arrays or memory mats including its peripheral circuits. Also, the random access memory R
The AM may be composed of, for example, a dynamic RAM or the like, and the memory cells MC constituting the memory array MARY may be so-called high resistance load type memory cells. The memory array MARY can include any number of redundant elements, and the random access memory RA
The block configuration and the like of M can take various embodiments.

In FIG. 4, the block configuration of the self-diagnosis circuit BIST is not restricted by this embodiment, and the types of signals transmitted and received between the blocks and their effective levels are the same. Internal voltage generating circuit VG can further include a voltage generating circuit for generating other various internal voltages, and internal voltage switching circuit VMDS shown in FIG.
And the conductivity type of each transistor can be arbitrarily set.

In FIG. 6, the test pattern generated by test pattern generation circuit TPG of self-diagnosis circuit BIST is only an example and does not affect the gist of the present invention. The specific number of bits of the X address signals AX0 to AXi and the Y address signals AY0 to AYj,
The switching order and the like can be arbitrarily set. In FIG. 7, various processing flows during a logic test of a large-scale integrated circuit device LSI can be considered. 8 and 9, the combinations of the test stages at the time of the power supply margin test and the data retention test and the potential control signals VC1 to VC1 are shown.
The relationship between VC3 and the potential of the internal voltage VMD can take various embodiments.

In the above description, the invention made mainly by the present inventor is applied to a large-scale integrated circuit device having a built-in random access memory and a self-diagnosis circuit as a background of the application and constituting a large-scale computer system. Although the above description has been made, the present invention is not limited to this, and can be applied to, for example, a logic integrated circuit device incorporating various other semiconductor memories, or a communication integrated circuit device in which analog and digital are mixed, for example. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device having a built-in functional block whose operating characteristic is at least affected by a potential fluctuation of an operating power supply, and a device or a system including the same.

[0062]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for example, in a large-scale integrated circuit device incorporating a random access memory and a self-diagnosis circuit, the self-diagnosis circuit includes a power supply in addition to a test pattern generation circuit and a test data comparison circuit for a logic test such as a random access memory. At the time of a margin test or a data retention test, an internal voltage switching circuit for selectively switching the potential of an internal voltage supplied as an operating power supply of a memory cell forming a memory array in accordance with a potential control signal is provided, and a power supply margin test and a data retention test are performed. By providing functions that can be implemented autonomously,
With the built-in self-diagnosis circuit, functional tests including a power margin test and a data retention test can be performed autonomously and efficiently, thereby reducing the test cost of a large-scale integrated circuit device or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a large-scale integrated circuit device to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a random access memory included in the large-scale integrated circuit device of FIG.

FIG. 3 is a partial circuit diagram showing one embodiment of a memory array and a Y switch circuit included in the random access memory of FIG. 2;

FIG. 4 is a block diagram showing one embodiment of a self-diagnosis circuit and an internal voltage generation circuit included in the large-scale integrated circuit device of FIG.

FIG. 5 is a circuit diagram showing an embodiment of an internal voltage switching circuit included in the internal voltage generation circuit of FIG.

FIG. 6 is a pattern diagram showing one embodiment for explaining a test pattern at the time of a logic test of the large-scale integrated circuit device of FIG. 1;

FIG. 7 is a flowchart showing an embodiment for explaining a processing procedure at the time of a logic test of the large-scale integrated circuit device of FIG. 1;

FIG. 8 is a time chart showing one embodiment at the time of a power supply margin test of the large-scale integrated circuit device of FIG. 1;

FIG. 9 is a time chart showing one embodiment of a data retention test of the large-scale integrated circuit device of FIG. 1;

[Explanation of symbols]

LSI: large-scale integrated circuit device, CHIP: semiconductor substrate, BIST: self-diagnosis circuit, VG: internal voltage generation circuit, RAM: random access memory, ECEB,
CEB: Chip enable signal, EWEB, WEB ...
... Write enable signal, WOEB, OEB ... Output enable signal, EAX0 to EAXi, AX0 to AXi
... X address signal, EAY0 to EAYj, AY0 to AY
j... Y address signal, EIO0 to EIO7, IO0
IO7 ... input / output data, EVEE, VEE ... power supply voltage, EGND, GND ... ground potential, VC ... potential control signal, VMD, VMS ... internal voltage. MARY memory array, XD X address decoder, X0 to Xi internal X address signals, XB X address buffer, YS Y switch circuit, YD Y
Address decoder, Y0 to Yj... Internal Y address signal, YB... Y address buffer, CD0 * to CD7 *
…… Complementary common data line, WA …… Write amplifier, SA…
... Sense amplifier, IB ... Data input buffer, OB ...
... Data output buffer, TG ... Timing generation circuit. W0 to Wm word line, B0 * to Bn * complementary bit line, MC CMOS memory cell, P1 to P4 P
Channel MOSFETs, N1 to N4... N-channel MOSFETs, YS0 to YSp... TCTL: test control circuit, SEL: selector, T
PG: Test pattern generation circuit, TDCP: Test data comparison circuit, VMDG, VMSG ... Voltage generation circuit, VMDS ... Internal voltage switching circuit, TST ... Test control signal, TCEB ... Test chip enable signal, TWEB ...... Test write enable signal, TO
EB: Test output enable signal, VC1 to VC3
...... Potential control signal, TX0 to TXi ... X address signal for test, TY0 to TYj ... Y address signal for test, TD0 to TD7 ... test data (expected value), RD
0 to RD7 ... read data, TR ... comparison result signal,
GVMD: Internal voltage. T1 to T3: NPN type bipolar transistor, R1
... R3 ... resistance, D1-D2 ... diode, S1-S
3. Switch. AX: X address signal, AY: Y address signal. ST1 to ST8 ... processing steps, TD ... test data, RD ... read data, T11 to T14, T21 to
T23 ... Test stage.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideki Hayashi 5-22-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Ultra SII Systems Co., Ltd. (reference) 2G032 AA07 AB05 AK14 AK19 5F038 BB02 BB05 DF05 DF14 DF16 DT02 DT03 DT07 DT08 DT10 DT16 DT17 EZ20 5L106 AA01 AA02 DD08 DD36 9A001 BB05 JJ48 KK31 KK54 LL06

Claims (5)

[Claims] 1. A function block that uses a predetermined internal voltage as an operation power supply, and is formed on the same semiconductor substrate surface as the function block,
A semiconductor integrated circuit device, comprising: a self-diagnosis circuit capable of autonomously performing a function test on the potential change of the internal voltage of the function block. 2. The internal voltage generator according to claim 1, wherein the functional block is a semiconductor memory, and wherein the semiconductor integrated circuit device generates the internal voltage based on a predetermined power supply voltage externally supplied. A semiconductor integrated circuit device comprising a circuit. 3. The function test according to claim 2, wherein the semiconductor memory includes a memory array in which predetermined memory cells using the internal voltage as an operation power supply are arranged in a lattice. A semiconductor integrated circuit device including a power margin test and a data retention test for the internal voltage. 4. The self-diagnosis circuit according to claim 1, wherein the self-diagnosis circuit includes: a test pattern generation circuit that generates a predetermined test pattern during the power margin test or the data retention test; A test pattern comparison circuit that compares read data read from the random access memory during a test or a data retention test with an expected value output from the test pattern generation circuit; and a potential of the internal voltage according to a predetermined potential control signal. And an internal voltage switching circuit for selectively switching the voltage. 5. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device comprises a bipolar circuit and a CMO.
A large scale integrated circuit device of a bipolar CMOS type having an S circuit as a basic element, wherein the large scale integrated circuit device constitutes a predetermined large computer system.