JP2000294675A - Chip carrier, semiconductor device, and method of manufacturing chip carrier - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a chip carrier and a semiconductor device capable of obtaining high bonding reliability after mounting an IC chip by separating a wiring layer and a bump formation surface of the chip carrier. A chip carrier is obtained by forming a bump formed of an electrode pad and a bonding solder on one surface of an insulating substrate and forming a multilayer wiring formed of a wiring layer and a wiring layer on the other surface. Further, the semiconductor device is obtained by bonding the pads of the IC chip and the bumps 21 of the chip carrier substrate and mounting them by flip-chip soldering.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a chip carrier and a semiconductor device used for flip-chip mounting using solder.

[0002]

2. Description of the Related Art In a conventional solder flip chip mounting type semiconductor device, when mounting an IC chip, solder spreads over a wiring layer of a wiring board and spreads, or excess solder overflows and short-circuits with an adjacent IC chip pad. In order to prevent this, an insulating resin layer called a solder resist is provided on the outermost layer. Most of the wiring layer is covered with this solder resist, and only pads required for mounting are exposed to the outside. Therefore, the pad is located at a position inside the solder resist and lower than the solder resist surface, and is separated from the pad of the IC chip.

[0003] Therefore, solder bumps are formed on the pads of the chip carrier surrounded by the solder resist to facilitate bonding with the pads of the IC chip. If the opening radius of the solder resist pad portion and the resist thickness are constant and the amount of supplied solder is constant, the height of the solder bump can be controlled, and high bonding reliability can be maintained.

[0004] However, due to process variations,
The height of the solder bumps of the chip carrier varies.
As a result, there are places where bonding is not performed between the pads of the IC chip and the solder bumps of the chip carrier. Since the solder resist is interposed between the wiring layer of the chip carrier and the IC chip pad, the solder bump of the chip carrier and
Since a gap is formed between the C chip pad and the gap, the distance is increased. Therefore, it is necessary to form a bump on the pad on the IC chip side using gold, solder, or the like.

[0005] The bumps formed on the IC chip are required to have a certain degree of height accuracy, and the wet plating method which is currently widely used significantly reduces the yield of the IC chip by adding a bump forming step. There is a problem.

[0006] Further, since the IC chip is manufactured using equipment that is more expensive than a printed circuit board, a chip carrier, or the like, the operation rate of the equipment greatly affects the manufacturing cost of the IC chip. Therefore, forming bumps on an IC chip lowers the yield of the IC chip, and places a great burden on semiconductor manufacturers.
For this reason, we would like to skip the process of forming bumps on IC chips if possible.

Accordingly, forming bumps on a chip carrier rather than forming them on the IC chip side contributes to an improvement in the yield of IC chips, which are high value-added components, and has the advantage of reducing the manufacturing risk by shortening the process. Can be expected.

[0008] However, the current chip carrier manufacturing method employs a method of stacking layers from the inner layer to the outer layer, or pressing and laminating to finally form a solder resist. It is difficult to make the configuration in which the pad protrudes from the fin.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a chip capable of obtaining high bonding reliability after mounting an IC chip by separating a wiring layer and a bump forming surface of a chip carrier. An object is to provide a carrier and a semiconductor device.

[0010]

According to a first aspect of the present invention, there is provided a chip carrier in which a wiring layer and a bump are formed on an insulating substrate.
The chip carrier is characterized in that the wiring layer is formed on one surface of the insulating substrate and the bumps are formed on the other surface.

According to a second aspect of the present invention, there is provided the chip carrier according to the first aspect, wherein the bump is formed of a solder joint to an electrode pad.

According to a third aspect of the present invention, there is provided a semiconductor device characterized in that an IC chip is mounted by a solder flip chip using the chip carrier according to the first or second aspect.

Furthermore, the present invention provides a method for manufacturing a chip carrier according to claim 1 or 2, wherein the method comprises the following steps. (A) Spacer layer 12 and insulating substrate 1 on metal plate 11
Step of forming 3. (B) a step of forming openings 14 at predetermined positions of the spacer layer 12 and the insulating substrate 13; (C) forming a joining braze 15 having a predetermined thickness in the opening 14 by electrolytic plating; (D) A step of forming an electrode pad 16 by electrolytic plating on the remaining portion of the opening 14 where the joining braze 15 is formed. (E) Wiring layer 17 on electrode pad 16 and insulating substrate 13
Forming a multi-layer wiring composed of steps (1) and (19). (F) A step of peeling and removing the metal plate 11 and the spacer layer 12 to form the chip carrier 10.

[0014]

Embodiments of the present invention will be described below. FIG. 1A is a schematic perspective view showing one embodiment of the chip carrier of the present invention, and FIG. 1B is a perspective view showing one embodiment of the chip carrier of the present invention in FIG. 2 (a) to 2 (f) are sectional views showing an embodiment of the chip carrier of the present invention in the order of steps, and FIG. 3 (a) is a sectional view showing the structure of the chip carrier of the present invention. Using IC
FIG. 3B is a schematic perspective view showing one embodiment of the semiconductor device of the present invention in which a chip is mounted by flip-chip soldering, and FIG. 3B is a schematic perspective view showing one embodiment of the semiconductor device of the present invention. FIG.

FIG. 1A shows a chip carrier 10 according to the present invention.
As shown in (b), a bump 21 comprising an electrode pad 16 and a brazing filler metal 15 is formed on one surface of an insulating substrate 13 and a multilayer wiring comprising a wiring layer 17 and a wiring layer 19 is formed on the other surface. In addition, I
The semiconductor device 30 of the present invention is obtained by mounting the C chip 31 by solder flip chip. The bump 21 is formed such that a part of the electrode pad 16 is embedded in the insulating substrate 13.
Since the insulating substrate 13 also serves as a solder resist, there is no need to form a solder resist around bumps as in a conventional chip carrier, and the height of the bumps 21 from the surface of the insulating substrate 13 is reduced in a later manufacturing process. Is determined by the thickness of the spacer layer and the height of the joining braze 16 described above. If both are formed with high precision, the height of the bump 21 can be formed with high precision. High bonding reliability between the pads 32 of the chip 31 and the bumps 21 of the chip carrier 10 can be realized.

Hereinafter, a method of forming the chip carrier 10 of the present invention will be described. First, the spacer layer 1 is formed on the metal substrate 11.
2 and an insulating substrate 13 are formed (see FIG. 2A). Here, the metal substrate 11 can be used as long as it is a metal having conductivity, but a stainless steel plate is preferable here in terms of a manufacturing process. The spacer layer 12 is used to form the joining solder 15 and the electrode pad 16 by electrolytic plating, and any resin having an insulating property can be used, but it is finally peeled and removed in a later step. Therefore, a liquid photosensitive resist or a dry film resist which has sufficient resistance to the electrolytic plating process and is easy to peel off is preferable. In addition, since the thickness of the spacer layer 12 determines the height of the bump 21 from the surface of the insulating substrate 13, it is necessary to form a layer having no uniform thickness variation. Further, the height of the bump 21 from the surface of the insulating substrate 13 is 5 to 2
00 μm, preferably 40 to 100 μm.

The insulating substrate 13 serves as an insulating substrate of the chip carrier 10, and is required to have insulating properties, heat resistance and mechanical strength, and is preferably a polyimide film. The insulating substrate 13 may be used by curing a liquid resin in addition to the film. In this case, polyester, epoxy, acrylic, polyimide resin and the like can be used, but polyimide resin is also preferable.

Next, an opening 14 for forming a bump 21 comprising an electrode pad 16 and a bonding solder 15 is formed in the spacer layer 12 and the insulating substrate 13 by excimer laser processing (see FIG. 2B). The shape of the opening 14 is generally a column or a truncated cone.

Next, a brazing filler metal 15 is formed in the opening 14 by electrolytic plating using the metal substrate 11 as a plating electrode (see FIG. 2C). As the metal material of the soldering joint 15, a metal that can be formed by a wet plating method and that is melted at the heating temperature during mounting to complete the joining with the pad of the IC chip is desirable. Here, lead-tin solder is preferred.

Next, an electrode pad 16 is formed on the joining solder 15 in the opening 14 by electrolytic plating using the metal substrate 11 as a plating electrode (see FIG. 2D). As the metal material of the electrode pad 16, copper and copper alloy having low electric resistance are most suitable. Further, since the wiring layer is formed of copper metal, it is advantageous from the viewpoint of reliability of connection with the wiring layer. The electrode pad 16 can be formed by a metal paste filling method by screen printing or a high-speed electroless plating method in addition to the electrolytic plating method.

Next, a wiring layer 17 is formed on the electrode pad 16 by an additive method or a semi-additive method.
Further, an insulating layer 18 is formed, a wiring layer 19 connected to the wiring layer 17 via via is formed on the insulating layer 18 by an additive method or a semi-additive method, and a two-layer multilayer wiring is formed (FIG. 2 ( e)). Here, the description has been made of the two-layer wiring, but the present invention is not particularly limited. A single-layer wiring or a multi-layer wiring of two or more layers can be set as needed.

Next, the substrate on which the bonding solder 15, the electrode pads 16, the wiring layers 17 and the wiring layers 19 are formed is immersed in a dedicated release liquid, and the metal substrate 11 and the spacer layer 12 are separated and removed. It is possible to produce the chip carrier 10 of the present invention in which the bumps 21 composed of the bonding solder 15 and the electrode pads 16 are formed on one surface of the insulating substrate 13 and the multilayer wiring composed of the wiring layers 17 and 19 is formed on the other surface. (See FIG. 2 (f)).

Further, the semiconductor device 30 can be obtained by bonding the pads 32 of the IC chip 31 and the bumps 31 of the chip carrier 10 and performing solder flip chip mounting (see FIGS. 3A and 3B).

[0024]

The present invention will be described in detail with reference to the following examples.
First, a metal substrate 1 made of a 0.3 mm thick stainless steel plate was used.
1 and a 25 μm thick dry film resist (H-K8
25: Hitachi Chemical Co., Ltd.) was laminated to form a spacer layer 12, and a 90 μm-thick polyimide film (Kapton: manufactured by DuPont) was laminated using the spacer layer 12 as an adhesive layer to form an insulating substrate. 13 was formed.

Next, a truncated cone-shaped opening 14 of 40 μmφ was formed at a predetermined position on the spacer layer 12 and the insulating substrate 13 on the metal substrate 11 by using an excimer laser processing machine.

Next, the metal substrate 11 is used as a plating electrode,
Electrolytic solder plating is performed, and lead 14 mm thick
A joining solder 15 made of tin solder was formed.

Next, the metal substrate 11 is used as a plating electrode.
An electrode pad 1 made of copper metal and having a thickness of 100 μm on the soldering joint 15 of the opening 14 by electrolytic copper plating made of a copper sulfate bath.
6 was formed.

Next, copper was sputtered on the insulating substrate 13 and the electrode pads 16 to form a thin film conductor layer having a thickness of about 3000 mm. Further, a 15 μm-thick copper conductor layer is formed on the thin-film conductor layer by electrolytic copper plating, and the conductor layer is patterned using a photolithography process and an etching process to form a wiring electrically connected to the electrode pad 16. Layer 17 was formed.

Next, an epoxy resin solution is applied on the insulating substrate 13 and the wiring layer 17 by screen printing, dried, and dried.
By curing, the insulating layer 18 was formed. Further, a via hole is formed at a predetermined position of the insulating layer 18 by laser processing, a copper conductor layer is formed on the via hole and the insulating layer 18, and a patterning process is performed using a photolithography process and an etching process to form a wiring layer 17. A wiring layer 19 connected via was formed.

Next, the substrate on which the bonding solder 15, the electrode pads 16, the wiring layers 17 and the wiring layers 19 are formed is immersed in a 10% caustic soda solution to peel and remove the metal substrate 11 and the spacer layer 12. The chip carrier 10 having the bumps 21 formed of the bonding solder 15 and the electrode pads 16 on one surface of the insulating substrate 13 and the multilayer wiring formed of the wiring layers 17 and 19 on the other surface was produced.

Since the chip carrier 10 can use the polyimide insulating substrate 13 as a solder resist for chip mounting, the step of forming the solder resist can be omitted.

Further, the semiconductor device 30 was manufactured by bonding the pads 32 of the IC chip 31 and the bumps 31 of the chip carrier 10 and mounting them by flip-chip soldering. As a result of flip-chip mounting the IC chip using the chip carrier 10 of the present invention, an appropriate amount of solder is supplied to the pad 32 side of the IC chip 31, and the semiconductor device 30 of the present invention having high bonding reliability is obtained. Was.

[0033]

According to the chip carrier of the present invention, the solder substrate and the bumps composed of the electrode pads are formed on one surface of the insulating substrate, and the wiring layer is formed on the other surface. Therefore, the step of forming the solder resist can be omitted. Furthermore, when the bumps are formed by the manufacturing method of the present invention, the thickness of the brazing filler metal can be accurately formed, the bonding brazing material (material composition and thickness) can be set according to the mounting conditions, and the uniform height can be set on the insulating substrate. Bumps can be formed. Furthermore, a semiconductor device having high bonding reliability can be realized when solder flip chip mounting is performed using the chip carrier of the present invention. As a result, a semiconductor device having high mounting reliability can be provided, and excellent practical effects can be exhibited in the semiconductor package field.

[Brief description of the drawings]

FIG. 1A is a schematic perspective view showing one embodiment of a semiconductor device substrate of the present invention. (B) is a schematic cross-sectional view taken along line AA of a schematic perspective view of one embodiment of the semiconductor device substrate of the present invention.

FIGS. 2A to 2F are cross-sectional views schematically illustrating the steps of manufacturing a semiconductor device substrate according to an embodiment of the present invention in the order of steps.

FIG. 3 (a) shows an example of a semiconductor device using the semiconductor device substrate of the present invention.
1 is a schematic perspective view showing one embodiment of a semiconductor device of the present invention in which a C chip is mounted by a solder flip chip. (B) is a schematic cross-sectional view taken along line BB of a schematic perspective view of one embodiment of the semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Chip carrier 11 ... Metal board 12 ... Spacer layer 13 ... Insulating board 14 ... Opening 15 ... Bonding solder 16 ... Electrode pad 17 ... Wiring layer 18 ... Insulating layer 19 ... Wiring layer 21 Bump 30 Semiconductor device 31 IC chip 32 Pad

Claims (4)

[Claims] 1. A chip carrier in which a wiring layer and a bump are formed on an insulating substrate, wherein the wiring layer is formed on one surface of the insulating substrate, and the bump is formed on the other surface. . 2. The chip carrier according to claim 1, wherein said bumps are made of solder to be bonded to electrode pads. 3. A semiconductor device, wherein an IC chip is mounted on the chip carrier according to claim 1 by solder flip chip mounting. 4. The method for manufacturing a chip carrier according to claim 1, comprising the following steps. (A) forming a spacer layer (12) and an insulating substrate (13) on a metal plate (11); (B) forming an opening (14) at a predetermined position of the spacer layer (12) and the insulating substrate (13); (C) a step of forming a joining braze (15) having a predetermined thickness in the opening (14) by electrolytic plating. (D) forming an electrode pad (16) by electrolytic plating on the remaining portion of the opening (14) in which the joining braze (15) is formed; (E) A step of forming a multilayer wiring composed of wiring layers (17) and (19) on the electrode pads (16) and the insulating substrate (13). (F) forming a chip carrier (10) by peeling and removing the metal plate (11) and the spacer layer (12);