JP2000294674A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To overcome the traditional idea of using an organic base material, to solve problems from a completely new perspective, to have excellent dimensional stability and reliability of component connection, and to have high heat dissipation. In addition, the present invention provides an epoch-making rational and economical semiconductor device capable of realizing high-density wiring and the like and including and incorporating an electronic device function part, and a method of manufacturing the same. A conductor penetrating from one side to the other side.
5, a connecting body 9 interposed between these silicon substrates 3 and having a conductor portion 13 penetrating from one surface side to the other surface side. And a conductor 5 of the silicon substrate 3 and
A conductor 5 of another silicon substrate 3 is electrically connected to the conductor 5 via a conductor 13 of the connection body. Silicon substrate 3
, An electronic device function unit may be formed. Connection 9
Can be composed of a thin resin base film or a glass base.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an organic substrate is used as a substrate for mounting components, a circuit pattern is formed on the surface thereof, and various types of components are mounted. However, this type of conventional substrate has the following problems.

[0003]

SUMMARY OF THE INVENTION High-density wiring using an organic base material has dimensional changes and instability in operation.
There is a limit in increasing the density, and there are many problems to be solved in terms of poor connection, reduced reliability, and long life due to differences in thermal expansion between component elements. Therefore, in the present invention,
In order to solve the problem from a completely new point of view, neglecting the traditional idea of using an organic base material, it has high dimensional stability, excellent component connection reliability, high heat dissipation, high density wiring, etc. It is an object of the present invention to provide a very innovative, rational, and economical semiconductor device capable of including and incorporating various functional units or functional elements (electronic device functional units) and a method of manufacturing the same. Make it an issue.

[0004]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a plurality of silicon substrates having a conductor penetrating from one surface side to the other surface, and a plurality of silicon substrates interposed between these silicon substrates. And a connector having a conductor portion penetrating from one surface side to the other surface side, and a conductor portion of the silicon substrate,
The configuration is characterized in that it is electrically connected to the conductor of another silicon substrate via the conductor of the connection body.

[0005] Preferably, an electronic device function section is formed on at least one silicon substrate. Preferably, the connection body is made of a thin resin base material. Preferably, the connection body is made of a thin-layer glass substrate. In the method for manufacturing a semiconductor device according to the present invention, a step of forming a conductor portion penetrating from one surface side to the other surface side on a silicon substrate; and a step of forming a conductor portion penetrating from one surface side to the other surface side on the connection body. Forming, a connecting body is interposed between the silicon substrates, and the conductor of one silicon substrate and the conductor of another silicon substrate are electrically connected via the conductor of the connecting body. Integrating the silicon substrate and the connection body so as to integrate the silicon substrate and the connection body.

Preferably, the step of forming the conductor portion in the silicon substrate includes forming a through hole in the silicon substrate and filling the through hole with a conductor member. Preferably, the step of forming the conductor portion in the connection body includes forming a through hole in the thin resin base material and filling the through hole with a conductor member. Preferably, the step of forming the conductor portion in the connection body includes forming a through-hole in the thin glass substrate and filling the through-hole with a conductor member. Preferably, the method includes a step of forming an electronic device function unit on the silicon substrate.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional side view of a silicon multilayer substrate according to one embodiment of the present invention, on which a predetermined electronic component C is mounted. The substrate 1 according to the present embodiment includes a plurality of silicon substrates 3 (3 in the illustrated example) in which conductor portions (vias filled with conductor members) are formed.
This is a multi-layer substrate formed by laminating and integrating with a thin-layered connector (adhesive layer) 9 therebetween.

The actual process of manufacturing the illustrated substrate will be described in detail with reference to FIGS. (1) First, a predetermined shape and dimensions (for example, a thickness of about 0.5 m
A silicon (Si) substrate 3 having a diameter of about 200 mm and a diameter of about 200 mm is prepared (FIG. 2). (2) Next, a plurality of through holes 3a having a desired shape and dimensions (for example, a diameter of about 0.2 mm) are formed in the silicon substrate 3 by, for example, electric discharge machining (or an ion milling method, a laser method, or the like). _{In two} streams (for example, about 110
An oxidation treatment is performed at 0 ° C.) to form an insulating layer on the surface of the silicon substrate 3 and on the inner wall of the through hole (FIG. 3).

Incidentally, there are the following two methods for forming the insulating layer on the silicon substrate 3. (A) The silicon substrate 3 on which the through hole 3a is formed is oxidized, and SiO
A method of forming _two layers. (b) A method in which an insulating resin layer is formed on the surface of the silicon substrate 3 on which the through-hole 3a is formed and on the inner wall of the through-hole 3a by coating or sputtering.

(3) Next, the through hole 3a of the silicon substrate 3
Is filled with a copper powder paste, and a heat treatment is performed in dry nitrogen (N ₂ ) (for example, about 1100 ° C.) to complete the conductor portion 5 (that is, the through hole 3a filled with the copper powder). afterwards,
Polishing treatment is performed on both surfaces of the substrate (FIG. 4). Note that an insulating layer (not shown) is provided between the silicon portion of the silicon substrate 3 and the conductor portion 5. Silicon oxide, polyimide, benzocyclobutene (B
CB) can be adopted. The insulating layer may be provided at least on the inner wall of the through hole, or provided on the inner wall of the through hole and the surface of the substrate.In the former case, the conductor is completed after the formation of the insulating layer, and then the surface is polished. Will do.

(4) Next, desired circuit patterns 7 are formed on both surfaces of the silicon substrate 3 (FIG. 5). The circuit pattern 7 may be formed by forming a metal layer by sputtering of Al, Cr / Cu, TiW / Cu or the like, and then performing etching. The circuit pattern 7 and the conductor portion 5 are appropriately connected. It goes without saying that a circuit pattern may be formed only on one side of the substrate. After the formation of the through-hole, an insulating layer is formed on the surface of the silicon substrate and the inner wall of the through-hole with a BCB-based resin, and then the conductor and the plane conductor layer (circuit pattern) are formed by electroless plating of copper or the like and electrolytic plating.
Can also be adopted.

When using a silicon substrate on which a memory element or the like (not shown) is formed, the following forming method is used. That is, a memory element is formed on a silicon substrate (wafer) on which the conductor section 5 is formed. In this case, the circuit pattern 7 is formed simultaneously with the formation of the memory element by a wafer process, and conducts with the conductor section. (5) Next, a film (thin layered connection body) 9 having the following configuration is prepared. That is, the other surface (adhesive surface) of a polyimide-based (for example, polyolefin) thermoplastic adhesive film (sheet) 9 having a copper foil (rolled copper foil or electrolytic copper foil) 11 on one surface is laser-processed (preferably). Is C
A plurality of holes (vias) 9a having a desired shape and dimensions are formed by O ₂ , excimer, etc.). At this time, a hole 9a is formed so that the copper foil 11 is exposed at the bottom. Using the copper foil 11 as an electrode, the hole 9a is filled with a low melting point metal, for example, a metal having a melting point of 360 ° C. or less (for example, a tin-lead eutectic alloy (solder)) by electroplating to form a conductor. The film 9 formed with the portion 13 is prepared (FIG. 6). In addition, as a material of the film (connecting body) 9, glass can be used instead of the flexible resin film. In this case, the softening point is set to 500 so as to correspond to the conductor.
Glass having a coefficient of thermal expansion of 2 × 10 ^{−6 to} 5 × 10 ⁻⁶ at or below ° C is desirable.

(6) Next, the film (connector) 9
Is positioned so that the copper foil (layer) 11 faces outward (in other words, does not face the silicon substrate 3), and is bonded to the corresponding surface of the silicon substrate 3 by heating. (FIG. 7). At this time, alignment (adhesion) is performed by forming an alignment mark on the copper foil 11.
Accuracy can be improved.

(7) Next, the copper foil layers 11 on the upper and lower surfaces are removed (for example, by an etching method) to expose the via end surfaces. At this time, a substrate (3: 3) having a circuit pattern 7 on both sides, which is formed by a series of steps described with reference to FIGS. 2 to 5, is separately prepared (FIG. 8). (8) Then, these substrates (3: 9, 3, 9: 3) are overlapped and bonded to complete a multilayer substrate (FIG. 9). Similarly, a multilayer substrate having a desired number of layers can be formed.

As described above, the silicon multi-layer substrate 1 of the present embodiment comprises a silicon substrate 3 in which a conductor portion 5 (for example, a via filled with a conductor member such as copper or aluminum) is formed through. Since the multi-layer substrate is formed by laminating and integrating with a film (connector) 9 interposed therebetween, a very high-density wiring structure can be realized. Further, since the thickness of the silicon substrate alone can be made extremely thin, for example, about 50 to 100 μm, a very small and high-density (silicon multilayer substrate) semiconductor device as a whole can be formed.

Further, since silicon itself, which is a material forming the base of the silicon substrate, has a high thermal conductivity, there is an advantage that the substrate can have low thermal resistance (high heat dissipation). Incidentally, with respect to the silicon substrate (layer) located inside, an electronic device function section (not shown) can be formed in and / or on the surface of the substrate. Specifically, one or more elements such as a capacitor, a resistor, and an inductor can be formed, or a memory functional element or a logic functional element can be formed.

FIG. 10 is a sectional view showing an embodiment in which a capacitor is provided on a silicon substrate. First, a plurality of through holes 3a are formed in the silicon substrate 3 by a method similar to the method shown in FIGS.
a is filled with a copper powder paste and heat-treated to form a conductor portion 5. After polishing both upper and lower surfaces of the silicon substrate 3, a circuit pattern 7 having an appropriate shape is formed on both upper and lower surfaces of the silicon substrate 3. A part of the circuit pattern 7 is electrically connected to the conductor 5.

Next, a high dielectric constant 15 is formed on the circuit pattern 7 on the upper surface of the silicon substrate 3 by sputtering a high dielectric constant titanate such as strontium titanate or lead titanate, or perovskite. , Capacitor 2
0 and 21 are formed. In this case, the circuit pattern 7 is formed by sputtering Al, TiW, Cr—Cu or the like as described above. In these examples, the lower electrodes of the capacitors 20 and 21 are formed. Become.

An upper electrode 17 is formed on the upper surface of the capacitor 20 by sputtering of Al, TiW, Cr-Cu or the like, and one end of the upper electrode 17 is connected to the conductor 5 so that the upper electrode 17 17 and a lower electrode (circuit pattern) 7 connected to another conductor portion.
Above and below. On the other hand, the upper electrode 21 is also formed on the upper surface of the capacitor 21 by sputtering Al, TiW, Cr—Cu, or the like, but this upper electrode 21 is not connected to the conductor portion 5 and An upper layer to be laminated, that is, a circuit pattern (not shown) formed on the lower surface of the resin film 9 is connected.

In any case, after lamination, the laminated body is the same as that shown in FIG. 9 except that a capacitor is provided inside. 11 to 13 show an embodiment in which a semiconductor chip such as a memory is built in a film portion. FIG. 11 shows a state before lamination, FIG. 12 shows a state after lamination, and FIG. It is sectional drawing which shows the state which laminated | stacked the silicon substrate (including the capacitor), respectively.

In this embodiment, first, a semiconductor chip 23 such as a memory is mounted between the upper and lower resin films 9, stacked between the two resin films 9, and incorporated. In the case where the film is built between the two resin films 9 as described above,
A thin semiconductor chip is used. Then, as shown in FIG. 13, a silicon substrate as shown in FIG. 5 (two layers in the example shown) is laminated on the upper surface of the laminate, and the silicon substrate 3 and the film 9 are disposed on the lower surface. Then, the silicon substrate 3 on which the capacitors 20 and 21 are mounted as described with reference to FIG.

As described above, a mode having a high-density function structure in which an electronic device function section (element) is built in the silicon multilayer substrate is also conceivable. In this specification, this is simply referred to as a silicon multilayer substrate. Instead, the term "semiconductor device", which is considered more accurate, is used. In the case of such a high-density functional structure, since it is basically formed from a so-called silicon-on-silicon structure, the difference in the coefficient of thermal expansion does not matter, and therefore, the semiconductor device as a whole has a thermal disadvantage. It is possible to enjoy an excellent effect that no or little (high reliability) occurs.

[0023]

As described above, according to the present invention, dimensional stability and reliability of component connection are extremely excellent,
It is possible to provide an innovative, rational, and economical semiconductor device capable of realizing high-density wiring and the like and including and incorporating various functional units or functional elements (electronic device functional units), and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional side view of a silicon multilayer substrate according to an embodiment of the present invention.

FIG. 2 is a sectional side view showing a silicon substrate alone.

FIG. 3 is a cross-sectional side view of a silicon substrate having a through hole formed therein.

FIG. 4 is a cross-sectional side view of a silicon substrate having a through hole filled with copper powder.

FIG. 5 is a sectional side view of a silicon substrate on which a circuit pattern is formed.

FIG. 6 is a cross-sectional side view showing a connector film and a silicon substrate.

FIG. 7 is a cross-sectional side view showing a bonding state between a connection body film and a silicon substrate.

8 is a cross-sectional side view showing a state in which another silicon substrate is arranged vertically with respect to the silicon substrate of FIG.

FIG. 9 is a cross-sectional side view of the completed silicon multilayer substrate.

FIG. 10 is a sectional view showing an embodiment in which a capacitor is provided on a silicon substrate.

FIG. 11 is a sectional view showing a state before lamination in an embodiment in which a semiconductor chip such as a memory is built in a film portion.

FIG. 12 is a cross-sectional view showing a state after lamination in an embodiment in which a semiconductor chip such as a memory is built in a film portion.

FIG. 13 is a cross-sectional view showing a state in which a silicon substrate is further laminated on both upper and lower surfaces of the laminate shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon multilayer substrate 3 ... Silicon substrate 3a ... Through-hole 5, 13 ... Conductor part 7 ... Circuit pattern 9 ... (connecting body) film 9a ... Hole 11 ... Copper foil

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E346 AA12 AA15 AA35 AA43 BB01 BB20 CC16 CC18 DD03 DD05 DD07 EE01 EE06 EE08 FF06 FF14 FF18 FF35 FF36 FF45 GG15 GG19 GG28 HH17 HH25

Claims (9)

[Claims] 1. A semiconductor device comprising: a plurality of silicon substrates having a conductor portion penetrating from one surface side to the other surface side; and a conductor portion interposed between the silicon substrates and penetrating from one surface side to the other surface side. A conductor portion of the silicon substrate and a conductor portion of another silicon substrate, which are integrated with each other, are electrically connected via the conductor portion of the connection body. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein an electronic device function unit is formed on at least one silicon substrate. 3. The semiconductor device according to claim 1, wherein the connection body is formed of a thin resin substrate. 4. The semiconductor device according to claim 1, wherein the connection body is made of a thin glass substrate. 5. A step of forming a conductor portion penetrating from one surface side to the other surface side on a silicon substrate; a step of forming a conductor portion penetrating from one surface side to the other surface side on a connection body; A connecting body is interposed between the substrates, and a silicon substrate and a conductive part of another silicon substrate are electrically connected to each other through a conductive part of the connecting body. And a step of integrating a connection body. 6. The manufacturing method according to claim 5, wherein the step of forming the conductor portion on the silicon substrate includes forming a through hole in the silicon substrate and filling the through hole with a conductor member. 7. The step of forming a conductor portion on the connection body,
6. The method according to claim 5, further comprising: forming a through hole in the thin resin base material and filling the through hole with a conductor member. 8. The step of forming a conductor portion on the connection body,
6. The method according to claim 5, further comprising: forming a through hole in the thin glass substrate, and filling the through hole with a conductive member. 9. The method according to claim 5, further comprising the step of forming an electronic device function part on a silicon substrate.