JP2000292362A - Wafer inspection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display correlation between a defect and a circuit pattern. SOLUTION: A wafer, test object, is inspected by a wafer defect inspection part 11, and coordinate value data S11 are outputted from the wafer defect inspection part 11. The coordinate value data S11 are inputted into an image data formation part 12, and graphics showing a defect of the wafer are formed relative to each chip to form image data S12 by the image data formation part 12. The image data S12 are inputted into a display part 13, and a first image corresponding to the image data S12 is displayed on the display part 13, overlapping with a part corresponding to the coordinate value data S11 in a second image showing a circuit pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting defects on a surface to be inspected of a wafer having a circuit pattern formed thereon, for example, by CAD (Compu
The present invention relates to a wafer inspection apparatus that displays data using an apparatus or the like.

[0002]

2. Description of the Related Art FIG. 2 is a schematic diagram showing an example of a conventional wafer inspection apparatus. This wafer inspection apparatus has a wafer defect inspection unit 1 with a pattern. The patterned wafer defect inspection unit 1 captures, for each chip, an image of the inspection surface of the wafer on which a circuit pattern is formed for each chip based on the wiring information of the circuit, and detects a defect existing on the inspection surface. Has a function of generating and outputting coordinate value data S1 representing the position and size of each chip. A wafer map display unit 2 is connected to the output side of the patterned wafer defect inspection unit 1. The wafer map display unit 2
The coordinate value data S1 is input, and the position and size of a defect existing on the inspection surface of each chip are displayed using a wafer map.

In this wafer inspection apparatus, a wafer to be inspected is inspected by a wafer defect inspection unit 1, and coordinate value data S1 is output from the wafer defect inspection unit 1. The coordinate value data S1 is input to the wafer map display unit 2, and a wafer map corresponding to the coordinate value data S1 is displayed on the wafer map display unit 2. FIG. 3 is a schematic diagram showing an example of a display screen on the wafer map display unit 2 in FIG.

[0004] On this display screen, the number of defects is indicated by a numeral at a corresponding location, and the shape of the defect is indicated by, for example, a mark "O". Then, in this wafer inspection apparatus, the defect management of the defect distribution, the number of defects, and the size of the defects in the wafer map of FIG. 3 is performed visually by a person in charge, and the defect analysis is performed using a sampling method.

[0005]

However, the conventional wafer inspection apparatus shown in FIG. 2 has the following problems (i) and (ii). (I) In the wafer inspection apparatus of FIG. 2, only a defect is displayed on the display screen, and it is impossible to perform a defect analysis in consideration of a correlation between the defect and the circuit pattern.

(Ii) The wafer inspection apparatus shown in FIG. 2 cannot express a correlation between a circuit pattern, a defect position and a defect size. Therefore, for example, when two patterns are short-circuited, it is impossible to determine whether or not a fatal defect occurs.

[0007]

According to a first aspect of the present invention, a circuit pattern is formed for each chip in a wafer inspection apparatus based on circuit wiring information. Wafer inspection means for capturing an image of the inspected surface of the wafer for each of the chips, and generating and outputting coordinate value data representing the position and size of a defect existing on the inspected surface for each of the chips Image data generating means for generating, for each of the chips, a graphic representing each of the defects based on each of the coordinate value data and generating image data corresponding to the graphic; Display means for displaying a first image corresponding to data and a portion corresponding to the coordinate value data of a second image representing a circuit pattern based on the wiring information on a common screen in a superimposed manner. I have.

By adopting such a configuration, the wafer is subjected to the wafer inspection means, an image of the inspected surface of the wafer is taken in for each chip, and the position and size of the defect are indicated from the wafer inspection means. The coordinate value data is output. The coordinate value data is input to the image data generating means, and the image data generating means outputs image data. The image data is input to the display means, and a first image corresponding to the image data and a portion corresponding to the coordinate value data of the second image representing the circuit pattern are displayed in an overlapping manner.

[0009]

FIG. 1 is a schematic configuration diagram of a wafer inspection apparatus showing an embodiment of the present invention. This wafer inspection apparatus has wafer inspection means (for example, a wafer defect inspection unit with a pattern) 11. The patterned wafer defect inspection unit 11 is, for example, a scanning electron microscope (Scanning Ele
ctronic Microscope (hereinafter referred to as “SEM”), etc., and captures an image of a surface to be inspected of a wafer on which a circuit pattern is formed for each chip based on circuit wiring information for each of the chips. It has a function of generating and outputting coordinate value data S11 representing the position and size of the defect existing above for each chip. An image data generating means (for example, an image data generating unit) 12 is connected to the output side of the patterned wafer defect inspection unit 11. The image data generating unit 12 is formed of, for example, a CAD device, and generates a graphic representing each defect for each chip based on each coordinate value data S11 to generate image data S12. A display unit (for example, a display unit) 13 is connected to an output side of the image data generation unit 12. The display unit 13 is, for example, a CAD
And image data S12. The coordinate value data of the first image corresponding to the image data S12 and the second image representing the circuit pattern based on the wiring information.
It has a function of displaying a portion corresponding to S11 on a common screen in a superimposed manner.

Next, the operation of FIG. 1 will be described. In this wafer inspection apparatus, a wafer to be inspected is inspected by a wafer defect inspection unit 11, and coordinate value data S11 is output from the wafer defect inspection unit 11. The coordinate value data S11 is input to the image data generation unit 12, and a figure (for example, a CAD figure) representing a defect of the wafer is created for each chip by the image data generation unit 12, and the image data S12 is generated. Image data S1
2 is input to the display unit 13 and the image data S1 is displayed on the display unit 13.
2 is superimposed and displayed on a portion corresponding to the coordinate value data S11 in the second image representing the circuit pattern.

FIG. 4 is a schematic diagram showing an example of a display screen on the display unit 13 in FIG. On this display screen, it is displayed that the circuit pattern P1 and the circuit pattern P2 are short-circuited by the foreign matter Q, and the short-circuited portion is surrounded by a circle. Therefore, the correlation between the fine circuit pattern and the defect is displayed at the level of the accuracy of the semiconductor manufacturing apparatus. In addition, if the circuit pattern (not shown) formed in the process after the formation of the circuit patterns P1 and P2 is superimposed on the display screen, the influence of the foreign matter Q is predicted. For example, the presence of the foreign matter Q is expected to break the pattern formed thereon. Therefore, if the wafer is inspected using the wafer inspection apparatus during the wafer manufacturing process, it is determined whether or not the next step of the manufacturing operation is possible.

As described above, in this embodiment, the correlation between the circuit patterns P1 and P2 and the position and size of the foreign matter Q is displayed on the display screen. When short-circuiting occurs, it becomes possible to determine whether or not a fatal defect occurs. Then, when a fatal defect is determined, the manufacturing operation in the next step is not performed, so that the yield of the wafer is improved and the efficient manufacturing operation is performed.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) In addition to the SEM, the patterned wafer defect inspection unit 11 may be any device as long as it captures an image of the inspection surface of the wafer and outputs defect coordinate data S11.

(B) The image data generating unit 12 is not limited to a CAD device, but may be any device that generates image data S12.
Any device may be used. (C) The display unit 13 is not limited to the CAD device, and may be any display device that displays the first image and the portion of the second image corresponding to the coordinate value data S11 on the common screen. A device is sufficient.

[0015]

As described in detail above, according to the first aspect of the present invention, the correlation between a plurality of circuit patterns and the position and size of a defect is displayed on the display means. When the circuit pattern of the book is short-circuited through a foreign substance, it is possible to determine whether or not a fatal defect occurs.
If the defect is fatal, the next step of the manufacturing operation is not performed, so that the yield of the wafer can be improved and the efficient manufacturing operation can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a wafer inspection apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional wafer inspection apparatus.

FIG. 3 is a schematic diagram of a display screen in FIG. 2;

FIG. 4 is a schematic diagram of a display screen in FIG. 1;

[Explanation of symbols]

11 Wafer with pattern (defect inspection part wafer inspection means) 12 Image data generation part (image data generation means) 13 Display part (display means)

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Claims (1)

[Claims] An image of a surface to be inspected of a wafer on which a circuit pattern is formed for each chip based on circuit wiring information is fetched for each chip, and the position and size of a defect present on the surface to be inspected. A wafer inspection means for generating and outputting coordinate value data representing the size of each chip, and generating a figure representing each defect for each of the chips based on the respective coordinate value data to correspond to the figure. Image data generating means for generating image data; and the coordinate value data of the first image corresponding to the image data and the second image representing a circuit pattern based on the wiring information. And a display means for displaying a portion corresponding to (a) on a common screen in a superimposed manner.