JP2000278120A - DLL circuit having mislock prevention function - Google Patents

Abstract

(57) [Problem] In a conventional DLL circuit, since it is a value designed based on a delay time of a normally locked state, it is possible to prevent the DLL circuit from being locked in a mislocked state (a state in which it is not normally locked). Since the phase difference is not determined in the delay time from input to output, there is a problem when using as a clock generation circuit. Therefore, in general, when a DLL circuit is used, there is a need for a mislock prevention circuit that does not cause the DLL circuit to be in a mislocked state, or that returns to a locked state when the DLL circuit falls into a mislocked state. SOLUTION: A mask circuit (4) for limiting the input of an external clock (CKext) is used for an input portion of a voltage control delay circuit (3) used in a DLL circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer (MCU) and a digital signal processor (DS).
The present invention relates to a DLL (Delay Locked Loop) circuit that functions to improve the operation speed of an LSI such as P).

[0002]

2. Description of the Related Art In recent years, in semiconductor integrated circuits, there has been a demand for miniaturization of the structure, improvement of the operation speed of LSI, and further improvement of processing performance.

A conventional technique will be described below with reference to FIGS.

FIG. 10 shows a basic Delay Locked Loop.
(Hereinafter abbreviated as DLL) circuit. Phase comparator 101
An inverted signal of a reference external clock (CKext) is inputted to one input terminal of a PC (hereinafter abbreviated as PC), and a voltage control delay circuit 103 (hereinafter abbreviated as VCD) is inputted to another input terminal.
And the delayed clock (CKout) is input to the external clock (CKext).

The VCD 103 is formed of a circuit in which a number of delay circuits are connected in cascade, and the delay time of this delay circuit changes according to an input control voltage.

As described above, when the delay time changes according to the input control voltage, the VCD 103 changes the propagation time of the delay clock (CKout) according to the control voltage, and changes the phase of the delay clock (CKout). I can do it.

Here, the PC 101 operates with a delay clock (C
Assuming that Kout) is delayed in phase from the external clock (CKext), a high level is output only during the period in which the phase is delayed.

The high-level pulse is integrated by a low-pass filter 102 (hereinafter abbreviated as LPF) to a DC level. The LPF is generally composed of a resistor and a capacitor, and a lag-type or lag-lead-type passive low-pass filter 102 is used.

As described above, the output level of the LPF 102 is higher than in the previous state. As a result, the propagation time of the VCD 103 becomes shorter than the previous propagation time, and the delay clock (CK)
The phase of (out) is advanced.

If the phase of the delayed clock (CKout) is still behind the phase of the external clock (CKext), the same process as before is followed, and the phase is further advanced.

As a result, on the contrary, the delay clock (CKout)
If the phase is too advanced from the external clock (CKext), the PC 101 outputs a low level for the same period as the phase difference, contrary to the previous case.

The low-level pulse is integrated by the LPF 102 to a DC level. Then, the output level of the LPF 102 becomes lower than in the previous state. As a result, VCD1
In 03, the propagation time is longer than the previous propagation time, and the phase of the delay clock (CKout) is delayed.

As described above, several times of the delayed clock (CK)
out) and the external clock (CKext) are compared, and the loop operates so as to eliminate the phase error constantly. Finally, the phase difference between the delay clock (CKout) and the external clock (CKext) becomes zero.

As a result, the output of the PC 101 becomes a high impedance state, and the output level of the LPF 102 maintains the same level as the previous state.
3 also maintains the same propagation time.

The above state is a state in which the DLL circuit is functioning normally, and is called a state in which the DLL circuit is locked.

Here, the DLL circuit will be described.

Assuming that the number of delay circuits constituting the VCD 103 is N, the delay time (Tt) from the input to the output of the VCD 103 when the DLL circuit is locked.
Since d) is kept constant, the delay time Td per delay circuit is Td = Ttd / N, where Ttd is the delay clock (CKout) and the external clock (CKex).
t) depends on the comparison cycle, and the comparison cycle is determined by the external clock (C
Ttd is the same as the half cycle (or one cycle) of the external clock (CKext) if it is performed in a half cycle (or one cycle) of Kext).

If an output clock (CKMO), which is a second delayed clock signal, is taken from an arbitrary Mth of the delay circuit constituting the VCD 103, the second delayed clock (CKMO) from the Mth is The phase difference with respect to the external clock (CKext) is Ttd × M / N,
An output clock having characteristics synchronized with the external clock (CKext) can be generated.

With this configuration, a clock output having an arbitrary phase difference with respect to an external clock (CKext) can be generated as an internal clock, and a polyphase clock or the like can be easily generated.

Further, by combining clock outputs having an arbitrary phase difference, an external clock (CKex
It is also possible to generate frequencies higher than t).

As described above, the DLL circuit is a circuit that can be used for application circuits such as clock generation in the LSI.

Next, a mislock circuit of the DLL circuit will be described. The above-mentioned arbitrary phase difference is usually a value designed from the delay time (Ttd) from input to output of the VCD 103 in a normally locked state. In the delay time (Ttd) from the input to the output in the above, the phase difference is not determined, so that there is a problem when used as a clock generation circuit.

Therefore, in general, when a DLL circuit is used, it is necessary to provide a mislock prevention circuit that does not cause the DLL circuit to be in a mislocked state, or restores the locked state when the DLL circuit enters a mislocked state.

Next, mislock, which is a problem of the DLL circuit, will be described.

FIG. 11 shows D in a normally locked state.
4 shows operation waveforms of the LL circuit. Since the comparison cycle is performed in a half cycle of the external clock (CKext), VCD
The delay time (Ttd) from the input to the output of 103 is the same as the half cycle of the external clock (CKext).

FIG. 12 shows operation waveforms of the DLL circuit in the state of mislock.

The delay time (Ttd) from the input to the output of the VCD 103 is the same as 1.5 cycles of the external clock (CKext), and the delay time of the VCD 103 is three times as long as the normally locked state. It's time.

However, the delayed clock (CKou)
t) and the external clock (CKext) are in phase with each other, and the PC 101 does not operate because there is no phase difference.
The LL circuit is not normal but is locked (it is considered normal without a phase difference and locked).

As described above, a locked state different from the normally locked state shown in FIG. 11 is called a mislocked state.

In the normally locked state, only one waveform exists between the input and output of the VCD 103 (Ttd) (see FIG. 11). In the mislocked state, a plurality of waveforms exist (see FIG. 12). And multiple waveforms are VCD1
In other words, it can be rephrased as a state where the data is completely accumulated between the input and the output of No. 03.

Since the number of stored waveforms depends on the number N of delay circuits of the VCD 103, the delay time between input and output is determined when the comparison cycle is set to a half cycle of the external clock (CKext). 3 times, 5 times, 7 times, ~
An odd-numbered delay time of N / 2 times can be present (normal time is in the normal lock state at the time of 1 time, and all other times are in the mislock state; see FIG. 16).

Further, the comparison cycle is set to an external clock (CKex
If the operation is performed in one cycle of t), it is doubled, quadrupled, and 6 times.
The delay time can be an even multiple of N times or N times.

FIG. 13 shows a conventional mislock prevention circuit for preventing the misclock.

As shown in FIGS. 13 and 16, in the case of the PC 101 comparing the rising edges, the VCD 10 is output at the falling timing of the external clock (CKext).
Four points between input 3 and output 3 (CK1D,
CK2D, CK3D, and CK4D), and the operation of raising the output of the PC 101 to a high level is performed when a low level state is detected in any one place.

FIG. 14 shows operation waveforms of the mislock prevention circuit in the normally locked state.

In the normal lock state, four detection points (CK1D, CK1D,
CK2D, CK3D, CK4D)
This mislock prevention circuit does not operate, and has no effect on the DLL circuit (see model 1 in FIG. 16).

FIG. 15 shows the operation waveforms of the unlocked circuit in the unlocked state. In the unlocked state, since a plurality of waveforms are accumulated between the input and the output of the VCD 103, the four detection points are in a state where the low level and the high level are mixed.

Then, the PON signal goes low at the falling timing of the external clock (CKext),
When the MOS1 is turned on, the operation of raising the output of the PC 101 to a high level is performed.

Then, the output level of the LPF 102 also becomes high. As a result, the propagation time of the VCD 103 becomes shorter than the previous propagation time, and the phase of the delay clock (CKout) is advanced.

The plurality of waveforms stored between the input and output of the VCD 103 are output as the delay time becomes shorter, and the phase difference Ttd between the delay clock (CKout) and the external clock (CKext) is output. However, within a half cycle, the operation of the mislock prevention circuit stops, the feedback control is normally performed by the output of the PC 101, and the normal lock state is drawn (Mod in FIG. 16).
e1).

FIG. 16 shows an operation state from input to output of the VCD 103 in the locked state of the DLL circuit.

As shown in FIG. 16, from Mode 1 to Mo
The operation states of seven modes of de15 are shown.

In this operation state, since the comparison cycle is performed in a half cycle of the external clock (CKext), an odd number of modes are provided (see FIG. 16. Mode 1 has one half cycle, and Mode 3 has a half cycle). Are three), and when the comparison cycle is performed in one cycle, an even number of modes are provided (not shown).

In the conventional DLL circuit, since the design is performed assuming the state of Mode 1, it is called a state in which Mode 1 is normally locked, and a state in which Mode 3 or more is mislocked.

At this time, in Mode 1, a half cycle has the same length as the phase difference Ttd between the delayed clock (CKout) and the external clock (CKext).
Locked. However, there is a problem that locking occurs even when an odd number of half-cycles of 3 or more are included in the same length as the phase difference Ttd (mode 3 or more).

If four detection points CK1D to CK4D in the conventional mislock prevention circuit of FIG. 13 are arranged between the input and output of the VCD 103 as shown in FIG. Since all the points are at the high level, it is determined that the state is the same as in the mode 1 (normal state), and it is understood that the conventional mislock prevention circuit has not been able to detect the state (other than the mode 1 is not in a normal state).

The method of arranging the four detection points between the input and the output of the VCD 103 is usually performed at regular intervals in order to improve the sensitivity of mislock (low-level state in FIG. 16) detection. Are not arranged, but are arranged in a place where the level tends to be relatively low in the mislock state.

However, in the arrangement of FIG.
It is delicate whether or not 13 can detect the mislock state.

Therefore, in order to prevent a mislock state after Mode 15, it is necessary to increase the number of detection points arranged between the input and the output of the VCD 103, thereby increasing the circuit scale of the mislock prevention circuit. There was a need.

Further, the maximum value of the number of modes in the mislock state depends on the number N of delay circuits constituting the VCD 103, and it is considered that the number of modes is theoretically up to mode (N / 2). In order to detect a mislock state, it is necessary to set the number of detection points arranged between the input and output of the VCD 103 to (N / 2).

This is because if the number N of delay circuits is increased,
The circuit scale of the mislock prevention circuit becomes large, which causes a cost problem. Unless the number N of the delay circuits is increased, it becomes impossible to generate a minute phase difference, and there is a functional problem.

As another method of avoiding the mislock state, a method of limiting the maximum delay time of the delay circuit can be considered. However, in a normal delay circuit, the control voltage (VC
D) When 3 becomes the ground potential, the transistor is cut off, so that the transistor is stopped.

That is, the maximum delay time of the delay circuit becomes infinite, and the maximum value of the number of modes in the mislock state is also VCD
Mo depending on the number N of delay circuits constituting
There will be up to de (N / 2).

Therefore, if the maximum delay time of the delay circuit is limited, the delay time (T
td) and the external clock (CK)
ext) at the frequency (FCKext), the maximum number of modes in the mislock state is 2 × (TtdMAX) × (FC
Kext). Therefore, the conventional mislock prevention circuit can be used without increasing the number of detection points arranged between the input and output of the VCD 103.

The problem in this case is that in the method of limiting the maximum delay time of the delay circuit, there is a difference whether a circuit is added to the delay circuit or a circuit is added to the control circuit. From the point of increase and the limitation of the delay time of the delay circuit, there may be problems such as restrictions on applications due to reduction of the control range and reduction of operation margin.

[0056]

In recent years, in semiconductor integrated circuits, there has been a demand for miniaturization of the structure, improvement of the operation speed of the LSI, and further improvement of the processing performance. As a result, there is an increasing demand for faster operation clocks for memories and CPUs.

From this, the memory, CPU, DS,
It is required to improve the reliability of the DLL circuit used for the P and the like. In the conventional DLL circuit, the value is designed based on the delay time (Ttd) in a normally locked state. , The delay time from input to output (T
In the case of td), there is a problem when used as a clock generation circuit because the phase difference is not determined.

Therefore, in general, when a DLL circuit is used, it is necessary to provide a mislock prevention circuit for preventing the DLL circuit from being in a mislocked state or for returning to the locked state when the DLL circuit is in a mislocked state.

In view of the above, the present invention provides a D having a highly reliable mislock prevention function that does not cause mislock.
An LL circuit is provided.

[0060]

According to the present invention, there is provided a DLL circuit having a mislock prevention function, comprising: a voltage control delay circuit for outputting a first delay clock signal having a predetermined delay time with respect to a reference clock signal; The voltage control delay circuit has a delay time controlled by a control voltage, outputs a second delay clock signal having a delay time shorter than the delay time, and outputs a second delay clock signal between the first delay clock signal and the reference clock signal. A phase comparator that outputs an error signal corresponding to the phase difference, control voltage generation means that generates the control voltage that controls a delay time of the voltage control delay circuit in accordance with the error signal, and the second delay clock signal And a mask circuit that restricts passage of the reference clock signal to the voltage control delay circuit in accordance with

The mask circuit according to the present invention further comprises an RS flip-flop for detecting a rising (falling) of the reference clock signal and a rising (falling) of the second delayed clock signal; Output and the reference clock signal,
According to the output signal of the flip-flop, the input reference clock signal is directly output and input to the voltage control delay circuit, or a high-level or low-level fixed signal is output to the voltage control delay circuit. And a circuit that operates so as not to pass the input reference clock signal by inputting the same.

Further, the mask circuit of the present invention includes a delay clock detecting circuit for detecting a rise (fall) of the second delay clock signal and outputting a pulse, and a rise (fall) of the reference clock signal. And an RS flip-flop for detecting a rising (falling) edge of an output pulse of the delay clock detection circuit; an output of the RS flip-flop and the reference clock signal being input, and input according to an output signal of the RS flip-flop. The reference clock signal is output as it is and input to the voltage control delay circuit, or a high or low level fixed signal is output and input to the voltage control delay circuit, and the input reference clock signal is input to the voltage control delay circuit. And a circuit that operates so as not to pass through.

Further, the mask circuit of the present invention receives the second delayed clock signal, and has one edge synchronized with the reference clock signal and the other edge synchronized with the second clock signal.
And a DLL circuit that outputs a clock pulse synchronized with the delayed clock signal and inputs the clock pulse to the voltage control delay circuit.

Further, the mask circuit of the present invention receives the second delayed clock signal, and sets a rising edge (falling edge) in synchronization with a rising edge (falling edge) of the input reference clock signal. Generates an output pulse composed of a falling (rising) edge synchronized with a rising (falling) edge of the input second delayed clock signal, and inputs the generated output pulse to the voltage control delay circuit. DLL circuit.

The mask circuit of the present invention further comprises: the reference clock signal flip-flop for receiving the second delayed clock signal and detecting a rising (falling) edge of the input reference clock signal; A second delayed clock signal flip-flop for detecting a rising (falling) edge of the input second delayed clock signal, wherein the reference clock signal flip-flop is connected to the input reference clock signal. The second delayed clock flip-flop detects the rising (falling) edge of the input second delayed clock signal and detects the rising (falling) edge of the reference clock. Reset the output of the signal flip-flop, and The output pulse of Ritsupufuroppu a DLL circuit for inputting to the voltage controlled delay circuit.

Further, the reference clock signal of the present invention is:
A DLL circuit that is a clock signal obtained by dividing an external clock signal by a half frequency divider, wherein the phase comparator determines a phase difference between each rising edge between the first delayed clock signal and the reference clock signal. A DLL circuit for comparison, wherein the voltage control delay circuit has a configuration in which a plurality of delay circuits are cascaded, and the second delay clock signal is output from any one of the plurality of delay circuits. Is a DLL circuit.

The mask circuit of the present invention masks the reference clock signal by holding its output at a high level at the rising edge of the reference clock signal, and outputs the high level output of the mask circuit to the mask circuit. A DLL circuit that propagates through the voltage control delay circuit and releases the mask when the second delayed clock signal goes high, and passes the reference clock signal.

[0068]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiments described here. The following embodiments can be variously modified without departing from the object of the invention.

An embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG.

FIG. 1 shows a basic DLL circuit diagram of the present invention.

According to the present invention, the comparison cycle is set to an external clock (CK).
ext), so that the duty of the external clock (CKext) (the ratio of the high level to the low level in one cycle) is 50%. 1 frequency divider 5 is inserted.

The output (CK2) of the frequency divider 5 is input as a reference clock signal to a mask circuit 4 having a function of preventing mislock, and the output of the mask circuit 4 is input to a voltage control delay circuit (VCD) 3. You.

Since the phase comparator 1 (hereinafter referred to as PC) is of a type that compares only the rising edge of the input clock, the rising edge of the input clock input to the voltage control delay circuit (VCD) 3 is used. Output clock (CKout) and output (CK
The inverted signal (CKref) of 2) is compared, and an error signal (Verr) corresponding to the phase difference between the two is output.

This error signal (Verr) is integrated by a low-pass filter (LPF) 2 which is a control voltage generating means.
A control signal (VcoNt) for controlling the delay time of the voltage control delay circuit (VCD) 3 is output.

By the above-described control called a feedback loop, the delay time of the voltage control delay circuit (VCD) 3 is maintained to be a half cycle of the input clock, and the DLL is controlled.
It can function as a circuit.

FIG. 2 shows an embodiment of a mask circuit 4 having a function of preventing mislock used in the present invention.

As shown in FIGS. 1 and 2, the output (CK2) of the half frequency divider 5 and the voltage control delay circuit (VCD) 3
Of the second delay clock (CK
MO) is input to an RS flip-flop 23 composed of a two-input NOR, and the output (RS
O) and a signal (CKiN) obtained by inverting the output of the two-input NOR which receives the output (CK2) of the half frequency divider 5 as an output of the mask circuit 4.

Since the PC 1 is of a type that compares only the rising edge of the input clock, the rising edge of the output (CK 2) of the half frequency divider 5 is used as the RS flip-flop in the mask circuit 4. Is detected,
Output of RS flip-flop (RSO) (not shown)
Becomes a high level, and the output (CKiN) of the mask circuit 4
Holds a high level regardless of the signal of the output (CK2) of the half frequency divider 5.

The high level output (CKiN) of the mask circuit 4 is input to the voltage control delay circuit (VCD) 3 and propagates through the voltage control delay circuit (VCD) 3. From the output terminal, the second delay clock (CKM
O) and returns to the mask circuit 4 (see FIG. 1).

The returned second delayed clock (CK)
When MO) goes high, the output (RSO) of the RS flip-flop in the mask circuit 4 is reset to low.

When the output (RSO) of the RS flip-flop goes low, the output (CK2) of the half frequency divider 5 passes through the output (CKiN) of the mask circuit 4 and is output.

Therefore, the output (CKiN) of the mask circuit 4 which has become high level is input to the voltage control delay circuit (VCD) 3 and propagates through the voltage control delay circuit (VCD) 3 and From the output terminal of the second delay clock (C
(KMO), the output of the half frequency divider 5 (CK2) is controlled by the masking circuit 4 while the output (CK2) of the half frequency divider 5 is voltage controlled while returning to the output cutoff mask circuit 4 as KMO). Mask without passing through the delay circuit (VCD) 3.

By this operation, the voltage control delay circuit (VC
D) Since only one waveform is input between the input of 3 and the output terminal on the way to output the second delay clock (CKMO), a plurality of mislocked waveforms are output from the voltage-controlled delay circuit ( VCD) 3 can be avoided.

When the comparison cycle of the phase comparator of the DLL circuit is performed by a half cycle of the reference clock signal, the position of the output terminal in the middle of extracting the second delay clock (CKMO) is as shown in FIG. Since it is only necessary to avoid Mode 3 and later in the operation state of VCD 3 in the middle (see FIG. 16; Modes 5, 7, and 9 after Mode 3 are in the mislock state), the delay circuit constituting the voltage control delay circuit (VCD) 3 It can be understood that the output terminal of the second delayed clock signal (CKMO) should be taken out after N / 3 or more with respect to the number N.

FIGS. 3 and 4 show operation waveforms of the DLL circuit when the mislock prevention circuit of the present invention is used.

FIG. 3 shows an operation waveform in a normally locked state, in which the RS in the mask circuit 4 (see FIG. 1) is shown.
The output of the flip-flop (hereinafter referred to as RSO) is DLL
It can be seen that there is no influence on the feedback control of the circuit.

FIG. 4 shows a voltage control delay circuit (VCD).
3 shows operation waveforms when the delay time of 3 is three times that of normal operation.

It can be seen that the delay time (Ttd) in the normal lock state (see FIG. 3) is three times that in the normal operation in FIG.

At this time, if there is no mask circuit 4 (see FIG. 1), the signal on the CKout side is masked by the mask circuit 4 even in a state where a mislock occurs (for example, the state of FIG. 4). The rising and falling edges are masked at Ttd to prevent the waveform from appearing.) PC1 outputs and masks a high-level error signal (Verr), indicating that it is operating normally.

In FIG. 1, when it is necessary to strictly discuss the precision of the delay time (Ttd) of the voltage control delay circuit (VCD) 3, as shown in FIG. The selector circuit 22 is inserted on the clock side, and the output of the RS flip-flop in the mask circuit 4 (R
SO), and when the RSO signal is at a high level (the mask circuit operates at this time and masks to the same state as the low level), the output (CK2) of the 1/2 frequency divider 5 is used as a reference clock (CK). CKref).

When the RSO signal is low (at this time, the mask circuit is released), the mask circuit 4
(CKiN) is selected as a reference clock (CKref).

As a result, the delay time (T
It is possible to avoid an error factor of the delay time (Ttd) of the voltage control delay circuit (VCD) 3 due to the time td).

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 6 is a detailed circuit diagram of the mask circuit 4 having the function of preventing mislock used in the present invention.

As shown in FIG. 6, a delay circuit (CKMO) on the way between the output (CK2) of the half frequency divider 5 and the input to the output of the voltage control delay circuit (VCD) 3 is used as a delay circuit. 61, an RS flip-flop 62 composed of a two-input NOR 25 passing through a NOR 24 (NOR 25, NOR 25)
26, and the output (RSO) of the RS flip-flop 62 and the output (C
A signal (CKiN) obtained by inverting the output of the 2-input NOR 27 to which K2) has been input by the inverter 28 is extracted as the output of the mask circuit 4 (see FIG. 5).

In the circuit shown in FIG. 6, as in FIG.
When the masking circuit 4 (see FIG. 5) detects the rising edge of the output (CK2) of the 1/2 frequency divider 5, the output (KiN) of the masking circuit 4 changes to a high level, and The high level is maintained regardless of the signal of the output (CK2) of the frequency divider 5.

Next, a delayed clock (CKMO) output from an output terminal in the middle of the voltage control delay circuit (VCD) 3
When the mask circuit 4 detects the rising edge of the signal (CKiN), the output (CKiN) of the mask circuit 4 changes to low level, the mask state is released, and the output (CKK) of the half frequency divider 5 is released.
2) is passed through and output from the output (CKiN) of the mask circuit 4.

FIG. 7 shows a delay time T that is three times the normal state.
The state of td is shown.

As shown in FIG. 7, the delay clock (CKM
The mask circuit 4 performs a mask operation only when the signal O) is at a low level.

When the signal of the delayed clock (CKMO) is at a high level, the mask operation of the mask circuit 4 is released.

Therefore, the conventional function of preventing mislocking is as follows.
The circuit operates only when the signal of the delayed clock (CKMO) is at a low level, whereas the circuit operates similarly when the signal of the delayed clock (CKMO) is at a high or low level.

By the above operation, the voltage control delay circuit (V
Since only one waveform is input between the input of the CD) 3 and the output terminal on the way of outputting the delayed clock (CKMO), a plurality of mislocked waveforms are output from the voltage control delay circuit (VCD) 3. It is possible to avoid the problem accumulated in the inside.

Next, a third embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 8, a mask circuit 4 having a function of preventing mislock used in the present invention (see FIG. 5).
In this circuit, when the mask circuit 4 detects the rising edge of the output (CK2) of the half frequency divider 5 as in FIG. 7, the output (CKiN) of the mask circuit 4 changes to a high level, The high level is held regardless of the signal of the output (CK2) of the half frequency divider 5.

Next, a delayed clock (CKMO) output from an output terminal in the middle of the voltage control delay circuit (VCD) 3
When the mask circuit detects the rising edge of, the output (CKiN) of the mask circuit 4 changes to a low level, and keeps the low level regardless of the signal of the delay clock (CKMO).

With the above operation, the delay clock (CKM) is input from the input of the voltage control delay circuit (VCD) 3 as in FIG.
Since only one waveform is input to the output terminal in the middle of outputting O), the problem that a plurality of mislocked waveforms are accumulated in the voltage control delay circuit (VCD) 3 is avoided. Things become possible.

Next, FIGS. 9 and 10 show the fourth and fifth embodiments of the present invention.

In both the fourth and fifth embodiments of the present invention,
This plays a role similar to that of the first embodiment of the present invention shown in FIG.

With the above operation, the delayed clock (CKM) is input from the input of the voltage control delay circuit (VCD) 3 as in FIG.
Since only one waveform is input to the output terminal in the middle of outputting O), the problem that a plurality of mislocked waveforms are accumulated in the voltage control delay circuit (VCD) 3 is avoided. Things become possible.

The circuit described above is not limited to the rising edge. If the phase comparator PC1 (see FIG. 1) is of a type that compares only the falling edge of the input clock, the circuit shown in FIG. The NOR circuit shown in FIGS. 6 and 8 can be replaced with a NAND circuit to detect the falling edge and operate the mask circuit 4.

[0111]

According to the present invention, a voltage control delay circuit (VCD) used in a DLL circuit of a semiconductor device can be provided.
The use of the mask circuit 4 for limiting the input of the external clock (CKext) to the input section 3 can prevent the DLL circuit from being locked.

Further, a low-cost and highly reliable DLL circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a DLL circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a mislock prevention circuit of the DLL circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing operation waveforms of the mislock prevention circuit of the normally locked DLL circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an operation waveform representing a delay time state three times that of a normally locked state according to the first embodiment of the present invention.

FIG. 5 is a block diagram schematically showing a DLL circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a mislock prevention circuit of a DLL circuit according to a second embodiment of the present invention.

FIG. 7 is a view showing an operation waveform representing a delay time state three times as long as a normally locked state according to the second embodiment of the present invention.

FIG. 8 is a diagram showing a mislock prevention circuit of a DLL circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram illustrating a mislock prevention circuit of a DLL circuit according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram schematically showing a DLL circuit according to a conventional technique.

FIG. 11 shows a normally locked D according to the related art.
FIG. 4 is a diagram showing operation waveforms of a mislock prevention circuit of the LL circuit.

FIG. 12 is a diagram showing a mislock prevention circuit of a DLL circuit according to a conventional technique.

FIG. 13 is a diagram showing a mislock prevention circuit of a DLL circuit according to a conventional technique.

FIG. 14 shows a normally locked D in the related art.
FIG. 4 is a diagram showing operation waveforms of a mislock prevention circuit of the LL circuit.

FIG. 15 is a diagram showing an operation waveform of a mislock prevention circuit in an unlocked state according to the related art.

FIG. 16 is a diagram showing an operation state from input to output of a voltage control delay circuit in a lock state of a DLL circuit according to a conventional technique.

[Explanation of symbols]

 1, 101 phase comparator (PC) 2, 102 low-pass filter (LPF) 3, 103 voltage control delay circuit (VCD) 4 mask circuit 22 selector circuit 23, 62 RS flip-flop 24, 25 , 26, 27: NOR circuit 28: Inverter 61: Delay circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 5/13 G06F 1/04 330A

Claims (10)

[Claims] 1. A DLL circuit having a mislock prevention function, comprising: a voltage-controlled delay circuit that outputs a first delayed clock signal having a predetermined delay time with respect to a reference clock signal; Outputs a second delay clock signal having a delay time controlled by a control voltage and further having a delay time shorter than the delay time, and an error corresponding to a phase difference between the first delay clock signal and the reference clock signal. A phase comparator that outputs a signal; a control voltage generation unit that generates the control voltage that controls a delay time of the voltage control delay circuit in accordance with the error signal; and a reference voltage in accordance with the second delay clock signal. And a mask circuit for restricting passage of a clock signal to the voltage control delay circuit. 2. An RS flip-flop for detecting a rise (fall) of the reference clock signal and a rise (fall) of the second delayed clock signal; and an output of the RS flip-flop. A reference clock signal is input, and in response to the output signal of the RS flip-flop, the input reference clock signal is directly output and input to the voltage control delay circuit, or a high-level or low-level fixed signal is output. 2. The DLL circuit according to claim 1, further comprising: a circuit which operates so as not to pass the inputted reference clock signal by outputting the inputted reference clock signal to the voltage control delay circuit. 3. The delay circuit according to claim 2, wherein the mask circuit detects a rise (fall) of the second delay clock signal and outputs a pulse, a rise (fall) of the reference clock signal and the delay. An RS flip-flop for detecting a rising edge (falling edge) of an output pulse of the clock detection circuit; an input of the output of the RS flip-flop and the reference clock signal; and the reference input according to an output signal of the RS flip-flop. The clock signal is output as it is and input to the voltage control delay circuit, or a high or low level fixed signal is output and input to the voltage control delay circuit so that the input reference clock signal is not passed. 2. The DLL circuit according to claim 1, further comprising a circuit that operates. 4. The mask circuit receives the second delayed clock signal, and outputs a clock pulse having one edge synchronized with the reference clock signal and the other edge synchronized with the second delayed clock signal. 2. The D according to claim 1, wherein the signal is output and input to the voltage control delay circuit.
LL circuit. 5. The mask circuit receives the second delayed clock signal, and outputs a rising (falling) edge synchronized with a rising (falling) edge of the input reference clock signal and the input second input clock signal. 2 to generate an output pulse consisting of a falling (rising) edge synchronized with the rising (falling) edge of the delayed clock signal,
2. The DLL circuit according to claim 1, wherein the generated output pulse is input to the voltage control delay circuit. 6. The reference clock signal flip-flop that receives the second delayed clock signal, detects a rising (falling) edge of the input reference clock signal, and inputs the second delayed clock signal. A second delayed clock signal flip-flop for detecting a rising (falling) edge of the second delayed clock signal, wherein the reference clock signal flip-flop receives the inputted reference clock signal. The second delayed clock flip-flop detects the rising (falling) edge of the input second delayed clock signal and detects the rising (falling) edge of the reference clock. Resetting the output of the signal flip-flop and flipping the reference clock signal. DLL circuit of claim 1, wherein the inputting the output pulse of flop to the voltage controlled delay circuit. 7. The DLL circuit according to claim 1, wherein said reference clock signal is a clock signal obtained by dividing an external clock signal by a half frequency divider. 8. The DL according to claim 1, wherein the phase comparator compares a phase difference between each rising edge between the first delayed clock signal and the reference clock signal.
L circuit. 9. The voltage controlled delay circuit has a configuration in which a plurality of delay circuits are cascaded, and the second delayed clock signal is output from any one of the plurality of delay circuits. The DLL circuit according to claim 1, wherein: 10. The masking circuit masks the reference clock signal by holding its output at a high level at the rising edge of the reference clock signal, and the output of the masking circuit that has gone to a high level is the voltage control delay. 2. The DLL circuit according to claim 1, wherein when the second delay clock signal propagates through the circuit and becomes high, the mask is released and the reference clock signal is passed.