JP2000277329A - Load drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce cost without requiring a reverse current diode or a capacitor for absorbing ripples. SOLUTION: This load drive circuit has a power transistor 3 for driving an inductive load 8 and a transistor 4 for driving the power transistor in on- state, which is connected between an output terminal and a control electrode of the power transistor 3 and is turned on, the turn on the power transistor 3, when a bias voltage reaches a prescribed clamp voltage by a back-surge input which is generated, when the inductive load 8 is switched off with reference to a constant potential prescribed in a power source 9 to cause the power transistor 3 to absorb the back surge.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load driving circuit for controlling a current flowing to an inductive load by PWM.

[0002]

2. Description of the Related Art A conventional load driving circuit drives a load by turning on / off a power transistor. In this method, the power transistor is turned on when the load is driven, and the power transistor is turned off when the load is not driven, so that the backsurge flows to the battery line by the return diode.

[0003]

However, in the conventional load drive circuit, when the load is not driven, the back surge is released to the battery line by the freewheel diode, and such a load is used in, for example, a vehicle or the like. In the case of an inductive load, the rated driving current is about several amps, and a power transistor and a free wheel diode having a rated current of several amps must be used. In general, when an element having a large rated current is formed of a semiconductor, the chip size becomes large and the cost increases.

Further, in the conventional load drive circuit, a backsurge flows from the freewheeling diode to the battery line when the load is not driven, so that a large current flows to the battery especially when the power transistor is turned off. The large current causes ripple noise in the battery line. In order to avoid this, a capacitor for absorbing ripple noise is used, so that the cost is further increased.

The present invention has been made in view of such conventional problems, and has as its object to provide a low-cost load driving circuit which does not require a free wheel diode and a ripple absorbing capacitor.

[0006]

According to a first aspect of the present invention, there is provided a power transistor for switchingly driving an inductive load connected to a power supply, and an output of the power transistor to the inductive load. Connected between the terminal and the control electrode, and turned on when a bias system voltage reaches a predetermined clamp voltage due to a backsurge input generated by switching the inductive load with reference to a constant potential defined by the power supply. The gist is that the power transistor includes a power transistor-on drive transistor that turns on the power transistor and causes the power transistor to absorb the back surge.
With this configuration, at the time of switching driving of the inductive load by the power transistor, the bias system voltage of the transistor for driving the power transistor on due to the back surge generated in the inductive load at the time of switching off, the predetermined voltage based on the constant potential specified by the power supply. When this clamp voltage is reached, the transistor for driving the power transistor turns on, and a back surge is conducted to the control electrode of the power transistor. When the control electrode voltage reaches a predetermined threshold, the power transistor is turned on, and the back surge flows through the power transistor and is absorbed. When the surge energy is consumed by this absorption, the power transistor ON drive transistor and the power transistor return to the OFF state.

According to a second aspect of the present invention, in the load driving circuit according to the first aspect, the constant potential is a positive potential of the power supply, and one end of the inductive load is connected to a positive potential side of the power supply; The point is that the other end of the inductive load is driven by switching with the power transistor. With this configuration, the bias voltage of the transistor for driving the power transistor on due to the back surge generated by the inductive load at the time of switching on adds the fixed voltage determined by the bias characteristic of the transistor for driving the power transistor to the positive potential of the power supply. When the voltage rises to the clamp voltage, the transistor for driving the power transistor turns on, and the power transistor is turned on with this turning on, and the back surge flows through the power transistor and is absorbed.

According to a third aspect of the present invention, in the load drive circuit according to the first aspect, the constant potential is a negative potential of the power supply, and one end of the inductive load is connected to a negative potential side of the power supply; The point is that the other end of the inductive load is driven by switching with the power transistor. With this configuration, the bias system voltage of the power transistor on drive transistor is subtracted from the negative potential of the power supply by a constant voltage determined by the bias characteristic of the power transistor on drive transistor due to the back surge generated by the inductive load at the time of switching on. When the clamp voltage reaches the clamp voltage, the transistor for driving the power transistor is turned on, and the power transistor is turned on with this turning on, and the back surge flows through the power transistor and is absorbed.

According to a fourth aspect of the present invention, in the load driving circuit according to the first or second aspect, the power transistor is an N-type MOS transistor, and the power transistor-on driving transistor is a PNP transistor. And With this configuration, the PNP caused by the back surge generated by the inductive load at the time of switching on
When the bias voltage of the transistor rises to the positive potential of the power supply and the clamp voltage obtained by adding the voltage between the base and the emitter of the PNP transistor, the PNP transistor turns on. A back surge is passed. When the gate voltage rises to a predetermined threshold, the N-type MOS transistor turns on, and the back surge flows through the N-type MOS transistor and is absorbed.

According to a fifth aspect of the present invention, in the load driving circuit according to the first or third aspect, the power transistor is a P-type MOS transistor, and the power transistor-on driving transistor is an NPN transistor. And With this configuration, NPN is generated by back surge generated by the inductive load at the time of switching off.
The bias voltage of the transistor changes from the negative potential of the power supply to
When the voltage drops to the clamp voltage obtained by subtracting the base-emitter voltage of the NPN transistor, the NPN transistor turns on, and a back surge flows through the gate of the P-type MOS transistor with the turning on. When the gate voltage drops to a predetermined threshold, the P-type MOS transistor is turned on, and the back surge flows through the P-type MOS transistor and is absorbed.

[0011]

According to the first aspect of the present invention, a power transistor for switchingly driving an inductive load connected to a power supply, and a power transistor connected between an output terminal to the inductive load and a control electrode of the power transistor. When the bias system voltage reaches a predetermined clamp voltage due to a backsurge input generated by switching the inductive load with reference to a constant potential defined by the power supply, the power transistor turns on to turn on the power transistor, Since the power transistor is provided with a power transistor on drive transistor for absorbing the back surge, a back surge generated by an inductive load at the time of switching off passes through a control electrode of the power transistor to turn on the power transistor. Flowing power transistor Because it is absorbed, there is no need for a freewheeling diode with a large rated current, and there is no path to the power supply in the path for clamping the back surge, and ripple noise caused by the steep rising current that occurs when switching is switched. Never return to the route. Therefore, it is not necessary to provide a capacitor for absorbing ripple noise. Since the power transistor-on drive transistor only needs to be able to apply a voltage for turning on the power transistor to the control electrode, the power transistor-on drive transistor needs to have a small rating, and the power transistor-on drive transistor can have a small chip area. . From these facts, cost reduction can be achieved.

According to the present invention, the constant potential is a positive potential of the power supply, one end of the inductive load is connected to a positive potential side of the power supply, and the other end of the inductive load is connected to the power supply. Since the switching drive is performed by the transistor, the power transistor on drive transistor is turned on when the bias voltage of the power transistor on drive transistor reaches the clamp voltage set based on the positive potential of the power supply due to back surge. Therefore, even if the power supply voltage fluctuates, it is possible to avoid a malfunction of the power transistor ON drive transistor, and it is possible to reliably absorb the back surge by the power transistor without using a freewheeling diode. it can.

According to the third aspect of the present invention, the constant potential is a negative potential of the power supply, one end of the inductive load is connected to a negative potential side of the power supply, and the other end of the inductive load is connected to the power supply. Since the switching drive is performed by the transistor, the power transistor on drive transistor is turned on when the bias voltage of the power transistor on drive transistor reaches the clamp voltage set based on the negative potential of the power supply due to back surge. Therefore, even if the power supply voltage fluctuates, it is possible to avoid a malfunction of the power transistor ON drive transistor, and it is possible to reliably absorb the back surge by the power transistor without using a freewheeling diode. it can.

According to the fourth aspect of the present invention, the power transistor is an N-type MOS transistor and the power transistor ON drive transistor is a PNP transistor. When the voltage rises to the clamp voltage set based on the positive potential, the PNP transistor turns on. Therefore, even if the power supply voltage fluctuates, malfunction of the PNP transistor can be avoided, and the freewheeling diode can be used. Without using it, the back surge can be reliably absorbed by the N-type MOS transistor.

According to the fifth aspect of the present invention, the power transistor is a P-type MOS transistor, and the power transistor ON drive transistor is an NPN transistor. Since the NPN transistor turns on when the clamp voltage set based on the negative potential is reached, even if the power supply voltage fluctuates, malfunction of the NPN transistor can be avoided, and the freewheeling diode can be used. Without using it, the back surge can be reliably absorbed by the P-type MOS transistor.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 to FIG. 4 are views showing a first embodiment of the present invention. First, the configuration of the load driving circuit will be described with reference to FIG. In the figure, 1 is the PW of the inductive load
The microcomputer that controls the M control is an integrated circuit. In the integrated circuit 2, an NMOS power transistor 3 for driving an inductive load, a Zener diode 5 for protecting a gate, a PNP transistor 4 as a transistor for driving a power transistor, a resistor 6, and an input buffer 7 are integrated. An IN terminal to which a PWM signal is input, a VB terminal to which a battery (power supply) 9 is connected, an OUT terminal to drive the inductive load 8, and GND to be connected to ground
Terminals are provided. The PWM signal input to the IN terminal from the microcomputer 1 is input to the gate (control electrode) of the NMOS power transistor 3 via the input buffer 7 and the resistor 6. The base of the PNP transistor 4 is connected to the positive potential side of the battery 9 via the VB terminal, the emitter is connected to the drain of the NMOS power transistor 3, that is, the OUT terminal, and the collector is connected to the gate of the NMOS power transistor 3. One end of the inductive load 8 is connected to the positive potential side of the battery 9, and the other end is connected to the OUT terminal of the integrated circuit 2.

Next, the operation of the load driving circuit configured as described above will be described with reference to the operation waveforms of FIG. When a Vcc level signal is applied to the IN terminal from the microcomputer 1 (FIG. 2A), the input signal
The signal of VB level is input to the gate of the NMOS power transistor 3 (FIG. 2).
(B)). As a result, the NMOS power transistor 3 is turned on (FIG. 2C), and the current starts to gradually increase due to the inductance component of the inductive load 8. When the on-state is continued as it is, the current becomes the voltage VB of the battery 9, the resistance RL of the inductive load 8, and the NMOS as shown in the following equation.
The current converges on the current Imax determined by the on-resistance Ron of the power transistor 3 (FIG. 2D).

Imax = VB / (RL + Ron) (1) Next, when a 0V signal is input from the microcomputer 1, the output of the input buffer 7 also becomes 0V, and the gate of the NMOS power transistor 3 is also connected via the resistor 6. It is pulled out to 0V.
Then, the NMOS power transistor 3 is turned off, so that a back surge occurs due to the inductance component of the inductive load 8. The back surge causes the drain potential of the NMOS power transistor 3 to rise, that is, the potential of the OUT terminal. When the voltage reaches the clamp voltage Vclamp determined by the voltage of the battery 9 and the base-emitter voltage VBE of the PNP transistor 4, the PNP transistor 4 Is turned on, and the NMOS power transistor 3
A backsurge is conducted to the gate of the gate, and a voltage starts to be applied.

Vclamp = VB + VBE (2) Here, when the gate voltage of the NMOS power transistor 3 rises to the threshold value, the NMOS power transistor 3 starts to transition to the ON state.
Is turned on, a current due to the back surge flows through the NMOS power transistor 3 and acts in a direction to prevent an increase in the drain voltage. Therefore, the circuit operation is in a form in which negative feedback is applied such that the drain voltage is maintained at the clamp voltage, and the surge energy stored in the inductive load 8 is consumed, and the circuit operation is continued until the drain voltage cannot be maintained.
If the drain voltage cannot be held, NM
The OS power transistor 3 is turned off.

FIGS. 3 and 4 show examples of operation waveforms when the inductive load is PWM-controlled by the load driving circuit having the above-described functions. FIG. 3 shows a comparison of a current waveform flowing through the inductive load due to a difference in switching cycle, and FIG. 4 shows a comparison of a current waveform flowing through the inductive load and an average current when the duty ratio of the PWM signal is varied. As shown in FIG. 3, when the switching cycle is T and when the switching cycle is 5T, the average current Iave is equal, but a large difference is seen in the current ripple. In the case where current control is performed by PWM, switching can be performed in a sufficiently fast cycle to reduce the amount of current ripple. Further, as shown in FIG. 4, by varying the duty ratio of the PWM signal, the current value of the average current Iave flowing through the inductive load 8 can be controlled.

As described above, in the present embodiment, NM
At the time of switching driving of the inductive load 8 by the OS power transistor 3, the back surge generated in the inductive load 8 at the time of switching off is reduced to N through the PNP transistor 4.
Input to the gate of MOS power transistor 3
Turn on the power transistor 3 and set back surge to NM
It is made to flow into the OS power transistor 3 to be absorbed. Therefore, conventionally, the backsurge itself was clamped by the freewheeling diode, so that a diode having a large rating was required. In the present embodiment, the PNP transistor 4 uses the gate to turn on the voltage for turning on the NMOS power transistor 3. Since it is sufficient to add them, only a small rating is required, the chip area of the PNP transistor 4 can be reduced, and the cost can be reduced.

Further, in the present embodiment, there is no path to the battery 9 in the path for clamping the back surge, and ripple noise caused by a steep rising current generated at the time of switching is returned to the path of the battery 9. Nothing. Therefore, it is not necessary to provide a capacitor for absorbing ripple noise, and the cost can be reduced in this respect as well.

Further, when performing current control by PWM, the clamp voltage for clamping the back surge is as follows:
It is desirable to reduce the current fluctuation by lowering the voltage as much as possible (extracting the back surge over time). However, a battery for a vehicle or the like has a large voltage fluctuation, and in the related art, a dump surge is added due to the voltage fluctuation of the battery. In this case, the clamp voltage must be set to a somewhat high value so that the power transistor is not turned on, and there is a trade-off relationship. In contrast, in the present embodiment,
When a dump surge is applied, the base of the PNP transistor 4 also increases as the battery voltage increases, so that the PNP transistor 4 does not turn on. Therefore, the clamp voltage can be reduced, and the NMOS power transistor 3 can be used even when a dump surge is applied while keeping the clamp voltage low so as to suppress current fluctuation.
Does not turn on.

FIGS. 5 and 6 show a second embodiment of the present invention. In the present embodiment, a PMOS power transistor 13 is used as a power transistor, an NPN transistor 14 is used as a power transistor ON drive transistor, and an inverter is used as an input buffer 17. The source of the PMOS power transistor 13 is connected to the positive potential side of the battery 9 via the SRC terminal of the integrated circuit 12, and the drain is connected to the integrated circuit 2
OUT terminal. The PWM signal input to the IN terminal from the microcomputer 1 is inverted by the input buffer 17 and then input to the gate of the PMOS power transistor 13 via the resistor 6. NPN
The base of the transistor 14 is connected to ground via the GND terminal, that is, to the negative potential side of the battery 9, and the emitter is connected to the drain of the PMOS power transistor 13, ie, OUT
The collector is connected to the terminal, and the collector is connected to the gate of the PMOS power transistor 13. One end of the inductive load 8 is connected to the negative potential side of the battery 9 and the other end is connected to the integrated circuit 12.
OUT terminal.

The first embodiment is a load drive circuit for controlling the downstream of the inductive load 8, whereas the present embodiment is a load drive circuit for controlling the upstream of the inductive load 8. FIG. 6 shows the circuit operation. The operation principle is almost the same as that of the first embodiment.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a load driving circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of each unit for explaining the operation of the first embodiment.

FIG. 3 is a diagram showing a comparison of waveforms of a current flowing through an inductive load due to a difference in a switching cycle in the first embodiment.

FIG. 4 is a diagram showing a comparison between a current waveform and an average current flowing through an inductive load when the duty ratio of a PWM signal is varied in the first embodiment.

FIG. 5 is a circuit diagram according to a second embodiment of the present invention.

FIG. 6 is a diagram showing operation waveforms of respective units for explaining the operation of the second embodiment.

[Explanation of symbols]

Reference Signs List 3 NMOS power transistor 4 PNP transistor (power transistor on driving transistor) 8 inductive load 9 battery (power supply) 13 PMOS power transistor 14 NPN transistor (power transistor on driving transistor)

Claims (5)

[Claims] 1. A power transistor for switchingly driving an inductive load connected to a power supply, connected between an output terminal of the power transistor to the inductive load and a control electrode, wherein a bias system voltage is defined by the power supply. When a predetermined clamp voltage is reached by a backsurge input generated by switching the inductive load with reference to a constant potential, the power transistor is turned on to turn on the power transistor, and the power transistor absorbs the backsurge. A load drive circuit, comprising: a power transistor-on drive transistor. 2. The method according to claim 1, wherein the constant potential is a positive potential of the power supply.
One end of the inductive load is connected to a positive potential side of the power supply,
2. The load drive circuit according to claim 1, wherein the other end of the inductive load is switched by the power transistor. 3. The constant potential is a negative potential of the power supply.
One end of the inductive load is connected to a negative potential side of the power supply,
2. The load drive circuit according to claim 1, wherein the other end of the inductive load is switched by the power transistor. 4. The load drive circuit according to claim 1, wherein said power transistor is an N-type MOS transistor, and said power transistor ON drive transistor is a PNP transistor. 5. The load drive circuit according to claim 1, wherein said power transistor is a P-type MOS transistor, and said power transistor ON drive transistor is an NPN transistor.