JP2000276271A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer system taking noise measures without directly connecting a noise influence source with a bus. SOLUTION: When transferring tuning data from a CPU 4 to a PLL control IC 1, first of all, the data are transferred through a bus 5 to an interface circuit 7 of a demodulation IC 2 and transferred from the interface circuit 7 of the demodulation IC 2 through a local bus 6 to the PLL control IC 1. When transferring data from the PLL control IC 1 to the CPU 4 oppositely, the data are temporarily transferred through the local bus 6 to the interface circuit 7 of the demodulation IC 2 and transferred from the interface circuit 7 of the demodulation IC 2 through the bus 5 to the CPU 4 later. Excepting for data transfer with the PLL control IC 1, the local bus 6 is fixed at a prescribed level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system with noise suppression.

[0002]

2. Description of the Related Art In recent years, digital data transmission / reception techniques have been developed for wireless broadcasting such as television and radio. Even in such a technique, a local oscillation signal is output from a PLL, a predetermined RF signal is tuned based on the local oscillation signal, and the RF signal is frequency-converted into an IF signal. The IF signal is input to a demodulation IC constituted by a digital circuit, and is digitally demodulated. The above configuration is described as shown in FIG.

In such a circuit, a tuning PLL is used.
Control IC (hereinafter referred to as PLL control IC) 1, demodulation IC
2 and other ICs 3 are connected to the CPU 4 via the bus 5. Tuning data is written to the PLL control IC 1 via the bus 5, and demodulation data and demodulation control data are transferred between the demodulation IC 2 and the CPU 4. For example, in the bus system, each IC including the CPU 4 has a different address, and when data is transferred, the address of the IC to which data is to be transferred is first transferred to change the desired IC to the data receiving state. The state is allowed and the data is sent afterwards.

[0004]

In the conventional circuit of FIG. 3 in which the PLL control IC1, the demodulation IC and the CPU 4 are connected via a common bus line, the CPU 4 constantly exchanges data with any one of the ICs. Therefore, for example, PL
In the L control IC 1, the data in the bus 5 constantly fluctuates even when the channel selection data is not rewritten. Therefore, noise is generated due to the fluctuation of the data, and the noise adversely affects the PLL control IC1.

For example, a PLL control IC constitutes a PLL together with a VCO for outputting a local oscillation signal and a frequency control signal for the VCO. PLL control IC is VCO
Is compared with the reference clock to output an error signal corresponding to the phase error. If noise is included in the bus line 5 as described above, the noise is superimposed on the error signal. When noise is superimposed, the error signal fluctuates, and the frequency control signal also fluctuates, so that the output frequency of the VCO fluctuates. As a result, jitter occurs in the output signal of the VCO, which causes deterioration of demodulation performance because the demodulation IC cannot accurately reproduce the reproduced clock.

[0006]

According to the present invention, a first circuit serving as a master, a second circuit serving as a slave, and a first bus connected between the first and second circuits are provided. A data transfer system having a third circuit connected to the second circuit via a second bus, the first circuit being connected to the second circuit, and the third circuit being connected via the first and second buses. Data transmission and reception.

In particular, the second bus is fixed at a predetermined level except when data is transmitted and received between the first and third circuits.

The second circuit includes an interface circuit for controlling transmission and reception of data between the first and third circuits.

Further, the interface circuit selects at least one of input data or a fixed-level signal via the first bus and outputs the selected signal to the second bus, And an interface control circuit that causes the selection circuit to select data from the first circuit only when it is detected that data transmission / reception between the three circuits is performed.

Still further, the interface circuit includes a second selection circuit for selecting one of input data or a fixed level signal via the second bus and outputting the selected signal to the first bus.

Data transmission and reception between the first circuit serving as a master and the second circuit serving as a slave which does not want to be affected by noise is performed via the first and second buses and the third circuit. Do. At this time, the second bus is fixed at a predetermined level except when data is transmitted and received between the first and third circuits, so that adverse effects of noise on the second circuit can be prevented.

[0012]

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, a PLL control IC 1 and a CPU 4
And remove the bus 5 connected between the
The local bus 6 connects between the L control IC 1 and the demodulation IC 6. The demodulation IC 2 has an interface circuit 7 for connecting the bus 5 and the local bus 6. To transfer channel selection data from the CPU 4 to the PLL control IC 1, first, the demodulation IC 2
From the interface circuit 7 of the demodulation IC 2 via the local bus 6.
This is transferred to the L control IC1. Conversely, when transferring an acknowledgment signal indicating that tuning data has been received from the PLL control IC 1 to the CPU 4 or, for example, various flags indicating PLL lock, the interface circuit 7 of the demodulation IC 2 once via the local bus 6. After being transferred to the interface circuit 7 of the demodulation IC 2
4 via the bus 5. In addition, PLL control IC1
When data is not exchanged between the local bus 6 and the CPU 4,
Is kept constant, and even if the level of the bus 2 fluctuates due to data transfer, noise is prevented from being mixed into the local bus 6.

Since the noise is not unnecessarily mixed into the local bus 6, the error signal and the frequency control signal do not fluctuate, and the occurrence of jitter in the output signal of the VCO can be prevented. Therefore, the reproduction clock can be accurately reproduced in the demodulation IC, and deterioration of the demodulation performance can be prevented.

The problem of noise caused by the bus 5 is as follows.
This is not a problem related only to the PLL control IC1. When noise is mixed into the bus 5, erroneous data is input to the demodulation IC 2 or another IC 3 according to the noise, and
2 and other ICs 3 may malfunction. In that case, the present invention is applied, and the interface circuit 7 is connected to an IC different from the IC to which data is to be transferred.
And a local bus is connected between the two ICs to transmit and receive data via the interface circuit and the local bus.

In FIG. 1, the demodulation IC 2 and the CPU 4
In order to exchange data with the demodulation IC 2, the demodulation IC 2 has its own interface circuit 8 and is performed via the interface circuit 8.

FIG. 2 is a diagram showing a specific example of the interface circuit 7 of FIG. 21 is an SDA input / output terminal, 22 is an SCL input terminal, and 23 and 24 are data S
A buffer for receiving the DA and the clock SCL, 25 controls the operation of the entire interface circuit 7 in accordance with the contents of the data SDA, and an interface control circuit for receiving data for the demodulation IC 2, and 26 a flag output from the interface control circuit 25 SL1 and a register for holding an address; 27, a MUX for selecting data SDA and fixed-level data PO0;
MUX for selecting CL and fixed-level data PO1,
29 and 30 are inverters for inverting the outputs of the MUXs 27 and 28, 31 and 32 are transistors that are turned on and off according to the outputs of the inverters 29 and 30, respectively, 33 is an input / output terminal PDA, 34 is an output terminal PCL, and 35 is a PL.
A buffer for receiving data from the L control IC 1
Buffer for inputting signal received at O0 input / output terminal, 36
Is an MUX that receives the buffer 35 and the fixed-level signal PO2, 37 is an inverter that inverts the output of the MUX 36, and 38 is a transistor that is turned on and off according to the output of the inverter 37. Further, FIG.
3 is an MUX inserted between the MUX 27 and the MUX 27 to select the output of the buffer 23 and the fixed level PO3.

First, data is sent from the CPU 4 to the PLL control I.
The operation when the data is transferred to C1 will be described. First,
Before the CPU 4 communicates with the PLL control IC 1, the CPU 4
Transmits start data indicating the start of communication with the PLL control IC1 to the demodulation IC2. The interface control circuit 25 is activated by the data. Then, the interface control circuit 25 outputs the flag SL1 that becomes “1” and the unique address AD of the interface circuit 7 and writes them into the register 26.

The SL1 signal becomes "1", the output of the buffer 23 is selected by the MUX 27, and the output of the buffer 24 is selected by the MUX 28. Therefore, SD
The A input / output terminal 21 and the PO0 input / output terminal 33 are conducted, and the SCL input terminal 22 and the PO1 output terminal 34 are conducted.

After the start data, the CPU 4 sets P
It outputs address data and tuning data corresponding to the LL control IC1. The address data is input to the interface control circuit 25, and coincides with the address written in the register 26. Thereby, the PLL control IC
Since it is recognized that the data is for one, even if the channel selection data is input to the interface control circuit 25, it is not received. Address data and normal data are input to the MUX 27 via the SDA input / output terminal 21 and the buffer 23. The data is output from the MUX 27 and inverted by the inverter 25. The output of the inverter 25 is applied to the gate of the transistor 31,
Is turned on and off. The voltage at the connection point between the resistor R1 and the transistor 33 becomes 0 V in accordance with the on / off of the transistor 31.
And the voltage Vc, and a signal is sent from the input / output terminal PO0 to the PLL control IC1 according to the data.

A clock is applied to the SCL output terminal 22 in synchronization with the address data and the tuning data. S
The clock input to the CL output terminal 22 is a MUX 28
, The clock is transferred to the PLL control IC 1 by turning on and off the transistor 32 after being inverted by the inverter 30.

The PLL control IC 1 receives address data and tuning data in synchronization with a clock. In response, the PLL control IC 1 outputs an ACK signal (acknowledge signal). At the timing when the ACK signal is output, the interface control circuit 25 sets the SL2 signal to “1”, whereby the MUX 36
Select the output and output. The ACK signal is stored in the buffer 35.
, And is input to the gate of the transistor 38 after being inverted by the inverter 37 via the MUX 36. When the transistor 38 is turned on or off, an ACK signal is transmitted from the SDA input / output terminal 21 to the CPU 4.

The MUX 39 is inserted between the buffer 23 and the MUX 27. PLL control IC1 and CP
Assuming that data is transmitted and received with U4,
When the SL1 signal becomes “1”, the MUX 27
Output on the 3 side is selected. Assuming that there is no MUX 39, when the ACK signal is generated, the transistor 31 is turned on and off in accordance with the on and off of the transistor 38. That is, the ACK signal may flow to the transistor 31. Therefore, the MUX is set by the SL2 signal being “1”.
39 selects a fixed level signal OP3,
The transistor 31 turns off. Therefore, when the ACK signal or another signal described later is transferred from the PLL control IC 1 to the CPU 4, the signal is prevented from wrapping around, and the signal can be transferred accurately.

When no ACK signal is generated, MUX
36 selects the fixed-level signal PO2, and the transistor 38 is turned off. If the SL2 signal is always kept at "1", racing occurs between the data transferred from the CPU 4 and the data transferred from the PLL control IC1. Therefore, in order to prevent such a problem from occurring, the timing at which the MUX 36 selects the PO0 input terminal 33 is limited to the timing at which the PLL control IC1 generates an ACK signal, and the timing at which the PLL control IC1 outputs flags and data. Can be Since the timing at which data is output from the PLL control IC 1 is determined by a predetermined rule, the MUX 36 is output at a predetermined timing.
Is switched, racing is prevented from occurring.

The generation of the SL2 signal is controlled by the interface control circuit 25. That is, since the interface control circuit 25 is included in the demodulation IC 2, it can be regarded that the demodulation IC 2 apparently controls the timing of the SL2 signal. Therefore, even if the PLL control IC 1 and the CPU 4 are actually communicating, the demodulation IC 2 and the CPU 4 are virtually communicating. Therefore, the interface control circuit 25 refers to the address for the PLL control IC1 written in the register 26, recognizes that the communication between the PLL control IC1 and the CPU 4 is being performed, and sets the SL1 signal to “1”. When the interface control circuit 25 and the CPU 4
It becomes the communication mode with. Even if it is in communication mode,
MUX 36 does not actually transmit or receive data.
It only controls the transmission and reception timing.

In the interface circuit shown in FIG.
The communication between the LL control IC 1 and the CPU 4 is released when the CPU 4 actually starts transmitting and receiving data to and from the demodulation IC 2. When the CPU 4 attempts to start communication with the demodulation IC 2, the CPU 4 first transmits address data for the demodulation IC 2. The address data is input to the interface control circuit 25 via the SDA input / output terminal 21 and the buffer 23 in synchronization with the clock SCL.
When the interface control circuit 25 recognizes that the address data is the address for the demodulation IC 2,
Is reset, and the data written in the register 26 is erased.

Then, the SL1 signal becomes "0" and the MU
X27 and X28 select data PO0 and PO1, respectively. Since the data PO0 and PO1 are at a fixed level of "0", the transistors 31 and 32 are turned off. Therefore, the levels of the PO0 input / output terminal 33 and the PO1 output terminal 34 become the power supply voltage level, so that the bus between the interface circuit and the PLL control IC 7 is disconnected. As a result, transmission of noise to the PLL control IC can be cut off. Further, the demodulation IC 2 can be reliably returned to the normal communication mode by the automatic reset function for the register 26 of the interface control circuit 25.

[0027]

According to the present invention, data transmission and reception between a first circuit serving as a master and a second circuit serving as a slave which is not to be affected by noise is performed by using the first and second buses. Since the processing is performed via the third circuit, it is possible to prevent adverse effects of noise on the second circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the interface circuit 7 of FIG.

FIG. 3 is a block diagram showing a conventional example.

[Description of Signs] 1 PLL control IC 1 2 Demodulation IC 4 CPU 5 Bus 6 Local bus 7 Interface circuit

Claims (5)

[Claims] 1. A data transfer system comprising a first circuit serving as a master, a second circuit serving as a slave, and a first bus connected between the first and second circuits. , A third circuit connected to the second circuit via a second bus, wherein the first and third circuits transmit and receive data via the first and second buses. Characteristic data transfer system. 2. The data transfer system according to claim 1, wherein the second bus is fixed at a predetermined level except when data is transmitted and received between the first and third circuits. 3. The data transfer system according to claim 1, wherein said second circuit includes an interface circuit for controlling data transmission and reception between said first and third circuits. 4. The interface circuit according to claim 1, wherein the interface circuit selects at least one of input data or a fixed-level signal via the first bus, and outputs the selected signal to the second bus. Only when it is detected that data transmission / reception is performed between the three circuits, the first circuit is provided to the selection circuit.
4. The data transfer system according to claim 3, further comprising an interface control circuit for selecting data from the circuit. 5. The interface circuit according to claim 2, wherein:
5. The data transfer system according to claim 4, further comprising a second selection circuit that selects one of input data or a fixed-level signal via the bus and outputs the selected signal to the first bus.