JP2000276101A - Method of driving plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize suppression of a false contour with stabilized operation, low power consumption, and high contrast by making a pulse width of the scanning pulse in a backward sub-field in a display period of a 1st field longer than that of the scanning pulse in the leading sub-field. SOLUTION: A 1st sustain driver initializes all discharge cells by simultaneously applying an erase pulse EP to row electrodes X1-Xn of a plasma display(PDP). Next, in a pixel data writing process Wc executed in each sub-field SF1-SF14, an address driver generates pixel data pulses having a voltage according to logic levels of pixel drive data bits supplied from memory, and sequentially applies them to column electrodes D1-m for each row. And in the pixel data writing process Wc, the later the sub-field is in one field period, the longer the pulse width of the applied scanning pulses is made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for driving a plasma display panel.

[0002]

2. Description of the Related Art In recent years, as display devices have become larger, thinner display devices have been required, and various thin display devices have been put into practical use. An AC (AC discharge) type plasma display panel (hereinafter, referred to as a PDP) has attracted attention as one of such thin display devices. The PDP includes a plurality of column electrodes (address electrodes) and a plurality of row electrodes arranged so as to cross the column electrodes. Each row electrode pair and column electrode is covered with a dielectric layer with respect to the discharge space, and has a structure in which a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .

At this time, since each discharge cell emits light by utilizing a discharge phenomenon, it has only two states of “light emission” and “non-light emission”. Therefore, in such a PDP, a subfield method is used to realize a halftone luminance display based on a video signal. In the sub-field method, one field period is divided into N sub-fields, and each sub-field is used to weight each bit digit of pixel data (N-bit data obtained by sampling a video signal corresponding to each pixel). Light emission driving is performed by allocating a corresponding light emission period (number of light emission).

For example, as shown in FIG. 1, when one field period is divided into six subfields SF1 to SF6, SF1: 1 SF2: 2 SF3: 4 is assigned to each of these subfields SF1 to SF6. SF4: 8 SF5: 16 SF6: 32

[0005] Here, for example, when a display of luminance "32" is performed, SF6 in subfields SF1 to SF6 is used.
Only this causes each discharge cell to emit light. When the display of the luminance “31” is performed, the subfield SF6
Are emitted in the other subfields SF1 to SF5 except for. As described above, the total number of light emission performed in the subfields SF1 to SF6 within one field period enables the halftone luminance expression in 64 steps.

[0006] However, as shown in FIG.
In the case where the display of 32 "is performed and the case where the display of the luminance" 31 "is performed, the period in the light emitting state and the period in the non-light emitting state in one field period are opposite to each other. In other words, during the period in which the discharge cells to emit light at the luminance "32" are emitting light within one field period, the discharge to emit light at the luminance "31" occurs. The cells are in a non-light-emitting state, while the discharge cells to be emitted at a luminance of "32" are in a non-light-emitting state while the discharge cells to be emitted at a luminance "31" are emitting light. While viewing an image in which the display area of 32 "and the display area of luminance" 31 "are adjacent to each other, the discharge cells existing in the display area of luminance" 32 "change from the non-light emitting state to the light emitting state. Table of luminance "31" at the transition timing When the user shifts his / her gaze to the display area, only the non-light emitting state of the two is continuously viewed, and a dark line is visually recognized on the boundary between the two display areas, which is a false contour having no relation to the pixel data. And appear on the screen, deteriorating the display quality.

Further, as described above, since the PDP utilizes a discharge phenomenon, it is necessary to perform a discharge (with light emission) irrelevant to the display content, thereby lowering the image contrast. There was a problem. Furthermore, at present, when commercializing such a PDP, realizing low power consumption is a general problem.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a plasma display capable of realizing suppression of false contour, low power consumption, and high contrast with stable operation. It is an object to provide a method for driving a panel.

[0009]

According to the present invention, there is provided a driving method of a plasma display panel, wherein each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. Wherein the display period of one field is divided into N sub-fields, and the display period of one field is divided into N sub-fields. A reset step of applying a reset pulse for generating a reset discharge for initializing all the discharge cells to a non-light emitting cell state only in the subfield of the section;
A pixel data writing step of applying a scan pulse for generating a selective writing discharge for causing the non-light emitting cell to transition to a light emitting cell state in one subfield corresponding to pixel data of the N subfields; Performing a sustaining pulse for generating a sustaining discharge for causing only the light emitting cells to emit light in the number of times corresponding to the weight of the subfield in each of the N subfields. The pulse width of the scan pulse in the subfield after the display period is longer than the pulse width of the scan pulse in the first subfield.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel to emit light based on a driving method according to the present invention. As shown in FIG. 2, such a plasma display device includes:
A / D converter 1, drive control circuit 2, data conversion circuit 3,
A drive unit including a memory 4, an address driver 6, a first sustain driver 7, and a second sustain driver 8,
And a PDP 10 as a plasma display panel.

The PDP 10 has m column electrodes D _{1 to} D _m as address electrodes, and n row electrodes X _{1 to} X _n and a row electrode Y _1, which are arranged to cross each of the column electrodes. ~
Y _n . At this time, a pair of the row electrode X and the row electrode Y forms a row electrode corresponding to one row in the PDP 10. The column electrodes D and the row electrodes X and Y are covered with a dielectric layer with respect to the discharge space, and have a structure in which a discharge cell corresponding to one pixel is formed at an intersection between each row electrode pair and a column electrode. I have.

The A / D converter 1 samples an input analog input video signal in response to a clock signal supplied from the drive control circuit 2 and converts the sampled video signal into, for example, an 8-bit pixel corresponding to each pixel. The data is converted to data D and supplied to the data conversion circuit 3. Since the input video signal is obtained by subjecting the original video signal to gamma correction processing, the pixel data D obtained by sampling the input video signal is also subjected to gamma correction processing. It can be said that there is.

The data conversion circuit 3 performs a luminance adjustment process and a multi-gradation process on the 8-bit pixel data D, and then drives each discharge cell of the PDP 10 to emit light in each of the 14 subfields. Is converted to 14-bit conversion pixel data HD and supplied to the memory 4. The operation of the data conversion circuit 3 will be described later. The memory 4 sequentially writes the converted pixel data HD according to a write signal supplied from the drive control circuit 2. At this time, the converted pixel data HD for one screen (n rows, m columns)
_When the writing of the _11-nm is completed, the memory 4 stores the pixel driving data bits DB14 _11-nm and DB1 obtained by dividing the converted pixel data HD _11-nm for one screen into each bit digit.
3 _11-nm ,..., DB2 _11-nm , DB1 _11-nm , that is, DB14 _11-nm : the 14th bit of the converted pixel data HD _11-nm DB13 _11-nm : the converted pixel data HD ₁₁ 13 bit DB 12 _11-nm of _-nm: 12th bit DB 11 _11-nm of the converted pixel data HD _11-nm: the eleventh bit DB 10 _11-nm of the converted pixel data HD _11-nm: the converted pixel data HD _11-nm of the 10 bit DB9 _11-nm: the ninth bit DB8 _1-nm the converted pixel data HD _11-nm: the eighth bit DB7 _11-nm of the converted pixel data HD _11-nm: the converted pixel data HD _11-nm of the 7 bit DB 6 _11-nm: the converted pixel data HD _11-nm sixth bit DB 5 _11-nm: the converted pixel data HD _11-nm fifth bit DB4 _11-nm: the converted pixel data HD _11-nm of the fourth bit DB3 _11-nm: the third bit DB2 _11-nm of the converted pixel data HD _11-nm: the converted pixel data D _11-nm of the second bit DB1 _11-nm: regarded as the first bit of the converted pixel data HD _11-nm, in response to the supplied read signal from the drive control circuit 2, the pixel driving data bits DB 14 _{11 -nm} , D
B13 _11-nm ,..., DB2 _11-nm , DB11 _-nm
The data is sequentially read out for each row and supplied to the address driver 6.

The drive control circuit 2 synchronizes with the horizontal and vertical synchronizing signals in the input video signal, and controls the A / D converter 1
And write and read signals for the memory 4 are generated. Further, the drive control circuit 2 controls the PDP 10 according to the light emission drive format as shown in FIG.
Is supplied to the address driver 6, the first sustain driver 7, and the second sustain driver 8, respectively.

In the light emission drive format shown in FIG. 3, light emission drive is performed on the PDP 10 by dividing a display period of one field into 14 subfields SF1 to SF14. In each subfield, only the pixel data writing process Wc in which pixel data is written into each discharge cell of the PDP 10 to set “light emitting cells” and “non-light emitting cells” and only the above “light emitting cells” are shown. A light emission sustaining process Ic for maintaining the light emitting state is performed by causing light emission for the number of times (period) shown in 3. Here, the ratio of the number of light emitting times executed in the light emitting sustaining process Ic of each subfield is as follows. Light emission sustaining process Ic of subfield SF1
When the number of times of light emission executed in is set to “1”, SF14: 39 SF13: 35 SF12: 32 SF11: 28 SF10: 25 SF9: 22 SF8: 19 SF7: 16 SF6: 13 SF5: 10 SF4: 8 SF3: 5 SF2 : 3 SF1: 1.

At this time, each of the subfields SF1 to SF1
The gamma correction process performed on the input pixel data D as described above is canceled by setting the ratio of the number of times of light emission to be executed in step 4 to be non-linear, that is, by setting the inverse gamma ratio to Y = X ^2.2 . In the light emission drive format shown in FIG. 3, only the first subfield SF14 is used.
A simultaneous reset process Rc for initializing the wall charge amount in all the discharge cells of the PDP 10 is performed, and an erasing process E for simultaneously erasing wall charges in all the discharge cells is performed only in the last subfield SF1.

Each of the address driver 6, the first sustain driver 7, and the second sustain driver 8 controls the PDP 10 according to the light emission drive format shown in FIG.
Drive pulses are generated in accordance with the timing signal supplied from the drive control circuit 2 to drive
The column electrodes D ₁ to D _m of DP10, row electrodes X ₁ to X _n and Y ₁ ~
Y _n .

[0018] Figure 4, the address driver 6 is applied to the first sustain driver 7 and second sustain driver 8 each by the PDP10 column electrodes D ₁ to D _m, row electrodes X ₁ to X _n and Y ₁ to Y _n FIG. 4 is a diagram showing application timings of various drive pulses. As shown in FIG. 4, first, in the simultaneous reset process Rc executed only in the first subfield SF14 of one field display period, the first sustain driver 7 and the second sustain driver 8
A reset pulse RP _{x is} applied to the row electrodes X and Y of DP10, respectively.
And RP _Y are applied simultaneously. Thereby, PDP10
A reset discharge is performed on all the discharge cells in the discharge cells, and wall charges are forcibly formed in each discharge cell (R ₁ ). Immediately after that, the first sustain driver 7 sets the erase pulse EP to P
By simultaneously applying the row charges to the row electrodes X _{1 to} X _n of the DP 10, an erasing discharge for erasing the wall charges formed in all the discharge cells is generated (R ₂ ). Therefore, according to the execution of the simultaneous reset process Rc, all of the discharge cells in the PDP 10 are initialized to "non-light-emitting cells" having no wall charge.

Next, in the pixel data writing process Wc performed in each subfield, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logic level of the pixel driving data bit DB supplied from the memory 4. Generate
This is sequentially applied to the column electrodes D _1-m every row. For example, in the pixel data writing process Wc in the subfield SF14, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logic level of each of the pixel drive data bits DB14 _11-nm , Are sequentially applied to the column electrodes D _{1 -m} . That application, as shown in FIG. 4, first, the pixel data pulse group DP14 ₁ of m pixel data pulses corresponding to the first row of the DB 14 _11-nm to the column electrodes D _1-m and, then, simultaneously applying a pixel data pulse group DP14 ₂ of m pixel data pulses corresponding to the second row in the column electrode D _1-m. In the same manner, the pixel data pulse group for each row DP14 ₃ ~DP1
4 _n are sequentially applied to the column electrodes D _{1 -m} . The second sustain driver 8 generates a negative scan pulse SP at the same timing as the application timing of each of the pixel data pulse groups DP, and sends this to the row electrodes Y ₁ to Y _{n as} shown in FIG. Are sequentially applied. At this time, discharge (selective write discharge) occurs only in the discharge cell at the intersection of the "row" to which the scan pulse SP is applied and the "column" to which the high-voltage pixel data pulse is applied, and the discharge cell A wall charge is formed therein. Therefore, the discharge cells initialized to the “non-light emitting cell” state in the simultaneous resetting process Rc change to the “light emitting cell”. In the discharge cells formed in the "column" to which the low-voltage pixel data pulse is applied, even if the scan pulse SP is applied, the above-described selective write discharge does not occur. Hold. That is, the discharge cells in the “light emitting cell” state maintain the “light emitting cell” state, and the discharge cells in the “non-light emitting cell” state maintain the “non-light emitting cell” state.

Here, in the present invention, the pulse width of the scan pulse SP applied in the pixel data writing process Wc of each subfield is made longer in the later subfield in one field period. The application cycle of the scan pulse SP is also longer in the rear subfield. The reason will be described later. Then, the light emission sustain process Ic is executed in each subfield, a first sustain driver 7 and second sustain driver 8 each of which row electrodes sustain pulses IP _X and IP _Y of positive polarity as shown in FIG. 4 It applied alternately to X ₁ to X _n and Y ₁ to Y _n. Here, the light emission sustaining process I of each subfield
The number of sustain pulses IP applied in c is SF14: 39 SF13: 35 SF12: 32 SF11: 28 SF10: 25 SF9: 22 SF8: 19 SF7: 16 SF6: 13 SF5: 10 SF4: 8 SF3: 5 SF2: 3 SF1: 1.

By the application of the sustain pulse IP as described above, only the discharge cells holding the wall charges, ie, the "light emitting cells" sustain discharge each time these sustain pulses IP _X and IP _Y are applied. Light emission is repeated the number of times (period) and the light emission state is maintained. Therefore, according to the light emission sustaining process Ic of the subfield SF1, light emission display for a low luminance component in the input video signal is performed, while, according to the light emission sustaining process Ic of the subfield SF14, light emission display for the high luminance component is performed. It is done.

At this time, the pulse width of each of the sustain pulses IP _X and IP _Y is set longer for a subfield to which the number of times of light emission is smaller as described above. For example, the pulse width W _S2 of the pulse width W _S1, SF2 of sustain pulses IP _X and IP _Y in the most number of times of light emission subfields SF1 assignment little, ..., the pulse width W _S13 in SF13, and most pulse width W _S14 each sustain pulses IP _X and IP _Y in the subfields SF14 allocation of the number of emissions is large, the _{W S1> W S2> ···· W} S13> W S14 the relationship.

[0023] Thus, in the subfield allocation is less number of light emissions, the reason for lengthening the pulse width of the sustain pulses IP _X and IP _Y are such as follows. If the number of times of light emission is small, that is, if the number of sustain discharges is small, the amount of priming particles formed in the discharge cells becomes very small, so that a sustain discharge is generated after the application of the positive sustain pulse IP. Delay time is longer.
At this time, even after the sustain discharge is generated, unless the sustain pulse IP of the positive polarity is continuously applied for a predetermined period, the wall charges in the discharge cells cannot be satisfactorily held.

Therefore, in the subfield to which the number of times of light emission is small, the pulse width is made longer than that of the sustain pulse IP in the subfield to which the number of times of light emission is large by the amount considering the increase in the delay time as described above. It is. Incidentally, with the extension of these sustain pulses IP _X and IP _Y each pulse width, the subfield allocation is less number of light emissions, and long application period between both sustain pulses.

For example, the application period T _S1 between the sustain pulses IP _X and IP _Y in the subfield SF1 to which the number of times of light emission is least assigned is the application period T _S2 in the SF2,.
Application period T _S13 at 13, and most application period T _S14 each between sustain pulses IP _X and IP _Y of assignment often subfield SF14 of number of _{emissions, T S1> T S2> ····} T S13> T _S14 is set.

Finally, as shown in FIG. 4, in the erasing step E performed only in the last subfield SF1 of one field, the second sustain driver 8
And generating an erase pulse EP and applies the row electrodes Y ₁ to Y _n, respectively. In response to the application of the erase pulse EP, PD
An erase discharge is generated in all the discharge cells at P10, and the wall charges remaining in all the discharge cells disappear. That is, by such an erasing discharge, all the discharge cells in the PDP 10 become “non-light emitting cells”.

With the above operation, the plasma display apparatus shown in FIG. 2 selectively executes one of the fifteen-step light emission driving according to the input video signal as shown in FIG. The black circles in FIG. 5 indicate that a selective writing discharge is generated in the pixel data writing process Wc in the subfield. Further, the black circles and the white circles indicate that light emission accompanying the sustain discharge occurs in the light emission sustaining step Ic in the subfield.

Therefore, according to these 15 stages of light emission driving, [0: 1: 2: 3: 4: 6: 9: 13: 19: 29: 44: 68:
106: 165: 256] It is possible to realize halftone luminance display corresponding to the input video signal in the following 15 steps. However, the pixel data D obtained based on the input video signal expresses 8 bits, that is, 256 levels of halftones. Therefore, data conversion is performed by the data conversion circuit 3 shown in FIG. 2 so that the halftone display of 256 steps is performed in a pseudo manner even by the 15-step gradation drive.

FIG. 6 is a diagram showing the internal configuration of the data conversion circuit 3. In FIG. 6, an ABL (automatic brightness control) circuit 31 controls the A / D so that the average brightness of an image displayed on the screen of the PDP 10 falls within a predetermined brightness range.
Adjusts the brightness level for pixel data D for each pixel sequentially supplied thereto from the converter 1, and supplies the time resulting luminance adjusted pixel data D _BL to the first data conversion circuit 32. This luminance level adjustment is performed before performing the inverse gamma correction by setting the ratio of the number of times of light emission to non-linear as described above.
That is, the ABL circuit 31 automatically adjusts the luminance level of the pixel data D according to the average luminance of the inverse gamma converted pixel data obtained by performing the inverse gamma correction on the pixel data D. This prevents the display quality from deteriorating due to the brightness adjustment.

FIG. 7 is a diagram showing the internal configuration of the ABL circuit 31. In FIG. 7, the level adjustment circuit 310
Outputs the luminance adjusted pixel data D _BL obtained by adjusting the level of the pixel data D in accordance with the average brightness determined by the average brightness detection circuit 311 to be described later. The data conversion circuit 312 converts the luminance adjustment pixel data _DBL into an inverse gamma characteristic (Y = X) having a non-linear characteristic as shown in FIG.
^The data converted to ^2.2 ) is supplied to the average luminance level detection circuit 311 as inverse gamma conversion pixel data Dr. That is, by performing inverse gamma correction processing on the luminance adjustment pixel data _DBL , pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal from which gamma correction has been canceled is restored. The average luminance detection circuit 311 calculates the average luminance of the inverse gamma conversion pixel data Dr and supplies the average luminance to the level adjustment circuit 310. Further, the average luminance detection circuit 311 selects a luminance mode capable of driving the PDP 10 to emit light at an average luminance corresponding to the average luminance from among luminance modes 1 to 4 as shown in FIG. The luminance mode signal LC indicating the luminance mode is supplied to the drive control circuit 2. Here, the drive control circuit 2 operates the subfields SF14 to SF as shown in FIG. 3 according to the luminance mode signal LC as shown in FIG.
The number of times to perform sustain discharge in each sustain emission step Ic of F1 is set.

First data conversion circuit 32 shown in FIG.
Is the ABL circuit 31 8 bits into 14 × 16/255 (= 224 /255) on the basis of but such conversion characteristics as shown in FIG. 10 the luminance adjusted pixel data D _BL of 8 bits supplied from (0 It is converted into the converted pixel data HD _p 224), and supplies it to the multi-gradation processing circuit 33. Specifically, 8-bit (0 to 255) luminance adjustment pixel data _DBL is converted according to the conversion tables shown in FIGS. 11 and 12 based on the conversion characteristics. That is, the conversion characteristics are set according to the number of bits of the luminance adjustment pixel data _DBL , the number of bits compressed by the multi-gradation processing described later, and the number of display gradations. As described above, the first data conversion circuit 32 is provided before the multi-gradation processing, and the conversion is performed in accordance with the number of display gradations and the number of compression bits by the multi-gradation. _BL is divided into an upper bit group (corresponding to multi-gradation pixel data) and a lower bit group (data to be truncated: error data) at a bit boundary,
A multi-gradation process is performed based on this signal. By the data conversion by the first data conversion circuit 32 as described above, the occurrence of luminance saturation due to the multi-grayscale processing in the subsequent stage and the occurrence of a flat portion of the display characteristic that occurs when the display grayscale is not at the bit boundary (that is, the grayscale) The occurrence of distortion is prevented.

FIG. 13 is a diagram showing the internal configuration of the multiple gradation processing circuit 33. As shown in FIG. 13, the multiple gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350. Error diffusion processing circuit 330
Data separation circuit 331 in the error data to the lower two bits in the converted pixel data HD _P of 8 bits supplied from the first data conversion circuit 32, separates the upper 6 bits as display data. Adder 332, and the lower two bits of the converted pixel data HD in _P as such error data, a delay output from the delay circuit 334, the coefficient multiplier 33
5 is added to the multiplication output of FIG.
To supply. The delay circuit 336 generates a signal obtained by delaying the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data as a delay addition signal AD ₁ , the coefficient multiplier 335 and the delay circuit 337.
Supply each. The coefficient multiplier 335 supplies the multiplication result obtained by multiplying the delayed addition signal AD ₁ by a predetermined coefficient value K ₁ (for example, “7/16”) to the adder 332. Delay circuit 337, further the delay addition signal AD ₁ - supplied to the delay circuit 338 which is delayed by (1 horizontal scanning period the delay time D × 4) comprising time as a delay addition signal AD _2. The delay circuit 338 generates a signal obtained by further delaying the delay addition signal AD ₂ by the delay time D,
It is supplied to the coefficient multiplier 339 as D ₃ . Further, the delay circuit 338 is supplied to the coefficient multiplier 340 to a delayed such delay addition signal AD ₂ by further the delay time D × 2 becomes time period as a delay addition signal AD _4. Further, the delay circuit 338 is supplied to the coefficient multiplier 341 and a delayed such delay addition signal AD ₂ by further the delay time D × 3 becomes time period as a delay addition signal AD _5. The coefficient multiplier 339 adds a predetermined coefficient value K ₂ to the delayed addition signal AD _3.
(For example, “3/16”) is supplied to the adder 342. The coefficient multiplier 340 supplies the multiplication result obtained by multiplying the delay addition signal AD ₄ by a predetermined coefficient value K ₃ (for example, “5/16”) to the adder 342. Coefficient multiplier 341, a predetermined coefficient value K to the delay addition signal AD _5
The result of multiplication by ₄ (for example, “1/16”) is supplied to the adder 342. The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340 and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the delay time D and supplies it to the adder 332. The adder 332, the converted pixel data HD lower 2 bits in the _P, a delayed output from the delay circuit 334, logic level when there is no carry when the sum of the multiplication output of the coefficient multiplier 335 A carry-out signal C _O having a logical level “1” is generated when the carry is “0”, and is supplied to the adder 333. The adder 333, the display data composed of upper 6 bits of the converted pixel data HD in _P, and outputs obtained by adding the carry-out signal C _O of 6 bits as the error diffusion processing pixel data ED. In other words, the number of bits of the error diffusion processing pixel data ED is becoming smaller than the converted pixel data HD _P.

The operation of the error diffusion processing circuit 330 will be described below. For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 14, first, the pixel G (j, k-1), the pixel G (j-1, k-1) on the upper left, the pixel G (j-1, k) on the upper right, and the pixel G (j-1, k + 1) on the upper right Error data corresponding to each, that is, error data corresponding to pixel G (j, k-1): delayed addition signal A
D1 Error data corresponding to _one pixel G (j-1, k + 1): delayed addition signal AD Error data corresponding to _three pixels G (j-1, k): delayed addition signal A
D ₄ pixel G (j-1, k- 1) to the error data corresponding: a delay addition signal AD ₅ each weighted addition with a predetermined coefficient value K ₁ ~K ₄ as mentioned above. Then, the addition result, the lower two bits of the converted pixel data HD _P, i.e. pixel G (j, k) by adding the error data corresponding to the carry-out signal C _O of 1 bit obtained when the Top 6 of the converted pixel data HD in _P a
The bit amount, that is, the value added to the display data corresponding to the pixel G (j, k) is referred to as error diffusion processed pixel data ED.

With this configuration, the error diffusion processing circuit 33
In 0, the display data upper 6 bits in the converted pixel data HD _P, captures the remaining lower two bits as error data, the peripheral pixels {G (j, k-1 ), G (j-1, k + 1), G (j-1, k),
G (j−1, k−1) 誤差 The weighted sum of the error data for each is reflected in the display data.
With this operation, the lower two pixels in the original pixel {G (j, k)}
The luminance of the bits is pseudo-expressed by the peripheral pixels. Therefore, with the number of bits smaller than 8 bits, that is, the display data of 6 bits, the luminance gradation equivalent to the pixel data of 8 bits is obtained. It becomes possible.

If the error diffusion coefficient value is constantly added to each pixel, noise due to the error diffusion pattern may be visually recognized, thereby deteriorating the image quality. Therefore, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field as in the case of the dither coefficient described later. The dither processing circuit 350 performs dither processing on the 6-bit error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby obtaining the error diffusion processing pixel data ED.
Generating a multi-gradation processing pixel data D _S which also reduces the number of bits to 4 bits while maintaining a comparable luminance gradation level. In the dither processing, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when gradation display corresponding to 8 bits is performed using upper 6 bits of pixel data of 8 bits of pixel data, four pixels adjacent to each other in the left, right, up, and down are set as one set, and each of the one set Four dither coefficients a to d each having a different coefficient value are assigned to each piece of pixel data corresponding to the pixel and added. According to such dither processing, 4 pixels are used for 4 pixels.
A combination of two different intermediate display levels will occur. Therefore, even if the number of bits of the pixel data is 6 bits, the luminance gradation level that can be expressed is four times, that is, halftone display equivalent to 8 bits is possible.

However, if the dither patterns of the dither coefficients a to d are constantly added to each pixel,
Noise due to the dither pattern may be visually recognized, and image quality may be impaired. Therefore, the dither processing circuit 350 changes the dither coefficients a to d to be assigned to each of the four pixels for each field.

FIG. 15 is a diagram showing the internal configuration of the dither processing circuit 350. In FIG. 15, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four pixels adjacent to each other, and sequentially supplies these to an adder 351. For example, as shown in FIG. 16, a pixel G (j, k) and a pixel G (j, k + 1) corresponding to the j-th row,
Pixel G (j + 1, k) and pixel G (j + 1, k) corresponding to the (j + 1) th row
k + 1) for each of the four pixels, four dither coefficients a,
b, c, and d are generated respectively. At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.

That is, in the first first field, pixel G (j, k): dither coefficient a pixel G (j, k + 1): dither coefficient b pixel G (j + 1, k): dither coefficient c Pixel G (j + 1, k + 1): dither coefficient d In the next second field, pixel G (j, k): dither coefficient b pixel G (j, k + 1): dither coefficient a pixel G ( j + 1, k): dither coefficient d pixel G (j + 1, k + 1): dither coefficient c In the next third field, pixel G (j, k): dither coefficient d pixel G (j, k) +1): dither coefficient c pixel G (j + 1, k): dither coefficient b pixel G (j + 1, k + 1): dither coefficient a Then, in the fourth field, pixel G (j, k) : Dither coefficient c Pixel G (j, k + 1): Dither coefficient d Pixel G (j + 1, k): Dither coefficient a Pixel G (j + 1, k + 1): Dither coefficient b , And dither coefficients a to d are circulated repeatedly and supplied to an adder 351. The dither coefficient generation circuit 352 repeatedly performs the operations of the first to fourth fields as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated.

The adder 351 is connected to the error diffusion processing circuit 3
The pixels G (j, k) and G (j, k +) supplied from
1), the pixel G (j + 1, k), and the error diffusion processing pixel data ED corresponding to each of the pixels G (j + 1, k + 1), and the dither coefficient assigned to each field as described above. a to d are added to each other, and the obtained dither added pixel data is supplied to the upper bit extraction circuit 353.

For example, in the first field shown in FIG. 16, the error diffusion processing pixel data ED + corresponding to the pixel G (j, k)
Error diffusion processing pixel data ED corresponding to dither coefficient a and pixel G (j, k + 1)
+ Dither coefficient b, error diffusion processed pixel data ED corresponding to pixel G (j + 1, k)
+ Dither coefficient c, error diffusion processed pixel data E corresponding to pixel G (j + 1, k + 1)
Each of the D + dither coefficient d is sequentially supplied to the upper bit extraction circuit 353 as dither added pixel data.

The upper bit extracting circuit 353 extracts until the upper 4 bits of such dither-added pixel data, and supplies the second data conversion circuit 34 shown in FIG. 6 as the multi-gradation pixel data D _S . Therefore, a possible value as a multi-gradation pixel data D _S is such is shown in FIG. 17 "
0000 becomes 15 kinds of "~" 1110 ". The second data conversion circuit 34 in accordance with such a conversion table multi-gradation pixel data D _S of such 4 bits shown in FIG. 17, 1
It is converted to 4-bit conversion pixel data HD.

Here, the logic level "1" described in the converted pixel data HD indicates that the selective writing discharge is to be performed in the pixel data writing process Wc of the subfield corresponding to the bit digit. ing. That is, the address driver 6 applies a high-voltage pixel data pulse to the column electrode D of the PDP 10 only in the pixel data writing process Wc of the subfield corresponding to the bit digit of the logic level “1” in the converted pixel data HD. Therefore, the selective write discharge is generated only in the subfield indicated by the black circle in FIG.

At this time, in each of the fifteen types of converted pixel data HD as shown in FIG. 17, the bit digit at which the logic level is "1" is at most one (in 14 bits).
It is. That is, during the one-field display period, the pixel data writing process Wc is performed 14 times by each of the subfields SF14 to SF1, in which the selective writing discharge is actually generated at most once. It is. Therefore, no sustain discharge is generated in the light emission sustaining process Ic of each subfield existing from the first subfield SF14 to the execution of the selective writing discharge, and the discharge cells are in a non-light emitting state. However, a sustain discharge is generated in the light emission sustaining process Ic in each of the subfields in which the selective writing discharge is performed and the subfields existing thereafter, and as shown by white circles in FIG.
The light emission state continues until the end of one field. That is, a light emission pattern in which the discharge cell changes from a light emitting state to a non-light emitting state within one field period is prohibited. Thereby, as shown in FIG.
Since there is no light emission pattern in which the period in which the discharge cell is in the light emitting state and the period in which the discharge cell is in the non-light emitting state are reversed, the generation of the false contour is suppressed.

In addition, since the reset discharge accompanied by strong light emission need not be performed only once in one field period as shown in FIGS. Can be suppressed. Further, as described above, the selective write discharge generated within one field period is at most one time as shown by the black circle in FIG. 17, so that the power consumption can be suppressed.

Further, in the present invention, as described above,
The pulse width of each of the scan pulse SP and the pixel data pulse DP applied in the pixel data writing process Wc of each subfield is made longer in the later subfield in one field period. For example, as shown in FIG.
The pulse width W _a1 of the scan pulse SP in the last subfield SF1 of one field, the pulse width W _a2 in SF2,
.., The pulse width W _a13 in SF13 and the pulse width W _{a14 in SF14 are} respectively W _a1 > W _a2 > W _a3 >... W _a13 > W _a14 .

In addition, the application cycle of the scanning pulse SP is set longer in the rear subfield. For example, the application period T _a1 of the scan pulse SP in the last subfield SF1 of one field, the application period T _{a2 in} SF2,..., The application period T _a13 in SF13, and SF1
Application period T _a14 each 4 has a _{T a1> T a2> T a3} > ···· T a13> T a14.

[0047] At this time, as the subfield of the rear of one field, the reason for lengthening the pulse width W _a of the scan pulse SP is such as follows. 15 as shown in FIG.
Among the various types of grayscale driving, in grayscale driving for displaying a low-luminance image, for example, in the second grayscale driving, a discharge cell is generated between the time when a reset discharge is generated in the first subfield SF14 and the time until the subfield SF2. No discharge occurs in the interior. Therefore, the priming particles formed in the discharge cells by the reset discharge decrease with time, and become small at the time of execution of the pixel data writing process Wc in the subfield SF1. Here, when the amount of the priming particles is sufficient at the time of execution of the pixel data writing process Wc, the selective writing discharge immediately occurs in response to the simultaneous application of the high-voltage pixel data pulse DP and the scanning pulse SP. However, if the amount of the priming particles is small, a delay occurs before the selective writing discharge occurs. Further, even after the selective writing discharge is generated, the wall charges cannot be formed in the discharge cells unless the high-voltage pixel data pulse DP and the scanning pulse SP are continuously applied for a predetermined period. .

Therefore, in the present invention, the pulse widths of the pixel data pulse DP and the scan pulse SP in the later sub-field during one field period are equal to those in the first sub-field by taking into account the delay time as described above. , The pixel data writing operation is stabilized. In the above embodiment, the pulse width W _a1 of the scan pulse SP in the last subfield SF1 of one field, the pulse width W _a2 in SF2,.
, The pulse width W _a13 in SF13 and the pulse width W _{a14 in SF14 are} respectively set to a relationship of W _a1 > W _a2 >... W _a13 > W _a14 , and accordingly, the last subfield of one field application period of the scanning pulse SP in SF1 T _a1,
Application period T _a2 in SF2, · · · ·, application period T _a13 in SF13, and the application period T _a14 each with SF14, although the _{T a1> T a2> ···· T} a13> T a14 However, it is not always necessary to make the pulse width and the application cycle of the scanning pulse SP different for each subfield.

For example, a scanning pulse for each subfield
SP pulse width W_aAnd the application period T_aTo W_a1= W_a2= W_a3= W_a4= W_a5> W_a6= W_a7= W_a8= W_a9= W
_a10= W_a11= W_a12= W_{a1 Three}= W_a14 T_a1= T_a2= T_a3= T_a4= T_a5> T_a6= T_a7= T_a8= T_a9= T
_a10= T_a11= T_a12= T_{a1 Three}= T_a14 Similarly, the sustain pulse for each subfield
IP_XAnd IP_YApplication period T between_SAnd each pulse width W_S
Also, W_S1= W_S2= W_S3= W_S4= W_S5> W_S6= W_S7= W_S8= W_S9= W
_S10= W_S11= W_S12= W_{S1 Three}= W_S14 T_S1= T_S2= T_S3= T_S4= T_S5> T_S6= T_S7= T_S8= T_S9= T
_S10= T_S11= T_S12= T_{S1 Three}= T_S14 It may be a relationship.

Further, in the above embodiment, the selective write discharge is generated in any one of the pixel data write steps Wc in the subfields SF1 to SF14, but the priming remaining in the discharge cells is performed. If the amount of the particles is small, the selective writing discharge may not be normally generated even if the scanning pulse SP and the high-voltage pixel data pulse are applied simultaneously.

Therefore, instead of the light emission drive pattern shown in FIG. 17, a light emission drive pattern as shown in FIG. 18 may be employed so that the selective write discharge can be reliably generated. In the light emission drive shown in FIG.
In the pixel data writing process Wc of each of two consecutive subfields, the first and second selective writing discharges are continuously generated (indicated by black circles). According to such an operation, even if the first selective writing discharge is not satisfactorily performed, the priming particles are formed by this discharging, so that the second selective writing discharge is normally performed. Become. In short, after performing the first selective write discharge,
By performing the second selective write discharge again in at least one of the subfields subsequent to the subfield, the selective write discharge is reliably generated.

[0052]

As described in detail above, in the present invention,
Only in the first subfield of one field period, a reset discharge is performed to initialize all the discharge cells of the plasma display panel to the state of the non-light emitting cells, and the non-light emitting cells are replaced with the light emitting cells in one subfield according to the pixel data. A selective write discharge to be changed to a state is generated. At this time, the pulse width of the scanning pulse applied to generate the selective writing discharge is made longer in a later subfield in one field period.

Therefore, according to the driving method of the plasma display panel according to the present invention, it is possible to suppress false contours, reduce power consumption, and increase contrast with stable operation.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a light emission drive format according to a subfield method.

FIG. 2 is a diagram showing a schematic configuration of a plasma display device that drives a PDP 10 to emit light based on a driving method according to the present invention.

FIG. 3 is a diagram showing a light emission drive format based on a drive method according to the present invention.

FIG. 4 is a diagram showing application timings of various driving pulses applied to the PDP 10 in one field.

FIG. 5 is a view showing all patterns of light emission driving performed based on the light emission drive format shown in FIG. 3;

FIG. 6 is a diagram showing an internal configuration of the data conversion circuit 3.

FIG. 7 is a diagram showing an internal configuration of an ABL circuit 31;

FIG. 8 is a diagram illustrating conversion characteristics in the data conversion circuit 312.

FIG. 9 is a diagram illustrating a correspondence relationship between a luminance mode and a ratio of the number of times of light emission performed in a light emission sustaining process of each subfield.

FIG. 10 is a diagram showing conversion characteristics in a first data conversion circuit 32;

11 is a diagram illustrating an example of a conversion table in the first data conversion circuit 32. FIG.

FIG. 12 is a diagram showing an example of a conversion table in the first data conversion circuit 32.

FIG. 13 is a diagram showing an internal configuration of a multi-gradation processing circuit 33.

14 is a diagram for explaining an operation of the error diffusion processing circuit 330. FIG.

FIG. 15 is a diagram showing an internal configuration of a dither processing circuit 350.

FIG. 16 is a diagram for explaining the operation of the dither processing circuit 350;

FIG. 17 is a diagram showing an example of all patterns of light emission driving performed based on the light emission driving format shown in FIG. 3 and an example of a conversion table used in the second data conversion circuit 34 when performing this light emission driving. is there.

18 shows all patterns of light emission drive performed based on the light emission drive format shown in FIG. 6, and another example of a conversion table used in the second data conversion circuit 34 when performing this light emission drive. FIG.

[Explanation of Signs of Main Parts]

 2 Drive control circuit 3 Data conversion circuit 6 Address driver 7 First sustain driver 8 Second sustain driver 10 PDP

Claims (5)

[Claims] 1. A plasma forming a discharge cell corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A method of driving a display panel, comprising: dividing a display period of one field into N subfields, and excluding all the discharge cells only in a head subfield among the N subfields. A reset step of applying a reset pulse for generating a reset discharge for initializing a light emitting cell to a state of the light emitting cell; and setting the non-light emitting cell to a light emitting cell in one of the N subfields according to pixel data. A pixel data writing step of applying a scanning pulse for generating a selective writing discharge for transitioning to a state; A sustaining step of applying a sustaining pulse that causes a sustaining discharge to cause only the light emitting cells to emit light by the number of times of light emission corresponding to the weighting of the subfield. A method for driving a plasma display panel, wherein a pulse width of a scan pulse is longer than a pulse width of the scan pulse in a first subfield. 2. A pulse width of the sustain pulse in a subfield after a display period of the one field is longer than a pulse width of the sustain pulse in a first subfield. Driving method of plasma display panel. 3. A method according to claim 1, further comprising: generating a first selective write discharge for changing the discharge cell to a light emitting cell state in one of the N subfields according to pixel data. 2. The method according to claim 1, wherein a second selective write discharge is generated in at least one of the sub-fields executed after the one sub-field. 4. An erasing step for generating an erasing discharge for setting all the discharge cells to the non-light emitting cells only in a last subfield of the subfields. A method for driving a plasma display panel according to claim 1. 5. An N + 1 gray scale display by causing the light emitting cells to emit light in the light emission sustaining step in each of n (n is 0 to N) consecutive subfields of the N subfields. 2. The method for driving a plasma display panel according to claim 1, wherein: