JP2000275622A - Liquid crystal panel and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To integrate a liquid crystal panel with a polarizing plate without deterioration in the polarizing plate and to improve the contrast of a liquid crystal display device by applying a heat radiating film on the face of an active matrix substrate, which does not face a counter substrate and avoiding air between the heat radiating film and the polarizing plate. SOLUTION: On the surface of one of substrates 11 of the liquid crystal panel, pixel electrodes 13 connected to thin film transistors TFT 12 are formed into a matrix to form an active matrix circuit. A heat radiating film 14 is formed on the other surface of the substrate 11, and a polarizing plate 15 is adhered to the heat radiating film 14. Thereby, even when heat is generated in the polarizing plate 15 due to absorbed light even in a black display device, the heat is rapidly diffused by the heat radiating film 14, to prevent temp. increase of the polarizing plate 15. Thus, changes or deterioration in the characteristics of TFT 12 by the heat are prevented. By avoiding air between the substrate 11 and the polarizing plate 15, the quantity of light reflected by the polarizing plate 11 to return to the substrate 11 can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a projector type liquid crystal display device and a liquid crystal panel used for a projection type liquid crystal display device.

[0002]

2. Description of the Related Art Due to intensive research on a technique for manufacturing a thin film transistor, a liquid crystal display device has been used as a display device of various electronic devices. FIG.
The display principle of a transmission type active matrix type liquid crystal display device will be briefly described with reference to FIG.

[0003] A liquid crystal display device expresses a gray scale using polarized light of light passing through a liquid crystal. An electric field is formed between the pixel electrode 3 of the active matrix substrate and the counter electrode 5 of the counter substrate to control the arrangement of molecules of the liquid crystal layer 6. The illumination light from the light source is converted into linearly polarized light oscillating in one direction by the polarizing plate 9, passes through the quartz substrate 4 of the counter substrate, the counter electrode made of a transparent conductive film, and enters the liquid crystal layer 6. The vibration direction of the light incident on the liquid crystal layer 6 is changed in the vibration direction of the light along the arrangement of the liquid crystal molecules, passes through the pixel electrode 3 and the quartz substrate 2,
Only the component of light that enters the polarizing plate 8 and vibrates in one predetermined direction passes through the polarizing plate 8. The polarizing plate 8 and the polarizing plate 9 are arranged such that the vibration directions of light that can pass therethrough are orthogonal to each other.
By controlling the arrangement of the liquid crystal molecules, the amount of light passing through the polarizing plate 8 is changed to perform gradation display.

In an active matrix type liquid crystal display device, the pixel 3 is changed by changing the voltage of the pixel electrode 3.
The arrangement of the liquid crystal molecules is controlled by changing the magnitude of the electric field between the liquid crystal molecules and the counter electrode 5.
By controlling the voltage applied to the FT 2, the timing of applying the voltage to the pixel electrode 5 and the magnitude thereof are controlled.

A projector type liquid crystal display device enlarges and projects an image displayed on a liquid crystal panel having a size of several inches by an optical system to display a large screen of several tens of inches. Since a light source having an extremely large light quantity is required as compared with the above, the temperature of the liquid crystal panel becomes high due to the illumination light. Generally, a polarizing plate is made of a polymer film as a base material and is directly bonded to a direct-view liquid crystal panel.
As shown in FIG. 15, it cannot be directly bonded to the panel.

[0006]

In recent years, liquid crystal panels have been required to have a higher pixel count and a higher definition. In order to improve the contrast, it is desired to attach a polarizing plate also to a projector-type liquid crystal panel. However, assuming that the polarizing plate 8 is adhered to the active matrix substrate shown in FIG. 15, light is absorbed by the polarizing plate 8 when black display is performed. For this reason, the temperature of the polarizing plate 8 rises, and the active matrix substrate is heated by this heat, which greatly deviates from the optimal operation conditions of the TFT 2 and the liquid crystal 6, and may lower the image quality. Furthermore, since a polymer film is used, the polarizing plate 8 itself may be deteriorated.

Therefore, conventionally, as shown in FIG. 15, the polarizing plate is separated from the active matrix substrate, and air exists between the quartz substrate 1 and the polarizing plate 8. Due to the difference in the refractive index between the quartz substrate 1 and air, about 3% of the light directly incident on the quartz substrate 1 is reflected at the interface between the quartz substrate 1 and air. When a glass substrate is used as the substrate, about 4% of the light is reflected and the light utilization rate is reduced. Further, light reflected at the interface with air illuminates the semiconductor layer of the TFT 2 and causes light deterioration. In the case of the projector type, since the light intensity is very large, even a few percent of reflected light
There is a possibility that the characteristics of the FT may be largely changed.

In order to reduce reflected light returning to the active matrix substrate, the difference between the refractive indexes of the substrate 1 and the medium in contact with the substrate may be reduced. 8 is desired to be attached. However, in the case of the projector type, the polarizing plate cannot be directly attached to the substrate due to the problem of the heat generation of the polarizing plate described above.

The present invention solves the above-mentioned problem and relates to a structure for attaching a polarizing plate to a liquid crystal panel for a projector type display device.

[0010]

According to the present invention, there is provided a liquid crystal panel used in a projector type display apparatus, which comprises an active matrix substrate having a pixel electrode connected to a thin film transistor (a first substrate). ) And an active matrix type liquid crystal panel in which liquid crystal is sandwiched between a counter substrate (a second substrate) having a counter electrode, a heat dissipation film is provided on a surface of the active matrix substrate which is not opposed to the opposed substrate. It is characterized in that no air is interposed between the polarizing plate and the polarizing plate.

That is, in order to attach a polarizing plate to a glass or quartz substrate of an active matrix substrate, a heat radiation film is provided in a state where air is not interposed between the substrate and the polarizing plate. As the heat dissipation film, an insulating film having a high thermal conductivity of at least 10 W / m · K, more preferably at least 50 Wm ⁻¹ K ⁻¹ may be used.
By forming the heat dissipation film, heat generated in the thin film transistor and the polarizing plate can be radiated, so that deterioration of the thin film transistor and the polarizing plate can be prevented. As a result, the polarizing plate can be provided on the substrate of the liquid crystal panel without air, so that light reflected by the polarizing plate can be reduced.

[0012]

Embodiments of the present invention will be described with reference to FIGS.

Embodiment 1 FIG. 1 is a cross-sectional view of a transmission type liquid crystal panel of the present embodiment. The liquid crystal panel is the substrate 1
A pixel electrode 13 connected to a TFT (thin film transistor) 12 is arranged on a matrix on one surface of the semiconductor device 1 to form an active matrix circuit. On the other surface of the substrate 11, a heat dissipation film 14 is formed.
A polarizing plate 15 is attached.

An opposing electrode 22 is formed on a substrate 21 of the opposing substrate. The substrate 11 and the substrate 21 are bonded with a gap therebetween with the pixel electrode 13 and the counter electrode 22 inside. The gap is filled with the liquid crystal 30. In the liquid crystal panel, a capacitor having a pixel electrode 13 and a counter electrode 22 as an electrode pair and a liquid crystal 30 as a dielectric is formed for each pixel. The arrangement of the liquid crystal molecules of the liquid crystal 30 is changed by controlling the potential of the capacitor. Substrates 11, 12
Is made of quartz or glass, and the substrate size is about 0.5 to 3 inches.

Illumination light from a light source is linearly polarized by a polarizing plate 23 provided from a liquid crystal panel, passes through the air, the substrate 21, and the counter electrode 22, is polarized by the liquid crystal 30, and is polarized by the pixel electrode 13, the substrate 11, It passes through the heat radiation film 14. Only the light component that vibrates in one predetermined direction is
Pass through.

In the present embodiment, even in a black display state, that is, in a state where light is not allowed to pass through the polarizing plate 15, the heat generated by the polarizing plate 15 due to the absorbed light is quickly diffused by the heat dissipation film 14. The temperature rise of the polarizing plate 15 can be prevented. As a result, the characteristics of the TFT 12 are not changed or deteriorated by heat. Substrate 1
By not sandwiching air between 1 and the polarizing plate, the amount of light reflected by the polarizing plate 11 and returning to the substrate 11 can be reduced.

As the heat radiation film 14, a flow film having at least one insulating layer having a light transmitting property and a heat conductivity is used. B,
At least one element selected from C and N, and Al and S
A compound containing at least one element selected from i and P is known as a material having a property of transmitting visible light and having good heat conductivity.

For example, aluminum nitride (aluminum nitride (AlN)), silicon carbide (silicon carbide (SiC)), silicon nitride (silicon nitride (S
iN)), boron nitride (boron nitride (BN)), and boron phosphide (boron phosphide (BP)).

An aluminum oxide (aluminum oxide (Al ₂ O ₃ )) is excellent in light transmittance and has a heat conductivity of 20%.
Wm ^-1 K ^-1 can be used for the material of the heat radiation film 14.

The above compound is not limited to the stoichiometric ratio, and a material containing another element in the composition can be used to control properties such as thermal conductivity. For example, by adding nitrogen to aluminum oxide, AlN _x O _1-x (0.02
.Ltoreq.x.ltoreq.0.5).

Some elements of silicon nitride (Si ₃ N ₄ ) are represented by O (oxygen) and M (M is Al, Y, La, Gd, D
(at least one element selected from y and Nd), and a compound containing Si, N, O, and M can be used.

The above-mentioned compound layer can be formed by a sputtering method. A film can be formed by using a target having a desired composition and using an inert gas such as argon or nitrogen as a sputtering gas.

Also, a thin diamond layer or a DLC (Diamond Like Carbohydrate) having a thermal conductivity of 1000 Wm ^-1 K ^-1.
n) A film having a layer is preferable as the heat dissipation film. Thin film diamond can be formed by a CVD method.

The heat radiation film 14 is composed of the TFT 12 and the pixel electrode 13.
It may be formed after manufacturing. If it does not hinder the alignment of the fabrication of the TFT 12,
May be formed before and during the production. Heat dissipation film 14
In consideration of the deterioration of the pixel 13, it is more preferable after the pixel 13 is formed, but it is formed at least after a heat treatment step at 600 ° C. such as a crystallization step or a thermal oxidation step of a semiconductor film used for the TFT 11.

The polarizing plate 15 may be a generally used polarizing film having a polymer film as a base, and is attached to the heat radiation film 14 using an adhesive formed on the polarizing film. Have been. In addition, polarizing plate 1
Reference numeral 5 denotes a boundary surface with air (an emission surface of illumination light from a light source).
It is preferable to provide an antireflection layer for preventing reflection at the surface, because the light utilization factor is improved.

[Embodiment 2] This embodiment relates to Embodiment 1.
This is a modified example. FIG. 2 is a cross-sectional view of the liquid crystal panel of the present embodiment, and the same reference numerals as in FIG. 1 indicate the same components.

According to the present invention, since the heat radiation film 14 is formed on the substrate 11, the temperature rise of the liquid crystal panel is reduced. Therefore, as shown in FIG. Become.

[Embodiment 3] This embodiment relates to Embodiment 1.
This is a modified example. FIG. 3 is a cross-sectional view of the liquid crystal panel of the present embodiment. The same reference numerals as in FIG. 1 denote the same components.

In this embodiment, an antireflection film 16 is provided between the heat radiation film 14 and the polarizing plate 15. Depending on the refractive index and the film thickness of the heat radiation film 14, light may be reflected at the boundary between the heat radiation film 14 and the polarizing plate 15 to lower the contrast. Here, a film 16 for preventing reflection is inserted. To at least prevent the reflection of vertically incident light,
The refractive index of the polarizing plate 15, the antireflection film 16, and the heat radiation film 14 is n
_Assuming that ₀ , n ₁ , and n ₂ , ideally satisfy n ₁ = (n ₀ n ₂ ) ^1/2 .

Embodiment An embodiment of the present invention will be described with reference to FIGS.

Embodiment 1 FIG. 4 shows an embodiment of the present invention.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing a pixel circuit and a control circuit for controlling the pixel circuit over the same substrate will be described. However, for the sake of simplicity, the control circuit shows a CMOS circuit as a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 4A, it is desirable to use a quartz substrate or a silicon substrate as the substrate 101. In this embodiment, a quartz substrate was used. Alternatively, a substrate obtained by forming an insulating film on the surface of a metal substrate or a stainless steel substrate may be used as the substrate. In the case of this embodiment, since heat resistance that can withstand a temperature of 800 ° C. or more is required, any substrate may be used as long as it meets the requirement.

The surface of the substrate 101 on which the TFT is to be formed has a thickness of 20 to 100 nm (preferably 40 to 80 nm).
Semiconductor film 102 having an amorphous structure having a thickness of
Formed by the plasma CVD method or the sputtering method in the D direction.
In this embodiment, an amorphous silicon film having a thickness of 60 nm is formed. However, since a thermal oxidation step is performed later, this film thickness does not necessarily become the final film thickness of the active layer of the TFT.)

The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. . Further, it is also effective to continuously form a base film and an amorphous silicon film on a substrate without exposing them to the atmosphere. By doing so, it becomes possible to prevent contamination of the substrate surface from affecting the amorphous silicon film, and it is possible to reduce the variation in characteristics of the TFT to be manufactured.

Next, a mask film 103 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 102, and openings 104a and 104b are formed by patterning. The opening serves as an addition region for adding a catalyst element that promotes crystallization in the next crystallization step.
(FIG. 4 (A))

Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiO _x N _y . The silicon nitride oxide film is SiH ₄ ,
N ₂ O and NH ₃ can be produced as a source gas, and the nitrogen concentration is 25 atomic% or more and 50 atomic% or more.
It is better to be less than.

At the same time as the patterning of the mask film 103 is performed, a marker pattern which is a reference for a subsequent patterning step is formed. When the mask film 103 is etched, the amorphous silicon film 102 is also slightly etched. However, this step can be used as a marker pattern at the time of mask alignment later.

Next, a semiconductor film having a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. 10-247735 (corresponding to US Application No. 09 / 034,041). The technology described in the publication discloses a catalyst element (nickel, cobalt, germanium, tin, lead, palladium, etc.) that promotes crystallization during crystallization of a semiconductor film having an amorphous structure.
Crystallization means using one or more elements selected from iron and copper).

Specifically, heat treatment is performed in a state where a catalytic element is held on the surface of the semiconductor film including the amorphous structure, and the semiconductor film including the amorphous structure is changed to a semiconductor film including the crystalline structure. It is to let. As the crystallization means, the technique described in Example 1 of JP-A-7-130652 may be used. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, and a semiconductor film including a crystal structure formed in the publication has a crystal grain boundary.

In this publication, a spin coat method is used when a layer containing a catalyst element is formed on a mask film.
Means for forming a thin film containing a catalytic element by a gas phase method such as a sputtering method or an evaporation method may be employed.

The amorphous silicon film is preferably subjected to a heat treatment at 400 to 550 ° C. for about 1 hour, depending on the hydrogen content, and is preferably crystallized after sufficient desorption of hydrogen. . In that case, the hydrogen content is 5 atomic%
It is preferable to set the following.

The crystallization step is first performed at 400 to 500 ° C. for 1 hour.
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600
C.) for 6 to 16 hours (preferably 8 to 14 hours).

In this embodiment, nickel is used as a catalyst element, and a heat treatment is performed at 570 ° C. for 14 hours. as a result,
From the openings 104a and 104b as starting points, crystallization proceeds in a direction substantially parallel to the substrate (direction indicated by an arrow), and a semiconductor film having a crystal structure in which macroscopic crystal growth directions are aligned (in this embodiment, a crystalline film). Silicon films) 105a to 105d are formed. (FIG. 4 (B))

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
In this embodiment, a step of adding an element belonging to Group XV (phosphorus in this embodiment) using the previously formed mask film 103 as a mask is performed, and the crystalline silicon film exposed in the openings 104a and 104b is added to the 1 × 10 4 ¹⁹ to 1 × 10 ²⁰ at
Phosphorus-added regions (hereinafter, referred to as gettering regions) 106a and 106b containing phosphorus at a concentration of oms / cm ³ are formed.
(FIG. 4 (C))

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline silicon film moves in the direction of the arrow, and is captured in the gettering regions 106a and 106b by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon films 107a to 107d after gettering is 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁷ atms / cm ³ or less.
It can be reduced to × 10 ¹⁶ atms / cm ³ .

Next, the mask film 103 is removed, and a protective film 108 is formed on the crystalline silicon films 107a to 107d for the later addition of impurities. The protective film 108 is 100 to 2
It is preferable to use a silicon nitride oxide film or a silicon oxide film having a thickness of 00 nm (preferably 130 to 170 nm). This protective film 108 is for preventing the crystalline silicon film from being directly exposed to plasma when adding impurities, and for enabling fine concentration control.

Then, a resist mask 109 is formed thereon, and an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) is added via the protective film 108. As the p-type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used.
This step (called a channel doping step) is a step for controlling the threshold voltage of the TFT. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.

By this step, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ at
oms / cm ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / c
Impurity regions 110a and 110b containing a p-type impurity element (boron in this embodiment) at a concentration of m ³ ) are formed. Note that in this specification, an impurity region containing a p-type impurity element within the above concentration range (a region not containing phosphorus) is defined as a p-type impurity region (b). (FIG. 4 (D))

Next, the resist mask 109 is removed, and the crystalline silicon film is patterned to form island-like semiconductor layers (hereinafter, referred to as active layers) 111 to 114. In addition,
The active layers 111 to 114 are formed of a crystalline silicon film having extremely good crystallinity by selectively adding nickel and crystallizing. Specifically, it has a crystal structure in which rod-shaped or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus.
The concentration of the catalyst element remaining in 14 is 1 × 10 ¹⁷ atms / c
m ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ . (FIG. 4
(E))

The active layer 111 of the p-channel TFT is
Is a region not containing an impurity element intentionally added, and the active layers 112 to 114 of the n-channel TFT are p-type impurity regions (b). In this specification, the active layers 111 to 114 in this state are all defined as being intrinsic or substantially intrinsic. That is, a region to which an impurity element is intentionally added to such an extent that the operation of the TFT is not hindered may be considered as a substantially intrinsic region.

Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a silicon nitride oxide film having a thickness of 30 nm is formed. As the insulating film containing silicon, another insulating film containing silicon may be used as a single layer or a stacked layer.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step at a temperature of (00 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added in an oxygen atmosphere. Note that boron added in the step of FIG. 4D is activated during this thermal oxidation step. (FIG. 5
(A))

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer.
Further, in this embodiment, an atmosphere in which a halogen element is included in an oxygen atmosphere is used, but the atmosphere may be performed in a 100% oxygen atmosphere.

During this thermal oxidation step, an oxidation reaction also proceeds at the interface between the insulating film containing silicon and the active layers 111 to 114 thereunder. In the present invention, in consideration of this, the thickness of the gate insulating film 115 finally formed is 50 to 200 nm.
(Preferably 100 to 150 nm). In the thermal oxidation step of this embodiment, 25 nm of the active layer having a thickness of 60 nm is oxidized, and the thickness of the active layers 111 to 114 is 4 mm.
5 nm. Further, since a 50-nm-thick thermal oxide film is added to the 30-nm-thick silicon-containing insulating film, the final gate insulating film 115 has a thickness of 110 nm.

Next, resist masks 116 to 11 are newly added.
9 is formed. Then, an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added to form impurity regions 120 to 122 exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group XV, typically, phosphorus or arsenic can be used. (FIG. 5
(B))

The impurity regions 120 to 122 will be
N-channel type TF of MOS circuit and sampling circuit
T is an impurity region for functioning as an LDD region. The impurity region formed here has n
The type impurity element is contained at a concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically, 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).

Note that, here, phosphorus is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ by an ion doping method in which phosphine (PH ₃ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the crystalline silicon film via the gate film 115.

Next, at 600 to 1000 ° C. (preferably 7 ° C.)
Heat treatment is performed in an inert atmosphere (at 00 to 800 ° C.) to activate the phosphorus added in the step of FIG. In this embodiment, the heat treatment at 800 ° C. for 1 hour is performed in a nitrogen atmosphere.
(FIG. 5 (C))

At this time, it is possible to repair the active layer and the interface between the active layer and the gate insulating film that have been damaged by the addition of phosphorus at the same time. In this activation step, furnace annealing using an electric heating furnace is preferable, but optical annealing such as lamp annealing or laser annealing may be used together.

By this step, n-type impurity region (b) 12
The boundary portion between 0 and 122, that is, the junction with the intrinsic or substantially intrinsic region (including the p-type impurity region (b)) existing around the n-type impurity region (b) becomes clear. . This means that when the TFT is completed later, LDD
This means that the region and the channel forming region can form a very good junction.

Next, a conductive film to be a gate wiring is formed. Note that the gate wiring may be formed using a single-layer conductive film, but is preferably a stacked film such as two layers or three layers as necessary. In this embodiment, a stacked film including the first conductive film 123 and the second conductive film 124 is formed. (FIG. 5 (D))

Here, the first conductive film 123 and the second conductive film 12
4 include tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (C
r), an element selected from silicon (Si), or a conductive film containing the above element as a main component (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the above elements ( Typically, Mo-W alloy,
Mo-Ta alloy) can be used.

The first conductive film 123 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm), and the second conductive film 124 may have a thickness of 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, as the first conductive film 123, 5
A 0 nm thick tungsten nitride (WN) film is formed on the second conductive film 1.
As 24, a 350 nm thick tungsten film is used. Although not shown, it is effective to form a silicon film under the first conductive film 123 with a thickness of about 2 to 20 nm. This can improve the adhesion of the conductive film formed thereon and prevent oxidation.

It is also effective to use a tantalum nitride film as the first conductive film 123 and a tantalum film as the second conductive film.

Next, the first conductive film 123 and the second conductive film 12
4 is etched at a time to form a gate wiring 1 having a thickness of 400 nm.
25 to 128 are formed. At this time, gate wirings 126 and 127 formed in the control circuit are n-type impurity regions (b) 1
The gate insulating film 115 is formed so as to overlap with a part of the gate electrodes 20 to 122. This overlapping portion will later become a Lov region. Although the gate wirings 128a and 128b appear to be two in cross section, they are actually formed from one continuous pattern. (FIG. 5E)

Next, a resist mask 129 is formed, and p
The impurity regions 130 and 131 containing boron at a high concentration are formed by adding a type impurity element (boron in this embodiment).
In this embodiment, 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically, 5 × 10 ^{21 to} 3 × 10 ²¹ atoms / cm ³ ) by an ion doping method (of course, an ion implantation method) using diborane (B ₂ H ₆ ).
Boron is added at a concentration of (× 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (FIG. 6 (A))

Next, the resist mask 129 is removed, and resist masks 132 to 134 are formed so as to cover the gate wiring and the region to be the p-channel TFT. And n
The impurity regions 135 to 141 containing phosphorus at a high concentration are formed by adding a type impurity element (phosphorus in this embodiment). Also in this case, the ion doping method using phosphine (PH ₃ ) (of course, the ion implantation method may be used), and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ at.
oms / cm ³ (typically ^{2 × 10 20 ~5 × 10 2} 1 atoms / c
m ³ ). (FIG. 6 (B))

In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 135 to 141 are formed contains phosphorus or boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. You do not need to consider the effect of phosphorus or boron. Therefore, in this specification, the impurity regions 135 to 141 may be referred to as n-type impurity regions (a).

Next, after removing the resist masks 132 to 134, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligned manner using the gate wirings 125 to 128 as a mask. The impurity regions 143 to 146 thus formed
Has a concentration of ２〜 to 1/10 (typically ３ to ４) of the n-type impurity region (b) (provided that it is 5% lower than the boron concentration added in the channel doping step described above). 10 to 10 times higher concentration, typically 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm
³ , typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ ). Note that, in this specification, an impurity region containing an n-type impurity element (excluding the p-type impurity region (a)) in the above concentration range is defined as an n-type impurity region (c). (FIG. 6 (C))

In this step, the part hidden by the gate wiring
Except for all impurity regions, 1 × 10¹⁶~ 5 × 10¹⁸at
oms / cm^ThreePhosphorus is added at a concentration of
This does not affect the function of each impurity region.
The n-type impurity regions (b) 143 to 146 already have
1 × 10 in channel doping process¹⁵~ 1 × 10¹⁸atoms / cm ^Three
Is added, but in this step, p-type
5 to 10 times the concentration of boron contained in the impurity region (b)
In this case, boron is also added as n-type impurity.
It may be considered that the function of the object area (b) is not affected.

However, strictly speaking, the n-type impurity region (b) 14
7 and 148, the phosphorus concentration of the portion overlapping the gate wiring remains at 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , while the portion not overlapping the gate wiring is 1 × 10 ¹⁶
Phosphorus at a concentration of ~ 5 × 10 ¹⁸ atoms / cm ³ is added,
It will contain phosphorus at a slightly higher concentration.

Next, a first interlayer insulating film 149 is formed.
The first interlayer insulating film 149 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. Further, the film thickness may be 100 to 400 nm.
In the present embodiment, SiH ₄ , N ₂ O, N
H ₃ is used as a source gas, and a silicon nitride oxide film having a thickness of 200 nm (the nitrogen concentration is 25 to 50 atomic%) is used.

Thereafter, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by furnace annealing, laser annealing, lamp annealing, or a combination thereof. When performing the furnace annealing method,
The heat treatment may be performed at 500 to 800C, preferably 550 to 600C in an inert atmosphere. In this embodiment, 600
A heat treatment is performed at 4 ° C. for 4 hours to activate the impurity element.
(FIG. 6 (D))

In this embodiment, the silicon nitride film 142
And the silicon nitride oxide film 149 are stacked to cover the gate wiring, and the activation step is performed in that state. In this embodiment, tungsten is used as a wiring material.
It is known that a tungsten film is very susceptible to oxidation. That is, even if it is covered with the protective film and oxidized, if the pinhole exists in the protective film, it is immediately oxidized. However,
In this embodiment, since the silicon nitride film and the silicon nitride oxide film are stacked, the activation step can be performed at a high temperature without concern for the problem of pinholes.

Next, after the activation step, heat treatment is performed in an atmosphere containing 3 to 100% hydrogen at 300 to 450 ° C. for 1 to 4 hours to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

After the activation step, the first interlayer insulating film 1
A second interlayer insulating film 15 having a thickness of 500 nm to 1.5 μm
0 is formed. In this embodiment, an 800 nm thick silicon oxide film is formed as the second interlayer insulating film 150 by a plasma CVD method. Thus, the first interlayer insulating film (silicon nitride oxide film) 149 and the second interlayer insulating film (silicon oxide film) 15
Then, an interlayer insulating film having a thickness of 1 μm, which is a laminated film of 0, is formed.

Note that an organic resin film such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) may be used as the second interlayer insulating film 150 if heat resistance is allowed in a later step. .

Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and the source wirings 151 to 154 and the drain wiring 155 are formed.
To 157 are formed. In order to form a CMOS circuit, the drain wiring 155 is shared between the p-channel TFT and the n-channel TFT. Although not shown, in the present embodiment, this wiring is
nm, aluminum film containing Ti 500 nm, Ti film 100
nm is a laminated film having a three-layer structure continuously formed by a sputtering method. (FIG. 7 (A))

Next, as a passivation film 158,
50 to 500 nm (typically 200 to 300 nm) of a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film.
m). At this time, in this embodiment, a plasma treatment is performed using a gas containing hydrogen such as H ₂ and NH ₃ before forming the film, and a heat treatment is performed after the film is formed. Hydrogen excited by this pretreatment is supplied into the first and second interlayer insulating films. By performing the heat treatment in this state, the film quality of the passivation film 158 is improved, and the hydrogen added to the first and second interlayer insulating films diffuses to the lower side, so that the active layer is effectively hydrogenated. be able to.

After the passivation film 158 is formed, a hydrogenation step may be further performed. For example, 3
300-450 ° C. in an atmosphere containing 〜100% hydrogen
The heat treatment is preferably performed for 1 to 12 hours, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening (not shown) may be formed in the passivation film 158 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed after the hydrogenation step.

Thereafter, a third interlayer insulating film 159 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film or an organic SiO ₂ compound other than those described above can also be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate.

Next, in a region to be a pixel circuit, the third
A shielding film 160 is formed over the interlayer insulating film 159. In addition,
In this specification, the term shielding film is used to mean that light and electromagnetic waves are shielded. The shielding film 160 is made of aluminum (A
1) A film made of an element selected from titanium (Ti) and tantalum (Ta) or a film containing any one of the elements as a main component and having a thickness of 100 to 300 nm. In this example, 1 wt%
An aluminum film containing titanium is formed to a thickness of 125 nm.

If an insulating film such as a silicon oxide film is formed to a thickness of 5 to 50 nm on the third interlayer insulating film 159, the adhesion of the shielding film formed thereon can be improved. In addition, when plasma treatment using CF ₄ gas is performed on the surface of the third interlayer insulating film 159 formed of an organic resin, adhesion of a shielding film formed on the film can be improved by surface modification.

It is also possible to form not only a shielding film but also other connection wirings by using the aluminum film containing titanium. For example, connection wiring for connecting the circuits in the control circuit can be formed. However, in that case, before forming the material for forming the shielding film or the connection wiring, the third
It is necessary to form a contact hole in the interlayer insulating film.

Next, an oxide 161 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the shielding film 160 by an anodic oxidation method or a plasma oxidation method (in this embodiment, an anodic oxidation method). In this embodiment, an aluminum oxide film (alumina film) is formed as the anodic oxide 161 because a film containing aluminum as a main component is used as the shielding film 160.

At the time of this anodizing treatment, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is first prepared. This is a solution obtained by mixing a 15% aqueous solution of ammonium tartrate and ethylene glycol at a ratio of 2: 8, and ammonia water is added thereto to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, the substrate on which the shielding film 160 is formed is immersed in the solution, and a constant (several mA to several tens mA) DC current is passed using the shielding film 160 as an anode.

The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide, but the voltage is increased at a constant current of 100 V / min at a step-up rate to reach the ultimate voltage of 45 V. By the way, the anodizing treatment is terminated.
In this manner, an anodic oxide 161 having a thickness of about 50 nm can be formed on the surface of the shielding film 160. As a result, the thickness of the shielding film 160 becomes 90 nm. It is to be noted that the numerical values relating to the anodic oxidation method shown here are merely examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.

Although the insulating film is provided only on the surface of the shielding film by using the anodic oxidation method here, the insulating film may be formed by a gas phase method such as a plasma CVD method, a thermal CVD method or a sputtering method. good. In this case, the film thickness is 20 to 1
00 nm (preferably 30 to 50 nm). Further, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film,
An LC (Diamond Like Carbon) film, a tantalum oxide film, or an organic resin film may be used. Further, a stacked film combining these may be used.

Next, a contact hole reaching the drain wiring 157 is formed in the third interlayer insulating film 159 and the passivation film 158, and a pixel electrode 162 is formed. In addition,
The pixel electrode 163 is a pixel electrode of another adjacent pixel.
The pixel electrodes 162 and 163 may be formed using a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is formed. Here, in order to obtain a transmissive liquid crystal display device, indium tin oxide (IT
O) A film is formed to a thickness of 110 nm by a sputtering method.

At this time, the pixel electrode 162 and the shielding film 1
60 overlap with each other via the anodic oxide 161 to form a storage capacity (capacity striation) 164. Note that in this case, it is desirable that the shielding film 160 be set to a floating state (an electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).

Thus, an active matrix substrate having a control circuit and a pixel circuit on the same substrate was completed. In FIG. 7B, a p-channel TFT 301 and n-channel TFTs 302 and 303 are formed in the control circuit, and a pixel T composed of the n-channel TFT is formed in the pixel circuit.
An FT 304 is formed.

In the p-channel TFT 301 of the control circuit, a channel forming region 201, a source region 202, and a drain region 203 are each formed of a p-type impurity region (a). However, strictly speaking, the source 202 region and the drain region 203 contain phosphorus at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ .

In the n-channel type TFT 302, a channel formation region 204, a source region 205, a drain region 206, and a region between a channel formation region and a drain region which overlaps with a gate wiring via a gate insulating film ( In this specification, such a region is referred to as an Lov region, where ov is assigned to overlap.) 207 is formed. At this time, the Lov region 207 is 2 × 10 ^{16 to} 5 × 10 ¹⁹
It is formed so as to contain phosphorus at a concentration of atoms / cm ³ and to completely overlap with the gate wiring.

In the n-channel type TFT 303, the channel forming region 208, the source region 209, the drain region 210, and the L
DD regions 211 and 212 are formed. That is, an LDD region is formed between the source region and the channel formation region and between the drain region and the channel formation region.

In this structure, the LDD regions 211, 2
12 are arranged so as to overlap with the gate wiring, a region (Lov region) that overlaps with the gate wiring via the gate insulating film and a region that does not overlap with the gate wiring (such a region is referred to as Loff region, where off is
Affixed in the meaning of offset. ) Has been realized.

The pixel TFT 304 includes channel forming regions 213 and 214, a source region 215, a drain region 216, Loff regions 217 to 220, and an Loff region 21.
8, 219 are formed in contact with n-type impurity regions (a) 221. At this time, the source region 215 and the drain region 21
6 are each formed of an n-type impurity region (a),
Regions 217 to 220 are formed by n-type impurity regions (c).

In this embodiment, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the pixel circuit and the control circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, n-channel type TF
T makes the arrangement of the LDD region different according to the circuit specifications,
By properly using the ov region or the Loff region, a TFT structure emphasizing high-speed operation or measures against hot carriers and a TFT structure emphasizing low off-current operation can be realized on the same substrate.

For example, in the case of an active matrix type liquid crystal display device, the n-channel type TFT 302 is suitable for a control circuit such as a shift register circuit, a frequency dividing circuit, a signal dividing circuit, a level shifter circuit, and a buffer circuit which emphasize high-speed operation. That is, the Lov region is formed only between the channel formation region and the drain region, so that the resistance component is reduced as much as possible and the hot carrier measures are emphasized. This is because, in the case of the above-described circuit group, the functions of the source region and the drain region do not change and the direction in which carriers (electrons) move is constant.

However, the Lov region can be formed with the channel forming region interposed therebetween, if necessary. That is, it can be formed between the source region and the channel formation region and between the drain region and the channel formation region.

Further, the n-channel TFT 303 is suitable for a sampling circuit (sample-hold circuit) in which both measures against hot carriers and low off-current operation are emphasized. That is, the hot carrier is prevented by forming the Lov region, and a low off-current operation is realized by forming the Loff region. In the sampling circuit, the functions of the source region and the drain region are reversed, and the carrier moving direction is 18
Since the angle is changed by 0 °, the structure must be line-symmetric with respect to the gate wiring. In some cases, L
There may be only the ov region.

Further, the n-channel type TFT 304 is suitable for a pixel circuit and a sampling circuit (sample-hold circuit) which place importance on low off-current operation. In other words, Loff regions that may cause an increase in the off-state current value are not provided, and Loff
By arranging only the region, a low off-current operation is realized. Further, the LD having a lower concentration than the LDD region of the control circuit.
By using the D region as the Loff region, a measure is taken to thoroughly reduce the off-current value even if the on-current value slightly decreases. Further, it has been confirmed that the n-type impurity region (a) 221 is very effective in reducing the off-current value.

Further, if the length (width) of the Lov region 207 of the n-channel TFT 302 is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm, for a channel length of 3 to 7 μm. good. The length (width) of the Lov regions 211a and 212a of the n-channel TFT 303 is 0.3 to 3.0 μm.
m, typically 0.5 to 1.5 μm, Loff region 211
The length (width) of b, 212b may be 1.0 to 3.5 μm, typically 1.5 to 2.0 μm. The pixel TF
The length (width) of the Loff regions 217 to 220 provided in the T304 is 0.5 to 3.5 μm, typically 2.0 to 2.0 μm.
The thickness may be set to 5 μm.

Further, the p-channel TFT 301 is formed in a self-aligned (self-aligned) manner,
One of the features of the present invention is that the FTs 302 to 304 are formed in a non-self-aligned manner (non-self-aligned).

Also, in this embodiment, an alumina film having a relative dielectric constant as high as 7 to 9 is used as the dielectric of the storage capacitor.
The area occupied by the storage capacitor required to form the required capacitance can be reduced. Further, by using the shielding film formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the image display section of the active matrix type liquid crystal display device can be improved.

The present invention is not limited to the structure of the storage capacitor shown in this embodiment. For example, the present applicant has filed Japanese Patent Application No. 9-316567 and Japanese Patent Application No. 9-2732.
A storage capacitor having a structure described in Japanese Patent Application No. 44 or Japanese Patent Application No. 10-254097 can also be used.

Here, a heat radiating film 231 is formed on the back surface of the active matrix substrate (the surface on which no TFT is formed). Here, alumina (aluminum oxide) is formed by a sputtering method.

A process of manufacturing a liquid crystal panel by modularizing an active matrix substrate and a counter substrate will be described. As shown in FIG. 8, an alignment film 241 is formed on the substrate in the state shown in FIG. In this embodiment, a polyimide film is used as an alignment film. On the opposite substrate 242, a transparent conductive film 243 and an alignment film 244 are formed. Note that a color filter and a shielding film may be formed on the counter substrate as needed.

Next, after forming the alignment film, a rubbing treatment is performed to adjust the liquid crystal molecules so as to be aligned with a certain pretilt angle. Then, the pixel circuit, the active matrix substrate on which the control circuit is formed, and the counter substrate are bonded together by a known cell assembling process via a sealing material, a spacer (both not shown), or the like. afterwards,
Liquid crystal 245 is injected between both substrates, and a sealing agent (not shown) is used.
Complete sealing. A known liquid crystal material may be used for the liquid crystal. Then, the polarizing plate 232 is attached to the surface of the heat dissipation film 231 using an adhesive provided on the polarizing plate 232. Thus, the active matrix type liquid crystal display panel shown in FIG. 8 is completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. Note that in FIG. 9, common reference numerals are used to correspond to the cross-sectional structure diagrams of FIGS. 4 to 7. The active matrix substrate includes a pixel circuit 311 formed on the quartz substrate 101.
, A scanning (gate) signal control circuit 312, and an image (source) signal control circuit 313. The pixel TFT 304 of the pixel circuit is an n-channel TFT, and a control circuit provided in the periphery is configured based on a CMOS circuit. Scanning signal control circuit 312 and image signal control circuit 3
Reference numeral 13 denotes a gate line 128 and a source line 154, respectively, which are connected to the pixel circuit 311. In addition, FPC804
There are provided connection wirings 316 and 317 from the external input / output terminal 315 to which is connected to the input / output terminal of the control circuit.

FIG. 10 shows an example of a circuit configuration of the active matrix type liquid crystal display device shown in FIG. The active matrix type liquid crystal display device of this embodiment includes an image signal control circuit 321, a scan signal control circuit (A) 327, a scan signal control circuit (B) 331, a precharge circuit 332, and a pixel circuit 326. Note that in this specification, the control circuit includes an image signal processing circuit 321 and a scanning signal control circuit 327.

The image signal control circuit 321 includes a shift register circuit 322, a level shifter circuit 323, a buffer circuit 324, and a sampling circuit 325. Also,
The scanning signal control circuit (A) 327 includes a shift register circuit 328, a level shifter circuit 329, and a buffer circuit 330.
It has. The scanning signal control circuit (B) 331 has the same configuration.

Here, shift register circuits 322, 328
Is a driving voltage of 3.5 to 16 V (typically 5 V or 10 V).
V) and n used in a CMOS circuit forming the circuit.
The structure shown by 302 in FIG. 6B is suitable for the channel type TFT.

The level shifter circuits 323, 329,
The driving voltage of the buffer circuits 324 and 330 is 14 to 16
V, as in the case of the shift register circuit.
A CMOS circuit including the n-channel TFT 302 shown in FIG. The gate wiring has a double gate structure,
The use of a multi-gate structure such as a triple gate structure is effective in improving the reliability of each circuit.

Although the driving voltage of the sampling circuit 325 is 14 to 16 V, the source and drain regions are inverted and the off-current value needs to be reduced. Therefore, the n-channel TFT 303 shown in FIG. Are suitable. In FIG. 6B, the n-channel type T
Although only FT is shown, when an actual sampling circuit is formed, an n-channel TFT and a p-channel TF are used.
Forming in combination with T is preferable because a large current easily flows.

The driving voltage of the pixel circuit 326 is 14 to
Since the off-state current is 16 V and a lower off-state current value than the sampling circuit 325 is required, it is preferable that the Lov region is not provided, and the n-channel TFT 304 in FIG. 6B be used as a pixel TFT. .

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in FIGS. In this embodiment, only the configurations of the pixel circuit and the control circuit are shown. However, according to the manufacturing process of the first embodiment, the signal dividing circuit, the frequency dividing circuit, the D / D
An A converter circuit, an operational amplifier circuit, a gamma correction circuit, and a signal processing circuit (also referred to as a logic circuit) such as a microprocessor circuit can be formed over the same substrate.

As described above, the present invention provides a semiconductor device including at least a pixel circuit and a control circuit for controlling the pixel circuit on the same substrate, for example, a signal processing circuit on the same substrate.
A semiconductor device including a control circuit and a pixel circuit can be realized.

When the steps up to FIG. 5B of this embodiment are performed, a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice is formed. For details on such a crystalline silicon film, refer to Japanese Patent Application No. 10-044 filed by the present applicant.
No. 659, Japanese Patent Application No. 10-152316, Japanese Patent Application No. 10-102
No. 152308 or Japanese Patent Application No. 10-152305 may be referred to. Hereinafter, the features of the crystal structure experimentally examined by the present applicant will be briefly described. This feature coincides with the feature of the semiconductor layer forming the active layer of the TFT completed by this embodiment.

The crystalline silicon film has a crystal structure in which a plurality of needle-shaped or rod-shaped crystals (hereinafter, abbreviated as rod-shaped crystals) are gathered and lined up microscopically. This is T
It can be easily confirmed by observation by EM (transmission electron microscopy).

Further, electron diffraction and X-ray (X-ray)
When diffraction is used, it can be confirmed that the surface of the crystalline silicon film (portion where a channel is formed) has a {110} plane as a main orientation plane, although the crystal axis has some deviation. At this time, if analysis is performed by electron beam diffraction,
It can be confirmed that diffraction spots corresponding to the 0 ° plane clearly appear. It can also be confirmed that each spot has a distribution on a concentric circle.

The crystal grain boundaries formed by the contact of the individual rod-shaped crystals are formed by HR-TEM (high-resolution transmission electron microscopy).
By observing the results, it can be confirmed that the crystal lattice has continuity at the crystal grain boundaries. This can be easily confirmed from the fact that the observed lattice fringes are continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above-mentioned paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

Particularly, when the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

When the crystalline silicon film of the present example was actually observed in detail using a TEM, it was found that most of the crystal grain boundaries (90%
It can be seen that (typically 95% or more) is the corresponding grain boundary of {3, typically {211} twin grain boundary.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3. In the crystalline silicon film of this embodiment, the lattice fringes of adjacent crystal grains at the crystal grain boundary are continuous at exactly an angle of about 70.5 °, which means that this crystal grain boundary is a corresponding grain boundary of Σ3. I can say.

When θ = 38.9 °, the corresponding grain boundary becomes Σ9, but there is another such corresponding grain boundary. In any case, it is still inert.

Such corresponding grain boundaries are formed only between crystal grains having the same plane orientation. That is, the crystalline silicon film of this embodiment can form such a corresponding grain boundary over a wide range only because the plane orientation is substantially {110}.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, a semiconductor thin film having such a crystal structure can be regarded as having substantially no crystal grain boundaries.

Further, it was confirmed by TEM observation that defects existing in the crystal grains were almost completely eliminated by the heat treatment step (corresponding to the thermal oxidation step in Example 1) at a high temperature of 800 to 1150 ° C. ing. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, it has been found that the spin density of the crystalline silicon film of this embodiment is at least 5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³ or less). However, this measured value is close to the detection limit of existing measuring devices, and the actual spin density is expected to be even lower.

From the above, the crystalline silicon film of this example has extremely few defects in crystal grains and can be regarded as having substantially no crystal grain boundaries. It can be considered a silicon film. The present applicant has proposed a crystalline silicon film having such a crystal structure as CGS (Con
Tinuous Grain Silicon).

[Embodiment 2] In this embodiment, the configuration of a pixel circuit having the structure shown in Embodiment 1 will be described with reference to FIG. In the top view shown in FIG. 11, attention is paid to an arbitrary pixel of the pixel circuit, and the reference numerals used in the first embodiment are quoted as they are.

FIG. 11A is a top view showing the superposition of an active layer, a gate wiring and a source wiring, and FIG. 11B is a top view showing a state where a shielding film and a pixel electrode are superposed thereon. It is. In FIG. 11A, the gate wiring 128
Crosses the active layer 114 thereunder via a gate insulating film (not shown). Although not shown, the active layer 114 includes a source region, a drain region, n
An Loff region composed of the type impurity region (c) is formed. C1 is a contact part between the source wiring 154 and the active layer 114, and C2 is a contact part between the drain wiring 157 and the active layer 114.

In FIG. 11B, the pixel TFT
A shielding film 160 on the surface of which an anodic oxide (not shown here, but refers to the anodic oxide 161 in FIG. 6B) is formed, and a pixel electrode 162 provided for each pixel.
163 are formed. Then, a storage capacitor 164 is formed in a region where the shielding film 160 and the pixel electrode 162 overlap via the anodic oxide. C3 is the drain wiring 157
And the pixel electrode 162.

In this embodiment, by using an alumina film having a relative dielectric constant as high as 7 to 9 as a dielectric of the storage capacitor, it is possible to reduce an area for forming a necessary capacitor. Further, by using the light-shielding film formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the image display section of the active matrix liquid crystal display device can be improved.

Embodiment 3 This embodiment relates to a rear projector type liquid crystal display device. FIG. 12 shows a configuration diagram of a rear projector type display device of the present embodiment.

By using a silicon film called CGS manufactured by the method of Embodiment 1, the scanning signal control circuit, the image signal control circuit, and the active matrix circuit, the scanning signal control circuit, and the image signal control circuit are formed on the same substrate. A control circuit for controlling the above can be manufactured. In this embodiment, a rear projector type liquid crystal display device is manufactured using a liquid crystal panel having such a control circuit.

The control circuit manufactured on the active matrix substrate includes a CPU for determining the entire sequence, a ROM for storing a sequence program, a RAM for storing setting data, control data, and arithmetic data by the CPU.

As shown in FIG. 12, an optical engine for projecting an image is arranged inside the housing 500, and the light path from the light source 501 to the screen 503 uniformly illuminates the liquid crystal panel. Optical system 504 having a lens array, a polarizing plate, and the like, a liquid crystal panel 505,
A mirror 506, a projection lens 507, and a mirror 508 are sequentially arranged. Reflector 5 behind light source 501
02 is attached. Optical system 504 to mirror 50
The optical member 8 is covered with a cover. Cover 5
A reflector 502 is attached so as to cover the entrance of the light 08 (the entrance of the light of the light source 501), and a screen 503 is attached so as to cover the exit of the light. The optical member 508 is dust-proof.

The control circuit of the liquid crystal panel 505 includes a main power supply 511, a video display circuit 512 for inputting a video signal to the liquid crystal panel 505, and an audio control circuit 51.
3. The infrared sensor 515 and the power switch 518 are connected. The control circuit controls these circuits and controls other circuits according to input signals from these circuits. Turning on / off the LED 517 indicates a power ON / OFF and a standby state.

An infrared sensor 515 receives infrared light from a remote controller, converts the received light into an electric signal, and outputs the electric signal to a control circuit. Then, the control circuit operates the main power supply 51.
1. The video display circuit 512 and the audio control circuit 513 are controlled to turn on / off the device and adjust the display contrast, color tone, and volume. The ON / OFF of the device and the adjustment of the volume can be also adjusted by adjusting the power switch 518 and the volume 519.

A fan 511 and a fan control circuit 512 for cooling the inside of the housing 500, particularly, the main power supply 511 and the lamp 501 are provided. The control circuit controls the fan control circuit 512 in accordance with turning on / off of the power supply, and operates and stops the fan 511. Light source 50
If one having a small calorific value is used, the liquid crystal panel 50
The heat radiation of 5 is performed by a heat radiation film provided on the active matrix substrate, and the light use efficiency of the light source 501 can be increased, so that a light source with low power consumption can be used. It is also possible to eliminate the 511 and the fan control circuit 512.

The optical members arranged in the cover 508 include:
Any of a single plate type and a three plate type may be used. In the case of single plate type,
It is necessary to provide the liquid crystal panel 505 with a color filter. In the case of the three-plate type, a color filter is unnecessary, but an optical element for separating light from a light source into three primary colors and an optical element for combining the separated light are required. FIG.
FIG. 1 shows an example of a three-plate optical system.

FIG. 14 is a configuration diagram of an optical system of a three-panel type liquid crystal display device. Three liquid crystal panels that display three primary colors of RGB (red, green, and blue) are used. An IR filter 60 is provided on an optical path from the light source 601 to the projection lens 607.
2. Homogenizer 603, polarizing plate 604, spectral surface 60
Dichroic prism 60 having 5a, 605b
5, a liquid crystal panel 612G for green and a dichroic prism 606 are sequentially arranged. On the optical path in the reflection direction of the spectral surface 605a of the dichroic prism 605,
Mirrors 608 and 609 and a liquid crystal panel for blue 612B are arranged, and mirrors 610 and 611 and a liquid crystal panel for red 612R are arranged on the optical path in the reflection direction of the spectral surface 605b. Further, a mirror and a screen (not shown) are arranged in the transmission direction of the projection lens.

The dichroic prisms 605 and 606 are optical elements for splitting light into three color components of RGB. The spectral surfaces 605a and 606a reflect the wavelength of the red component and transmit the wavelengths of the other components.
b reflects the wavelength of the blue component and transmits the wavelengths of other components. Further, a polarizing plate is attached to the active matrix substrate of the liquid crystal panel, and the polarizing plate 604 is positioned in the direction of polarization by the polarizing plate attached to the liquid crystal panel.
Are orthogonal to each other.

The light emitted from the light source 601 has its infrared component removed by an IR filter 602, its intensity is made uniform by a homogenizer 603, converted into linearly polarized light oscillating in one direction by a polarizing plate 604, and applied to a dichroic prism 605. Incident. Dichroic prism 6
Of the light incident on 05, the red component is reflected on the spectral surface 605a, and the blue component is reflected on the spectral surface 605b. The light of the green component not reflected by the spectral surfaces 605a and 605b illuminates the liquid crystal panel 612G. The light of the red component reflected by the spectral surface 605a is reflected by the mirrors 608 and 609, and illuminates the liquid crystal panel 612R. Spectral surface 605
The light of the blue component reflected by b is reflected by mirrors 610 and 611 to illuminate liquid crystal panel 612B. The three-color light of red, green, and blue is transmitted through the liquid crystal panel, whereby the two-dimensional intensity distribution of the light is modulated, and a red image,
Light for green and blue images.

The red, green, and blue lights transmitted through the liquid crystal panels 612R, 612G, and 612B are emitted from the same surface of the dichroic prism 606 by the function of the spectral surfaces 606a and 606b of the dichroic prism 606. And a color image is obtained. In order to project this color image, the emission from the dichroic mirror 606 is enlarged by a projection lens 607, reflected by a mirror (not shown), and projected on a screen.

Note that the configuration of the three-plate optical system is not limited to that shown in FIG. 14, but may of course be another configuration. For example, instead of using a dichroic prism to split light, an optical system can be designed using a dichroic mirror.

In the present embodiment, the display device of the rear projector has been described.
The present invention can be applied to a projector and a head-mounted display device.

According to the present invention, since the heat radiation film is provided, the polarizing plate can be integrated with the liquid crystal panel without deterioration.
The contrast of the liquid crystal display device is improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a liquid crystal panel according to a first embodiment.

FIG. 2 is a cross-sectional view of a liquid crystal panel according to a second embodiment.

FIG. 3 is a cross-sectional view of a liquid crystal panel according to a third embodiment.

FIG. 4 is a diagram illustrating a manufacturing process of a pixel circuit and a control circuit.

FIG. 5 illustrates a manufacturing process of a pixel circuit and a control circuit.

FIG. 6 illustrates a manufacturing process of a pixel circuit and a control circuit.

FIG. 7 illustrates a manufacturing process of a pixel circuit and a control circuit.

FIG. 8 is a cross-sectional structural view of an active matrix liquid crystal display device.

FIG. 9 is a perspective view of an active matrix liquid crystal display device.

FIG. 10 is a circuit block diagram of an active matrix liquid crystal display device.

FIG. 11 illustrates a manufacturing process of a pixel circuit and a control circuit.

FIG. 12 is a configuration diagram of a rear projector.

FIG. 13 is a configuration diagram of a rear projector.

FIG. 14 shows an optical system of a three-panel liquid crystal display device.

FIG. 15 is a cross-sectional view of a conventional liquid crystal panel.

Claims (10)

[Claims] 1. A liquid crystal panel having a first substrate having a pixel electrode connected to a thin film transistor and a liquid crystal interposed between a second substrate and a surface of the first substrate which is not opposed to the second substrate. , A heat dissipation film and a polarizing plate are provided, and no air is interposed between the heat dissipation film and the polarizing plate. 2. The heat dissipation film according to claim 1, wherein the heat dissipation film is an aluminum oxide layer, an aluminum nitride layer, a silicon carbide layer, a silicon nitride layer, a boron nitride layer,
A liquid crystal panel comprising at least one of a boron phosphide layer and a thin film diamond layer. 3. The liquid crystal panel according to claim 1, wherein the heat dissipation film has a compound layer containing Al, O, and N. 4. The method according to claim 1, wherein the compound layer comprises Si, N, O, M (M is Al, Y, L
a, a liquid crystal panel having a compound layer containing at least one element selected from Gd, Dy, and Nd). 5. The method according to claim 1, wherein:
The liquid crystal panel, wherein the first substrate includes a driving circuit including a thin film transistor for driving the thin film transistor. 6. A first substrate having a pixel electrode connected to a thin film transistor, a liquid crystal panel sandwiching liquid crystal between second substrates, a light source for illuminating the liquid crystal panel, and a light transmitted through the liquid crystal panel. An optical member for projecting, a projector-type liquid crystal display device, comprising: a heat dissipation film and a polarizing plate provided on a surface of the first substrate that is not opposed to the second substrate; A liquid crystal display device wherein no air is interposed between the heat radiation film and the polarizing plate. 7. The heat dissipating film according to claim 6, wherein the heat dissipation film includes an aluminum oxide layer, an aluminum nitride layer, a silicon carbide layer, a boron nitride layer, a boron phosphide layer,
A liquid crystal display device comprising at least one thin film diamond layer. 8. The liquid crystal display device according to claim 6, wherein the heat dissipation film has a compound layer containing Al, O, and N. 9. The method according to claim 6, wherein the compound layer comprises Si, N, O, M (M is Al, Y, L
a liquid crystal display device comprising a compound layer containing at least one element selected from the group consisting of a, Gd, Dy, and Nd). 10. The liquid crystal display device according to claim 6, wherein the first substrate includes a driving circuit including a thin film transistor for driving the thin film transistor.