JP2000269645A - Manufacture of multilayer printed wiring board - Google Patents
Manufacture of multilayer printed wiring boardInfo
- Publication number
- JP2000269645A JP2000269645A JP6920699A JP6920699A JP2000269645A JP 2000269645 A JP2000269645 A JP 2000269645A JP 6920699 A JP6920699 A JP 6920699A JP 6920699 A JP6920699 A JP 6920699A JP 2000269645 A JP2000269645 A JP 2000269645A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- resin layer
- layer
- insulating resin
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title description 9
- 239000011347 resin Substances 0.000 claims abstract description 46
- 229920005989 resin Polymers 0.000 claims abstract description 46
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 238000005488 sandblasting Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 abstract description 8
- 238000013461 design Methods 0.000 abstract description 5
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 9
- 239000011342 resin composition Substances 0.000 description 8
- 238000005553 drilling Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000012670 alkaline solution Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003999 initiator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 239000012461 cellulose resin Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004033 diameter control Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層プリント配線
板の製造方法に関し、特に高密度多層プリント配線板
の、スルーホール形成やバイアホール形成のための孔あ
け工程を合理化した多層プリント配線板の製造方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a high-density multilayer printed wiring board, in which a hole making step for forming through holes and via holes is rationalized. It relates to a manufacturing method.
【０００２】[0002]
【従来の技術】多層プリント配線板の製造において、内
部の導体パターン層間及び外部と内部の導体パターン層
間を電気的に接続する場合は、スルーホール形成やバイ
アホール形成が行われており、従来は、前記導体パター
ン層の所望の接続位置に端子を設けておき、この端子部
分において導体パターン層及び絶縁樹脂層にドリルによ
り孔をあけ、この孔内にメッキを施すようにしていた。
またあらかじめ孔あけ形成及びメッキ形成を施した積層
板を絶縁樹脂を介して積層、接着することも行われてい
た。しかし上記に述べたような方法はいずれも孔あけに
多大の工数を必要とするものであった。またドリル加工
による孔あけでは孔の小径化が困難であり、近年の多層
プリント配線板における回路の高密度化への要請に対応
できないものであった。2. Description of the Related Art In the production of multilayer printed wiring boards, when electrically connecting between internal conductor pattern layers and between the external and internal conductor pattern layers, through holes and via holes are formed. A terminal is provided at a desired connection position of the conductor pattern layer, and a hole is formed in the terminal portion by a drill in the conductor pattern layer and the insulating resin layer, and plating is performed in the hole.
In addition, a laminated plate that has been subjected to drilling and plating has been laminated and bonded via an insulating resin. However, all of the above-mentioned methods require a large number of man-hours for drilling. Also, it is difficult to reduce the diameter of the hole by drilling, and it has not been possible to respond to the recent demand for higher density of circuits in a multilayer printed wiring board.
【０００３】そこで特公平２−３６７６号公報に開示さ
れているように、電気的に接続すべき導体層の最下層よ
りも上の層にあらかじめ孔をあけておき、この孔を介し
て上側からレーザを照射し、最上層から最下層までの樹
脂層を除去することにより孔あけ加工を施し、この孔内
にメッキを施すことにより、スルーホールやバイアホー
ルの小径化を達成する工法が提案されている。また更に
特開平６−３３４３０１号公報に開示されているよう
に、レーザにてスルーホール用の孔を加工した後、この
スルーホールにサンドブラスト加工を施すことにより、
スルーホール用の孔の内壁部に存在する、熱溶融固化し
た絶縁樹脂層の変質層を除去する工法が提案されてい
る。[0003] Therefore, as disclosed in Japanese Patent Publication No. 2-3676, a hole is previously formed in a layer above the lowermost layer of the conductor layer to be electrically connected, and from the upper side through this hole. A method has been proposed in which laser irradiation is performed to remove the resin layer from the uppermost layer to the lowermost layer, perform drilling, and then plating this hole to reduce the diameter of through holes and via holes. ing. Further, as disclosed in Japanese Patent Application Laid-Open No. 6-334301, after a hole for a through hole is processed by a laser, the through hole is subjected to sandblasting,
There has been proposed a method of removing a deteriorated layer of an insulating resin layer which has been melted and solidified and is present on an inner wall portion of a through hole.
【０００４】[0004]
【発明が解決しようとする課題】しかし上記のような従
来のスルーホール加工やバイアホール加工の工法におい
ては、そのスルーホールやバイアホールの孔径はレーザ
光の光径に依存して制限されるものであり、スルーホー
ルやバイアホールの孔径の設計の自由度が高い工法が求
められていた。However, in the above-described conventional methods of through-hole processing and via-hole processing, the diameters of the through-holes and via-holes are limited depending on the beam diameter of the laser beam. Therefore, there is a demand for a construction method having a high degree of freedom in designing the hole diameters of through holes and via holes.
【０００５】本発明は上記の点に鑑みてなされたもので
あり、スルーホールやバイアホールの孔径の設計の自由
度を高くして、回路設計の自由度を向上することができ
る多層プリント配線板の製造方法を提供することを目的
とするものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a high degree of freedom in designing the diameters of through holes and via holes to improve the degree of freedom in circuit design. It is an object of the present invention to provide a production method of
【０００６】[0006]
【課題を解決するための手段】本発明に係る多層プリン
ト配線板の製造方法は、複数の導体層３と、導体層３間
に介在する絶縁樹脂層２とを有する積層板１の、導体層
３の所定箇所に孔６をあけ、この孔６から表出する絶縁
樹脂層２にサンドブラスト処理を施して絶縁樹脂層２に
スルーホール又はバイアホール形成用の孔７を形成する
工程を含むことを特徴とするものである。According to the present invention, there is provided a method for manufacturing a multilayer printed wiring board, comprising the steps of: forming a conductive layer on a laminated board having a plurality of conductive layers and an insulating resin layer interposed between the conductive layers; 3, forming a hole 7 for forming a through hole or a via hole in the insulating resin layer 2 by subjecting the insulating resin layer 2 exposed from the hole 6 to sandblasting. It is a feature.
【０００７】[0007]
【発明の実施の形態】以下、本発明の実施の形態を説明
する。Embodiments of the present invention will be described below.
【０００８】本発明に用いる積層板１は、複数の導体層
３と、導体層３間に介在する絶縁樹脂層２とを有するも
のである。この積層板１の形成方法は特に限定するもの
ではなく、一般に多層プリント配線板の製造に供される
ものを用いることができ、例えばガラス布基材に、エポ
キシ樹脂、ポリイミド樹脂等の熱硬化性樹脂や無機フィ
ラー等を含む樹脂組成物を含浸、乾燥させてなるプリプ
レグの両面に銅箔等の金属箔を配置し、この状態で加熱
加圧することにより形成される両面金属張積層板１を用
いることができる。また回路形成された積層板１に、更
に絶縁樹脂層２と導体層３を積層成形して得られる積層
板１を用いることもできる。The laminate 1 used in the present invention has a plurality of conductor layers 3 and an insulating resin layer 2 interposed between the conductor layers 3. The method of forming the laminated board 1 is not particularly limited, and a method generally used for manufacturing a multilayer printed wiring board can be used. For example, a thermosetting resin such as an epoxy resin, a polyimide resin, etc. A metal foil such as a copper foil is placed on both surfaces of a prepreg obtained by impregnating and drying a resin composition containing a resin, an inorganic filler, and the like, and a double-sided metal-clad laminate 1 formed by applying heat and pressure in this state is used. be able to. Further, the laminated plate 1 obtained by laminating the insulating resin layer 2 and the conductor layer 3 on the laminated plate 1 on which a circuit is formed can also be used.
【０００９】以下、図１に両面金属張積層板１を用いる
場合を例示して本発明を説明する。Hereinafter, the present invention will be described by exemplifying a case where a double-sided metal-clad laminate 1 is used in FIG.
【００１０】図１（ａ）に示すような両面金属張積層板
１の両面に、エッチングレジスト５を形成する。エッチ
ングレジスト５の形成にあたっては、まず図１（ｂ）に
示すように、バーコーター、ロールコータ、コンマコー
タ、カーテンコータなどの方法により塗布、印刷する
か、あるいは、ドライフィルム状としたものをラミネー
トする等の方法により、導体層３の表面に感光性樹脂組
成物等からなる樹脂層４を形成する。次に、感光性樹脂
組成物として光硬化性樹脂組成物を用いる場合は、絶縁
樹脂層２を介在し積層された一対の導体層３のうちの一
方の側、すなわちここでは上層の導体層３側において所
望のスルーホールやバイアホール形成部分をマスクした
状態で樹脂層４を露光し、その後、非露光部分を現像除
去して、図１（ｃ）に示すように、露光部分をエッチン
グレジスト５として形成する。ここで光硬化性樹脂組成
物としては、その非露光部分が１％Ｎａ2ＣＯ3水溶液等
の弱アルカリ溶液で現像可能であり、またその露光硬化
物が耐強酸性を有すると共に３％ＮａＯＨ溶液等の強ア
ルカリ溶液で剥離可能なものを用いることが好ましい。
このような光硬化性樹脂組成物としては、不飽和ポリエ
ステル、適宜の不飽和モノマー、光重合開始剤等からな
る感光性樹脂組成物や、ウレタン（メタ）アクリレート
オリゴマー、水溶性セルロース樹脂、光重合開始剤、
（メタ）アクリレートモノマー等からなる感光性樹脂組
成物を用いることができ、市販品として提供されている
ものとしては、例えば東京応化工業株式会社製の厚み３
０μｍの感光性ドライフィルム［品番 ＢＦ−６０３Ｔ
−３］を用いることができる。An etching resist 5 is formed on both sides of a double-sided metal-clad laminate 1 as shown in FIG. In forming the etching resist 5, first, as shown in FIG. 1B, coating and printing are performed by a method such as a bar coater, a roll coater, a comma coater, a curtain coater, or a dry film is laminated. The resin layer 4 made of a photosensitive resin composition or the like is formed on the surface of the conductor layer 3 by the method described above. Next, when a photocurable resin composition is used as the photosensitive resin composition, one side of a pair of conductor layers 3 stacked with the insulating resin layer 2 interposed therebetween, that is, the upper conductor layer 3 in this case, On the side, the resin layer 4 is exposed in a state where a desired through-hole or via-hole forming portion is masked, and then the unexposed portion is removed by development, and as shown in FIG. Form as Here, as the photocurable resin composition, the unexposed portion can be developed with a weak alkaline solution such as a 1% aqueous solution of Na 2 CO 3 , and the exposed cured product has a strong acid resistance and a 3% NaOH solution. It is preferable to use a material that can be peeled off with a strong alkaline solution such as
Examples of such a photocurable resin composition include a photosensitive resin composition comprising an unsaturated polyester, an appropriate unsaturated monomer, a photopolymerization initiator, and the like; a urethane (meth) acrylate oligomer; a water-soluble cellulose resin; Initiator,
A photosensitive resin composition comprising a (meth) acrylate monomer or the like can be used, and as a commercially available product, for example, a thickness 3 manufactured by Tokyo Ohka Kogyo Co., Ltd.
0 μm photosensitive dry film [Model BF-603T]
-3] can be used.
【００１１】絶縁樹脂層２のスルーホールやバイアホー
ル形成部分に、サンドブラスト処理を施し、図１（ｅ）
に示すように、絶縁樹脂層２に、孔６が形成されなかっ
た側の導体層３、すなわちここでは下層の導体層３まで
達するスルーホール形成用又はバイアホール形成用の孔
７を形成する。ここでサンドブラスト処理に用いる砥粒
としては、１〜１５０μｍの範囲の粒径を有し、ガラス
粉、アルミナ、シリカ、ガラスビーズ、炭化ケイ素、酸
化ジルコニウム等の材質からなる粒子を用いることがで
き、この砥粒を、導体層３に形成した孔６から表出する
絶縁樹脂層２に０．５〜６ｋｇ/ｃｍ2の範囲のブラスト
圧力で噴射することが好ましい。具体的には例えば、株
式会社不二製作所製のサンドブラスト機［品番 ＳＣ−
２０２］を用い、粒径２５μｍの炭化ケイ素粉を研磨材
として用いて、ブラスト圧力１．５ｋｇ／ｃｍ2で５分
間サンドブラスト処理を施すものである。A portion of the insulating resin layer 2 where a through hole or a via hole is formed is subjected to a sand blasting process, and the portion shown in FIG.
As shown in (1), a hole 7 for forming a through hole or a via hole is formed in the insulating resin layer 2 on the side of the conductor layer 3 where the hole 6 is not formed, that is, in this case, the conductor layer 3 reaches the lower layer. Here, as abrasive grains used for sandblasting, particles having a particle size in the range of 1 to 150 μm, glass powder, alumina, silica, glass beads, silicon carbide, particles made of a material such as zirconium oxide can be used, It is preferable that these abrasive grains are sprayed onto the insulating resin layer 2 exposed from the holes 6 formed in the conductor layer 3 at a blast pressure in the range of 0.5 to 6 kg / cm 2 . Specifically, for example, a sand blasting machine manufactured by Fuji Manufacturing Co., Ltd. [part number SC-
202], and sand blasting is performed for 5 minutes at a blast pressure of 1.5 kg / cm 2 using silicon carbide powder having a particle size of 25 μm as an abrasive.
【００１２】次に、バイアホール形成を行う場合は、積
層板１を３％ＮａＯＨ溶液等の強アルカリ溶液で処理し
てエッチングレジスト５を剥離した後、アディティブ法
やサブトラクティブ法等により導体層３に回路を形成す
るものであり、このとき図１（ｆ）に示すように絶縁樹
脂層２に形成した孔７の内壁にメッキ層８を形成してバ
イアホールを形成し、絶縁樹脂層２を介して積層された
導体層３間を導通するものである。Next, when forming a via hole, the laminate 1 is treated with a strong alkaline solution such as a 3% NaOH solution to remove the etching resist 5, and then the conductive layer 3 is formed by an additive method or a subtractive method. In this case, as shown in FIG. 1 (f), a plating layer 8 is formed on the inner wall of the hole 7 formed in the insulating resin layer 2 to form a via hole, and the insulating resin layer 2 is formed. This is to conduct between the conductor layers 3 laminated through the intermediary.
【００１３】またスルーホール形成を行う場合は、まず
図１（ｄ）に示すように上層の導体層３にエッチング処
理により孔６を形成する。次に、下層の導体層３に形成
した樹脂層４に、上層の場合における図１（ｃ）に示す
場合と同様の露光、現像処理を施して、下層の樹脂層４
をエッチンレジスト５として形成する。更に上層の場合
における図１（ｄ）に示す場合と同様のエッチング処理
を施して、下層の導体層３の、上層の導体層３に形成し
た孔６に対応する位置に孔を設ける。このように両側の
導体層３にそれぞれ孔６を設けた状態で絶縁樹脂層２の
スルーホールやバイアホール形成部分に、サンドブラス
ト処理を施し、絶縁樹脂層２に積層板１を貫通するスル
ーホール形成用の孔７を形成する。次に積層板１を３％
ＮａＯＨ溶液等の強アルカリ溶液で処理してエッチング
レジスト５を剥離した後、アディティブ法やサブトラク
ティブ法等により導体層３に回路を形成するものであ
り、このとき絶縁樹脂層２に形成した孔７の内壁にメッ
キ層８を形成してスルーホールを形成し、絶縁樹脂層２
を介して積層された導体層３間を導通するものである。When forming a through hole, first, as shown in FIG. 1D, a hole 6 is formed in the upper conductor layer 3 by etching. Next, the resin layer 4 formed on the lower conductor layer 3 is exposed and developed in the same manner as in the case of the upper layer shown in FIG.
Is formed as an etchant resist 5. Further, by performing the same etching treatment as that shown in FIG. 1D in the case of the upper layer, holes are provided in the lower conductor layer 3 at positions corresponding to the holes 6 formed in the upper conductor layer 3. In the state where the holes 6 are provided in the conductor layers 3 on both sides in this manner, a portion of the insulating resin layer 2 where a through hole or a via hole is formed is subjected to sandblasting, and a through hole is formed in the insulating resin layer 2 so as to penetrate the laminate 1. Holes 7 are formed. Next, 3% of laminated board 1
After removing the etching resist 5 by treatment with a strong alkaline solution such as a NaOH solution, a circuit is formed in the conductor layer 3 by an additive method, a subtractive method, or the like. At this time, the holes 7 formed in the insulating resin layer 2 are formed. A plating layer 8 is formed on the inner wall of the substrate to form a through hole, and the insulating resin layer 2 is formed.
Are conducted between the conductor layers 3 laminated through the intermediary layer.
【００１４】このようにして多層プリント配線板を製造
すると、スルーホールやバイアホールを形成するための
孔７を絶縁樹脂層２に容易に形成することができるもの
である。またレーザ光径により絶縁樹脂層２に形成する
孔径が規制されるレーザ加工による孔あけの場合と異な
り、絶縁樹脂層２に形成する孔７の孔径が制限されず、
スルーホールやバイアホールの孔径の設計の自由度を高
くして、多層プリント配線板の回路設計の自由度を向上
することができるものである。またエッチングレジスト
や導体層３がサンドブラストのマスクとして機能し、正
確な孔径制御を行うことができるものであり、また孔径
の異なる孔７を絶縁樹脂層２に同時に形成する場合は、
導体層３に設けるスルーホール形成用やバイアホール形
成用の孔６の孔径を制御するだけで、容易に形成するこ
とができるものである。When the multilayer printed wiring board is manufactured in this manner, holes 7 for forming through holes and via holes can be easily formed in the insulating resin layer 2. Also, unlike the case of drilling by laser processing in which the hole diameter formed in the insulating resin layer 2 is regulated by the laser beam diameter, the hole diameter of the hole 7 formed in the insulating resin layer 2 is not limited,
The degree of freedom in designing the hole diameters of the through holes and the via holes can be increased, and the degree of freedom in the circuit design of the multilayer printed wiring board can be improved. In addition, the etching resist and the conductor layer 3 function as a mask for sandblasting, so that accurate hole diameter control can be performed. When holes 7 having different hole diameters are simultaneously formed in the insulating resin layer 2,
It can be easily formed only by controlling the diameter of the hole 6 for forming a through hole or a via hole provided in the conductor layer 3.
【００１５】[0015]
【発明の効果】上記のように本発明に係る多層プリント
配線板の製造方法は、複数の導体層と、導体層間に介在
する絶縁樹脂層とを有する積層板の、導体層の所定箇所
に孔をあけ、この孔から表出する絶縁樹脂層にサンドブ
ラスト処理を施して絶縁樹脂層にスルーホール又はバイ
アホール形成用の孔を形成する工程を含むものであり、
スルーホールやバイアホールを形成するための孔を絶縁
樹脂層に容易に形成することができるものであり、また
絶縁樹脂層に形成する孔の孔径が制限されず、スルーホ
ールやバイアホールの孔径の設計の自由度を高くして、
多層プリント配線板の回路設計の自由度を向上すること
ができるものであり、また孔径の異なるスルーホールや
バイアホール形成用の孔を絶縁樹脂層に同時に形成する
ことが容易となるものである。As described above, the method for manufacturing a multilayer printed wiring board according to the present invention provides a laminated board having a plurality of conductor layers and an insulating resin layer interposed between the conductor layers. A step of forming a hole for forming a through hole or a via hole in the insulating resin layer by performing sandblasting on the insulating resin layer exposed from the hole,
A hole for forming a through hole or a via hole can be easily formed in the insulating resin layer, and a hole diameter of the hole formed in the insulating resin layer is not limited. By increasing the freedom of design,
It is possible to improve the degree of freedom in circuit design of the multilayer printed wiring board, and it is easy to simultaneously form through holes having different hole diameters and holes for forming via holes in the insulating resin layer.
【図１】（ａ）乃至（ｆ）は本発明の実施の形態の一例
における工程を示す概略の断面図である。FIGS. 1A to 1F are schematic sectional views showing steps in an example of an embodiment of the present invention.
１ 積層板 ２ 絶縁樹脂層 ３ 導体層 ６ 孔 ７ 孔 REFERENCE SIGNS LIST 1 laminated board 2 insulating resin layer 3 conductor layer 6 hole 7 hole
Claims (1)
縁樹脂層とを有する積層板の、導体層の所定箇所に孔を
あけ、この孔から表出する絶縁樹脂層にサンドブラスト
処理を施して絶縁樹脂層にスルーホール又はバイアホー
ル形成用の孔を形成する工程を含むことを特徴とする多
層プリント配線板の製造方法。1. A laminated board having a plurality of conductor layers and an insulating resin layer interposed between the conductor layers, a hole is formed in a predetermined portion of the conductor layer, and the insulating resin layer exposed from the hole is subjected to sandblasting. Forming a hole for forming a through hole or a via hole in the insulating resin layer by using the method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6920699A JP2000269645A (en) | 1999-03-15 | 1999-03-15 | Manufacture of multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6920699A JP2000269645A (en) | 1999-03-15 | 1999-03-15 | Manufacture of multilayer printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000269645A true JP2000269645A (en) | 2000-09-29 |
Family
ID=13396030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6920699A Withdrawn JP2000269645A (en) | 1999-03-15 | 1999-03-15 | Manufacture of multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000269645A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1043047A (en) * | 1996-07-31 | 1998-02-17 | Matsushita Electric Ind Co Ltd | Pressure cooker |
| US20100230142A1 (en) * | 2007-10-23 | 2010-09-16 | Ube Industries, Ltd. | Method for manufacturing printed wiring board |
| JP2011160005A (en) * | 2011-05-25 | 2011-08-18 | Tatsuta Electric Wire & Cable Co Ltd | Partially-multilayered flexible printed wiring board |
| CN102612276A (en) * | 2012-03-13 | 2012-07-25 | 惠州中京电子科技股份有限公司 | Manufacturing process for pores of multilayer HDI (high density interconnector) circuit board |
| CN103025054A (en) * | 2011-09-26 | 2013-04-03 | 京瓷Slc技术株式会社 | Printed circuit board, mount structure thereof, and methods of producing these |
| JP2013093485A (en) * | 2011-10-27 | 2013-05-16 | Kyocer Slc Technologies Corp | Manufacturing method of wiring board and manufacturing method of packaging structure using the same |
| JP2016171339A (en) * | 2016-05-23 | 2016-09-23 | 京セラ株式会社 | Method for manufacturing wiring board |
| JP2022071490A (en) * | 2020-10-28 | 2022-05-16 | 味の素株式会社 | Manufacturing method of printed wiring board |
-
1999
- 1999-03-15 JP JP6920699A patent/JP2000269645A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1043047A (en) * | 1996-07-31 | 1998-02-17 | Matsushita Electric Ind Co Ltd | Pressure cooker |
| US20100230142A1 (en) * | 2007-10-23 | 2010-09-16 | Ube Industries, Ltd. | Method for manufacturing printed wiring board |
| TWI455671B (en) * | 2007-10-23 | 2014-10-01 | Ube Industries | Printed circuit board manufacturing method |
| JP2011160005A (en) * | 2011-05-25 | 2011-08-18 | Tatsuta Electric Wire & Cable Co Ltd | Partially-multilayered flexible printed wiring board |
| CN103025054A (en) * | 2011-09-26 | 2013-04-03 | 京瓷Slc技术株式会社 | Printed circuit board, mount structure thereof, and methods of producing these |
| JP2013093485A (en) * | 2011-10-27 | 2013-05-16 | Kyocer Slc Technologies Corp | Manufacturing method of wiring board and manufacturing method of packaging structure using the same |
| CN102612276A (en) * | 2012-03-13 | 2012-07-25 | 惠州中京电子科技股份有限公司 | Manufacturing process for pores of multilayer HDI (high density interconnector) circuit board |
| JP2016171339A (en) * | 2016-05-23 | 2016-09-23 | 京セラ株式会社 | Method for manufacturing wiring board |
| JP2022071490A (en) * | 2020-10-28 | 2022-05-16 | 味の素株式会社 | Manufacturing method of printed wiring board |
| JP7371606B2 (en) | 2020-10-28 | 2023-10-31 | 味の素株式会社 | Manufacturing method of printed wiring board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20060606 |