JP2000269512A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To realize a semiconductor device having high TFT characteristics. SOLUTION: In a pixel matrix circuit of an AM-LCD, a lower electrode 114 of a storage capacitor is made to contain an element belonging to Group 15 and a catalyst element used for crystallization so as to reduce resistance, and furthermore, a dielectric material of the storage capacitor. , The capacity can be increased without increasing the area for forming the capacitor. Therefore, AM-L with a diagonal of 1 inch or less
Even in a CD, a sufficient storage capacity can be secured without lowering the aperture ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to an electro-optical device represented by a liquid crystal display panel and a configuration of an electronic device having such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (thickness of several hundreds to several thousands) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

For example, in a liquid crystal display device, a pixel portion (also referred to as a pixel matrix circuit) for individually controlling pixel regions arranged in a matrix, a driving circuit (hereinafter, referred to as a driver circuit) for controlling the pixel portion, Attempts have been made to apply TFTs to any electric circuit such as a logic circuit (a processor circuit or a memory circuit) for processing a data signal from the outside.

At present, a TFT using an amorphous silicon film (amorphous silicon film) as an active layer has been put into practical use. The circuit requires a TFT using a crystalline silicon film (polysilicon film, polycrystalline silicon film, etc.).

For example, as a method of forming a crystalline silicon film on a glass substrate, there are known techniques described in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329 by the present applicant. The techniques described in these publications use a catalyst element that promotes crystallization of an amorphous silicon film, thereby providing 500
It is possible to form a crystalline silicon film having excellent crystallinity by heat treatment at about 600 ° C. for about 4 hours.

[0007] In particular, the technique described in Japanese Patent Application Laid-Open No. 8-78329 is to perform the crystal growth substantially parallel to the substrate surface by applying the above-mentioned technique, and the inventors have found that the formed crystallized region is particularly laterally oriented. It is called the growth area (or lateral growth area).

However, even if a driver circuit is formed using such TFTs, the required performance is still not completely satisfied. In particular, it is impossible at present to configure a high-speed logic circuit that requires an extremely high-speed operation from megahertz to gigahertz with a conventional TFT.

[0009]

As described above, in order to realize a system-on-panel with a built-in logic circuit, there is a need to develop a completely new material that has not existed before.

The present invention meets such a demand, and provides an extremely high-performance TFT structure capable of forming a high-speed logic circuit which cannot be manufactured by a conventional TFT, and a manufacturing method thereof. That is the task.

Further, the invention of the present application has improved the pixel section. Specifically, the present invention provides a structure for forming a storage capacitor capable of securing a large capacity in a small area and a manufacturing method thereof.

It is another object of the present invention to provide a highly reliable electro-optical device by forming each circuit of an electro-optical device represented by an AM-LCD with a TFT having an appropriate structure according to a function.

[0013]

According to the present invention, a source region, a drain region, and a channel forming region formed between the source region and the drain region are formed on an insulating surface. At least a gate insulating film formed in contact with the channel formation region, and a wiring formed in contact with the gate insulating film, and a part of the source region and the drain region includes silicon crystal. A semiconductor device including an element which promotes the formation of a semiconductor.

In the above structure, the wiring is characterized in that the wiring includes at least one layer mainly composed of one kind of element selected from tantalum, molybdenum, tungsten, titanium, chromium, and silicon.

In the above structure, a part of the source region and the drain region is selected from nickel, cobalt, palladium, germanium, platinum, iron, and copper at a concentration of 1 × 10 ¹⁹ atoms / cm ³ or more. It is characterized by containing an element or a plurality of elements.

According to another aspect of the present invention, in a semiconductor device having a driver circuit and a pixel portion formed on the same substrate, a thickness of a dielectric of a storage capacitor included in the pixel portion is set to be smaller than that of the pixel portion. A thinner than the thickness of the gate insulating film of the pixel TFT included in the semiconductor device.

In the above structure, the dielectric of the storage capacitor included in the pixel portion is formed through at least a step of thermal oxidation.

In the above structure, one electrode of the storage capacitor is a semiconductor film, and the electrode has 1 × 10 ¹⁹ at.
It is characterized by containing an element selected from nickel, cobalt, palladium, germanium, platinum, iron and copper at a concentration of oms / cm ³ or more.

Further, in the above structure, the electrode has 5
At a concentration of × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ , 15
It is characterized by containing elements belonging to the group.

In the above structure, the pixel TFT
The thickness of the gate insulating film is 50 to 200 nm, and the thickness of the dielectric of the storage capacitor is 5 to 50 nm.

In the above structure, the pixel TFT
Comprises an active layer, an insulating film in contact with the active layer, and a wiring in contact with the insulating film, wherein the active layer has a channel forming region, a source region formed on both sides of the channel forming region, and A drain region, and an element selected from nickel, cobalt, palladium, germanium, platinum, iron, and copper at a concentration of 1 × 10 ¹⁹ atoms / cm ³ or more in the source region and part of the drain region. It is characterized by being included.

In the above structure, a low-concentration impurity region may be provided between at least one of the channel formation region and the source region or at least one of the channel formation region and the drain region. Features.

Further, the invention for realizing the above structure is a method for manufacturing a semiconductor device having a driver circuit and a pixel portion on the same substrate, wherein a semiconductor layer is formed on a substrate by using a catalytic element. A first step of selectively adding an element belonging to Group 15 of the periodic table to the semiconductor layer;
A third step of collecting in a region to which an element belonging to Group V is added, a fourth step of forming an insulating film on the semiconductor layer,
A fifth step of removing a part of the insulating film and exposing a part of the active layer; a sixth step of forming a thermal oxide film on a part of the exposed active layer; A seventh step of forming a wiring on the thermal oxide film, an eighth step of forming a sidewall on a side surface of the wiring, and a group 15 of the periodic table with respect to the active layer using the wiring and the sidewall as a mask. A ninth step of adding an element belonging to group, a tenth step of removing the sidewall, an eleventh step of adding an element belonging to group 15 of the periodic table to the active layer using the wiring as a mask, A twelfth step of forming a resist mask on the region to be formed and adding an element belonging to Group 13 of the periodic table, and activating the elements belonging to Group 13 of the periodic table and Group 15 of the periodic table added to the active layer; Perform processing 13 and steps, a method for manufacturing a semiconductor device characterized by having a.

Another aspect of the invention is a method of manufacturing a semiconductor device having a driver circuit and a pixel portion on the same substrate, comprising a first step of forming a semiconductor layer on the substrate using a catalytic element. A second step of forming an insulating film on the semiconductor layer, and a third step of selectively adding an element belonging to Group 15 of the periodic table to the semiconductor layer using a mask;
A fourth step of removing a part of the insulating film using the mask and exposing a part of the active layer, and applying a heat treatment to the catalytic element in a region where an element belonging to Group 15 of the periodic table is added. A fifth step of collecting, a sixth step of forming a thermal oxide film on a part of the exposed active layer, a seventh step of forming a wiring on the insulating film and the thermal oxide film, An eighth step of forming a sidewall on a side surface, and a ninth step of adding an element belonging to Group 15 of the periodic table to the active layer using the wiring and the sidewall as a mask.
A step, a tenth step of removing the sidewall,
Using the wiring as a mask, one of the periodic table
An eleventh step of adding an element belonging to Group 5; a twelfth step of forming a resist mask on a region to be NTFT and adding an element belonging to Group 13 of the periodic table; and the periodic table added to the active layer. And a thirteenth step of activating the elements belonging to Group 13 and Group 15 of the periodic table.

Further, in the above structure, a part of the active layer includes at least a region serving as a storage capacitor of the pixel portion.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view of an AM-LCD in which a driver circuit and a pixel portion are integrally formed on the same substrate. Here, a CMOS circuit is shown as a basic circuit constituting a driver circuit, and a TFT having a double gate structure is shown as a pixel TFT. Of course, not only the double gate structure but also a triple gate structure or a single gate structure may be used.

In FIG. 1, reference numeral 101 denotes a substrate having heat resistance, which may be a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate (typically, a stainless steel substrate). Whichever substrate is used, a base film (preferably, an insulating film containing silicon as a main component) may be provided as necessary.

Reference numeral 102 denotes a silicon oxide film provided as a base film, on which an active layer of a driver TFT and a pixel TFT are formed.
Of the active layer and a semiconductor layer serving as a lower electrode of the storage capacitor are formed. In this specification, “electrode” means
It is a part of the “wiring” and refers to a portion where electrical connection with another wiring or a portion intersecting with a semiconductor layer is made. Therefore,
For convenience of explanation, we use "wiring" and "electrode" properly,
It is assumed that the term “electrode” is always included in the term “wiring”.

Referring to FIG. 1, the active layer of the driver TFT includes a source region 103, a drain region 104, an LDD (lightly doped drain) region 105 and a channel forming region 106 of an N-channel type TFT (hereinafter referred to as NTFT). It is formed of a source region 107, a drain region 108, and a channel formation region 109 of a channel type TFT (hereinafter referred to as PTFT).

The active layer of the pixel TFT (here, NTFT is used) is formed of a source region 110, a drain region 111, LDD regions 112a and 112b, and channel forming regions 113a and 113b. Further, the semiconductor layer extended from the drain region 111 is used as the lower electrode 114 of the storage capacitor.

In FIG. 1, the lower electrode 114 is connected to the pixel TF
Although it is directly connected to the drain region 111 of T,
The lower electrode 114 and the drain region 11 are indirectly connected to each other.
1 may be electrically connected.

The lower electrode 114 is doped with an element belonging to Group 15 of the periodic table with respect to the semiconductor layer. Further, in the present invention, 1 × 10 ¹⁹
atoms / cm ³ or more (typically 3 × 10 ¹⁹ to 1 × 10 ²¹ ato
It is characterized in that the catalyst element used for crystallization of the semiconductor film exists at a concentration of ms / cm ³ ). That is, even if a voltage is not applied to the upper wiring 122 of the storage capacitor, it can be used as an electrode as it is, which is effective in reducing the power consumption of the AM-LCD.

Similarly, the source region 1 of the pixel TFT is
10, a drain region 111, source regions 103 and 107 of the driver TFT, and drain regions 104 and 10
One of the features of the present invention is that a region (a region shown by oblique lines in FIG. 1) containing a catalyst element used for crystallization of a semiconductor film exists in a part of the semiconductor device. In FIG. 1, the drain wiring 127 is shown.
The contact portion where the drain region 104 of the NTFT and the drain region 108 of the PTFT are in contact is a region containing a catalytic element. With such a configuration, a good ohmic contact can be obtained due to the presence of the catalytic element, which is effective. Probably because silicidation is caused by the presence of the catalyst element.

Then, a gate insulating film is formed to cover the active layer and the lower electrode of the storage capacitor. In the present invention, the dielectric 118 of the storage capacitor is used as the gate insulating film 1 of the pixel TFT.
It is formed thinner than 17. Typically, the thickness of the storage capacitor dielectric 118 is 5 to 50 nm (preferably 10 to 30 nm).
nm), and the thickness of the gate insulating film 117 is 50 to 200 nm.
(Preferably 100 to 150 nm).

As described above, the lower electrode 114 of the storage capacitor is made to contain the element belonging to Group 15 of the periodic table and the catalyst element used for crystallization, thereby lowering the resistance of the lower electrode 114 and further increasing the dielectric constant of the storage capacitor. By making the body thin, capacity can be gained without increasing the area for forming a capacitor.

Here, the gate insulating film 117 of the pixel TFT and the gate insulating films 115, 1
Reference numeral 16 denotes the same insulating film having the same thickness, but is not particularly limited. For example, a configuration may be adopted in which at least two or more TFTs having different gate insulating films exist on the same substrate depending on circuit characteristics.

Next, the gate insulating films 115, 116, 11
7, gate wirings 119 and 12 of the driver TFT are provided.
0 and the gate wiring 121 of the pixel TFT are formed. At the same time, an upper electrode 122 of the storage capacitor is formed on the dielectric 118 of the storage capacitor. Gate wiring 119-12
1 and the material for forming the upper electrode 122 of the storage capacitor are 800 to 1150 ° C. (preferably 900 to 1100 ° C.).
(° C.) is used.

Typically, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, etc.)
Or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, a titanium film, or the like), a silicide film obtained by silicidizing the metal film, or a nitrided film (a tantalum nitride film, a tungsten nitride film, a titanium nitride film, or the like). But it is good. Further, these may be freely combined and laminated.

When the metal film is used, it is preferable that the metal film has a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with a silicon nitride film is effective. In FIG. 1, a silicon nitride film 123 is provided to prevent oxidation of the gate wiring.

Next, reference numeral 124 denotes a first interlayer insulating film, which is formed of an insulating film containing silicon (single-layer or laminated). As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, a silicon oxynitride film (having a higher nitrogen content than oxygen), and a silicon nitride oxide film (having a higher oxygen content than nitrogen) ) Can be used.

A contact hole is provided in the first interlayer insulating film 124, and the source wirings 125 and 126, the drain wiring 127, and the pixel TF of the driver TFT are provided.
A source wiring 128 and a drain wiring 129 of T are formed. A passivation film 130 and a second interlayer insulating film 131 are formed thereon, and a black mask (light shielding film) 132 is further formed thereon. Further, a third interlayer insulating film 133 is formed on the black mask 132,
After providing the contact holes, the pixel electrodes 134 are formed.

In FIG. 1, a black mask (light-shielding film) 132 is formed on the second interlayer insulating film 131, but is not particularly limited, and may be formed as needed. For example, a configuration in which a light shielding film is provided on the opposite substrate may be adopted,
A structure in which a light-shielding film using the same material as the gate wiring is provided under each TFT may be employed.

Second interlayer insulating film 131 or third interlayer insulating film 1
As 33, a resin film having a small relative dielectric constant is preferable. As the resin film, a polyimide film, an acrylic film, a polyamide film, a BCB (benzocyclobutene) film, or the like can be used.

The pixel electrode 134 is a transmission type A
To manufacture an M-LCD, a transparent conductive film typified by an ITO film may be used, and to manufacture a reflective AM-LCD, a metal film having a high reflectivity typified by an aluminum film may be used.

In FIG. 1, the pixel electrode 134 is electrically connected to the drain region 111 of the pixel TFT via the drain electrode 129, but the pixel electrode 134 is directly connected to the drain region 111. It is good also as a structure.

The AM-LCD having the above structure is
The lower electrode 114 of the storage capacitor contains an element belonging to Group 15 of the periodic table and a catalyst element used for crystallization to form the lower electrode 114.
14 is characterized in that the resistance of the storage capacitor is reduced and the dielectric of the storage capacitor is formed thinner than the gate insulating film of the pixel TFT. By doing so, it is possible to realize a high-performance TFT and a storage capacitor capable of securing a large capacitance in a small area.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0048]

[Embodiment 1] In this embodiment, a manufacturing process for realizing the structure of FIG. 1 described in "Embodiment of the Invention" will be described. 2 to 4 are used for the description.

First, a quartz substrate 201 is prepared as a substrate, and a 20-nm-thick silicon oxide film (also referred to as a base film) is formed thereon.
202 and an amorphous silicon film (not shown) were continuously formed without opening to the atmosphere. This prevents impurities such as boron contained in the air from adsorbing to the lower surface of the amorphous silicon film.

In this embodiment, an amorphous silicon (amorphous silicon) film is used, but another semiconductor film may be used. A microcrystalline silicon (microcrystalline silicon) film or an amorphous silicon germanium film may be used. As means for forming the base film and the semiconductor film,
A PCVD method, an LPCVD method, a sputtering method, or the like can be used.

Next, the amorphous silicon film is crystallized. In this embodiment, a technique described in Japanese Patent Application Laid-Open No. 9-313260 was used as a crystallization means. The technology described in the publication discloses nickel, cobalt, palladium, germanium, platinum, iron, as a catalyst element for promoting crystallization of a silicon film.
An element selected from copper is used.

In this embodiment, nickel is selected as a catalyst element, and a layer containing nickel is formed on the amorphous silicon film.
Heat treatment was performed at 550 ° C. for 14 hours for crystallization. Then, the formed crystalline silicon (polysilicon) film was patterned to form a semiconductor layer 203 of the driver TFT and a semiconductor layer 204 of the pixel TFT. (Fig. 2 (A))

The driver TFT and the pixel TFT
Before and after the formation of the semiconductor layer of FIG.
An impurity element (phosphorus or boron) for controlling the threshold voltage of the FT may be added. This process is NTFT
Alternatively, it may be performed only for the PTFT, or may be performed for both.

Next, as shown in FIG. 2B, resist masks 205a and 205a are formed on the active layers 203a and 204a.
05b is formed, and an addition step of an element belonging to Group 15 of the periodic table (in this embodiment, phosphorus) is performed. The concentration of phosphorus to be added is 5 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 1
0 ^{19 to} 5 × 10 ¹⁹ atoms / cm ³ ). However, the concentration of phosphorus to be added varies depending on the temperature and time of the later gettering step and the area of the phosphorus-doped region, and is not limited to this concentration range. The region to which phosphorus is added in this manner (hereinafter, referred to as a phosphorus-doped region)
203b and 204b were formed.

The resist mask 205a is arranged so as to expose a part (or all) of a region which will later become a source region or a drain region of the driver TFT.
Similarly, the resist mask 205b is used to
The source region or the drain region of T is arranged so as to expose a part (or the whole). At this time, since a resist mask is not provided in a region serving as a lower electrode of the storage capacitor, phosphorus is entirely added, and
4b.

The resist masks 205a and 205b
It is preferable that the surface of the active layer is oxidized before the formation. By providing the silicon oxide film, the adhesion between the active layer and the resist mask can be improved, and the active layer can be prevented from being contaminated with an organic substance.

Next, the resist masks 205a and 205b
Is removed, and a heat treatment at 500 to 650 ° C. is applied for 2 to 16 hours to getter the catalyst element (nickel in this embodiment) used for crystallizing the silicon film. To achieve the gettering action, a temperature of about ± 50 ° C. from the highest temperature of the heat history is required, but the heat treatment for crystallization requires
Since the heat treatment is performed at 00 ° C., the gettering action can be sufficiently exerted by the heat treatment at 500 to 650 ° C.

In this embodiment, the heat treatment at 600 ° C. for 8 hours causes nickel to move in the direction of the arrow (shown in FIG.
It was gettered and captured by the phosphorus contained in b. Thus, the gettering region (phosphorus-doped region 203)
b, 204b) are formed. Thus, the concentration of nickel contained in the regions 203a and 204a is 2 × 10 ¹⁷ atoms / cm ³ or less (preferably 1 × 1 ¹⁷ atoms / cm ^3).
0 ¹⁶ atoms / cm ³ or less). The gettering region remains as the lower electrode of the storage capacitor, and remains as part or all of the source region or the drain region of the driver TFT and the pixel TFT. (Fig. 2 (C))

Next, a gate insulating film 206 is formed by a plasma CVD method or a sputtering method. (FIG. 2 (D))
The gate insulating film 206 functions as a gate insulating film of the pixel TFT, and has a thickness of 50 to 2
00 nm. In this embodiment, a silicon oxide film having a thickness of 100 nm is used.

In addition, not only a silicon oxide film but also a laminated structure in which a silicon nitride film is provided on a silicon oxide film, or a silicon oxynitride film in which nitrogen is added to a silicon oxide film may be used. .

After the gate insulating film 206 is formed, a resist mask (not shown) is provided and the gate insulating film is selectively removed. At this time, the gate insulating film 20 is formed on the pixel TFT.
6 is removed, and the region above the region that becomes the driver TFT and the storage capacitor is removed. Thus, the state shown in FIG. 2E is obtained.

Next, at 800 to 1150 ° C. (preferably 9 ° C.)
A heat treatment step of 15 minutes to 8 hours (preferably 30 minutes to 2 hours) at a temperature of (00 to 1100 ° C.) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, 95
A heat treatment step was performed at 0 ° C. for 30 minutes. In this heat treatment step, an effect of repairing defects and the like in the crystal grains of the active layer is obtained, so that a crystalline silicon film having extremely good crystallinity is formed.

The oxidizing atmosphere may be a dry oxygen atmosphere, a wet oxygen atmosphere, or an oxygen atmosphere containing a halogen element. When the thermal oxidation step is performed in an atmosphere containing a halogen element, the effect of removing nickel can be expected, which is effective.

By performing the thermal oxidation step in this manner, the surface of the semiconductor layer exposed in the region serving as the storage capacitor is:
A silicon oxide film (thermal oxide film) 207 of 5 to 50 nm (preferably 10 to 30 nm) is formed. (FIG. 3A) Finally, the silicon oxide film 207 functions as a dielectric of a storage capacitor, and the silicon oxide film 206 serves as a pixel TFT and a driver TF.
Functions as a T gate insulating film.

Although not shown for simplicity, the pixel T
A gate insulating film 206 made of a silicon oxide film remaining on the FT and the driver TFT, and semiconductor layers 203 and 20 thereunder.
The oxidation reaction proceeds also at the interface with No. 4. for that reason,
Finally, the thickness of the gate insulating film 206 of the pixel TFT is 50
To 200 nm (preferably 100 to 150 nm).

After the thermal oxidation step is completed, the gate wiring 209 (NTFT side) of the driver TFT is turned on.
10 (PTFT side), pixel TFT gate wiring 211,
An upper wiring (also referred to as an upper electrode) 212 of the storage capacitor is formed. Although the gate wiring 211 has two gate wirings because the pixel TFT has a double gate structure, it is actually the same wiring.

In this embodiment, the gate wirings 209 to 2
A stacked film of silicon film / tungsten nitride film / tungsten film from the lower layer (or silicon film / tungsten silicide film from the lower layer) was used as 11 and the upper wiring 212 of the storage capacitor. Of course, it is needless to say that other conductive films described in “Embodiments of the invention” can be used. In this embodiment, the thickness of each gate wiring is 25
It was set to 0 nm.

In this embodiment, the lowermost silicon film is formed by using a low pressure thermal CVD method. Since the insulating film in the region serving as the storage capacitor is as thin as 5 to 50 nm, a semiconductor layer (active layer) may be damaged depending on conditions when a sputtering method or a plasma CVD method is used. Therefore, a thermal CVD method capable of forming a film by a chemical vapor reaction is preferable. Note that it is preferable that an impurity imparting conductivity be added to the lowermost silicon film.

Next, a silicon nitride film 213 having a thickness of 25 nm is formed to cover the gate wirings 209 to 211 and the upper wiring 212 of the storage capacitor. The silicon nitride film 213 prevents oxidation of the gate wirings 209 to 211 and the upper wiring 212 of the storage capacitor, and at the same time functions as an etching stopper when removing a sidewall made of a silicon film.

At this time, it is effective to perform a plasma treatment using a gas containing hydrogen (ammonia gas in this embodiment) as a pretreatment for forming the silicon nitride film 213. Hydrogen activated (excited) by plasma is confined in the active layer (semiconductor layer) by this pretreatment, so that hydrogen termination is effectively performed.

Further, when nitrous oxide gas is added in addition to the gas containing hydrogen, the surface of the object to be treated is washed by the generated moisture, and it is possible to effectively prevent the contamination by boron and the like contained in the air. it can.

Thus, the state shown in FIG. 3B was obtained. next,
An amorphous silicon film (not shown) is formed, and anisotropic etching is performed with a chlorine-based gas to form sidewalls 214 to 21.
8 is formed. After the sidewalls 214 to 218 are formed, a process of adding an element belonging to Group 15 of the periodic table (phosphorus in this embodiment) to the semiconductor layers 203 and 204 is performed.
At this time, the gate wirings 209 to 211, the upper electrode 212 of the storage capacitor, and the side walls 214 to 218 were used as masks, and the impurity regions 219 to 223 were formed in a self-aligned manner. (FIG. 3C) The concentration of phosphorus added to the impurity regions 219 to 223 is 5 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm.
Adjust to ³

In the step of adding phosphorus, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used.
Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

In this embodiment, the impurity is added using the side wall, but the present invention is not particularly limited. A resist mask using a photomask may be used instead of the side wall.

When the state shown in FIG. 3C is obtained, the side walls 214 to 218 are removed, and the phosphorus adding step is performed again. In this step, the doping is performed at a lower dose than in the previous step of adding phosphorus. Thus, the sidewall 2
A low concentration impurity region is formed in a region where phosphorus is not added by using 14 to 218 as a mask. The concentration of phosphorus added to this low concentration impurity region is 5 × 10 ^{17 to} 5 × 1.
Adjust so as to be 0 ¹⁸ atoms / cm ³ . (FIG. 3 (D))

Further, similarly to the process shown in FIG.
In the step of adding phosphorus, an ion implantation method that performs mass separation may be used, or a plasma doping method that does not perform mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

In this process, a CMOS circuit N is formed.
A source region 224, an LDD region 225, and a channel forming region 226 of the TFT are defined. Further, the source region 227, the drain region 228, and the LDD region 229 of the pixel TFT are provided.
a, 229b and channel formation regions 230a, 230b are defined. Further, a lower electrode 231 of the storage capacitor is defined.

Also, a low concentration impurity region 232 is formed in a region to be a PTFT of a CMOS circuit, similarly to the NTFT.

Next, a region other than the region to be the PTFT of the CMOS circuit is covered with resist masks 233 and 234, and an element belonging to Group 13 of the periodic table (boron in this embodiment) is added. In this step, doping is performed at such a dose as to form an impurity region having a higher concentration than phosphorus already added.
Specifically, the adjustment is performed so that boron is added at a concentration of 1 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . As a result, PT
All the impurity regions exhibiting N-type conductivity formed in the region to be the FT become impurity regions exhibiting P-type conductivity because the conductivity types are inverted by boron. (FIG. 4 (A))

Of course, in the boron process, an ion implantation method for performing mass separation may be used, or a plasma doping method for not performing mass separation may be used. Further, the condition of the acceleration voltage and the dose amount may be set by the practitioner to the optimal values.

In this process, a CMOS circuit is formed.
A source region 235, a drain region 236, and a channel formation region 237 of the TFT are defined. Also, the drain region 238 of the NTFT of the CMOS circuit is defined.

Needless to say, the doping order is not limited to this embodiment. For example, after the step shown in FIG. 3B, phosphorus is added before the step of forming the sidewalls 214 to 218 to remove the low concentration impurity region. A forming step may be performed.
In addition, the step of adding phosphorus includes a region serving as a storage capacitor,
The operation may be performed separately for a region where a gate insulating film is to be a driver TFT and a region where a pixel TFT is to be formed.

After all the impurity regions have been formed, the resist masks 233 and 234 are removed. Then, the added impurities are activated by laser light or heat treatment. If only activation is performed, 300-70
Although about 2 hours at a temperature range of 0 ° C. is sufficient, here, a heat treatment step is performed at a temperature range of 750 to 1150 ° C. for 20 minutes to 12 hours. In this embodiment, the heat treatment at 950 ° C. for 2 hours was performed in an inert atmosphere. (FIG. 4
(B))

In this step, phosphorus or boron added to each impurity region is activated and, at the same time, nickel (catalytic element used at the time of crystallization) remaining in the channel formation region is converted to the source region and the nickel by the gettering action of phosphorus. It also serves as a step of re-gettering to the drain region. In addition, by performing the heat treatment in a temperature range of 750 to 1150 ° C., impurities flow under the gate wiring,
A structure called a highly reliable GOLD structure can also be formed.

The reason why the processing temperature is high is that unless the temperature of about ± 50 ° C. is added from the highest temperature in the heat history applied to the semiconductor layer from the crystallization step to the gettering step, the phosphorus gettering This is because the action does not work effectively. In the case of this embodiment, 950 is used for forming the gate insulating film.
Since the heat history passes through the heat history of 900C, a heat treatment at 900 to 1000C is effective.

In this step, nickel moves and is gettered and captured by phosphorus contained in the source region or the drain region. Thereby, the channel forming region 2
The concentration of nickel contained in 38 to 241 was 2 × 10 ¹⁷ at
oms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less). Therefore, the operation of the TFT is not affected at all.

[0087] On the contrary, the source region 243-245 and drain regions 246-248 concentrated ^{nickel, 1 × 10 19 atoms / cm} 3 or more (typically 3 × 10 ¹⁹
１1 × 10 ²¹ atoms / cm ³ ).

When the state shown in FIG. 4B is obtained,
A first interlayer insulating film 249 is formed. In this embodiment, a 1 μm thick silicon oxide film formed by a plasma CVD method was used. Then, after forming the contact holes, source wirings 250 to 252 and drain wirings 253 and 254 were formed. These wirings were formed of a laminated film in which a conductive film containing aluminum as a main component was sandwiched between titanium films.

At this time, the drain wiring 253 is used as a common wiring for NTFT and PTFT forming a CMOS circuit. In addition, since the source region and the drain region contain nickel at a high concentration as described above, good ohmic contact with the source wiring and the drain wiring can be realized.

After that, a passivation film 255 is formed. As the passivation film 255, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or a stacked film of these insulating films and a silicon oxide film can be used.
In this embodiment, a silicon nitride film having a thickness of 300 nm is used as a passivation film.

In this embodiment, as a pretreatment for forming a silicon nitride film, a plasma treatment using an ammonia gas is performed, and the passivation film 255 is formed as it is.
Hydrogen activated (excited) by plasma by this pretreatment is confined by the passivation film 255, so that hydrogen termination of the active layer (semiconductor layer) of the TFT can be promoted.

Further, when nitrous oxide gas is added in addition to the gas containing hydrogen, the surface of the object to be treated is washed by the generated moisture, and it is possible to effectively prevent the contamination by boron and the like contained in the air. it can.

After forming the passivation film 255,
An acrylic film having a thickness of 1 μm was formed as the second interlayer insulating film 256. Then, a titanium film was formed thereon to a thickness of 200 nm and patterning was performed to form a black mask 257.

Next, as the third interlayer insulating film 258, 1
A contact hole was formed by forming an acrylic film having a thickness of μm, and a pixel electrode 259 made of an ITO film was formed. Thus, an AM-LCD having a structure as shown in FIG. 4C is completed.

As described above, the present invention is characterized in that the step of adding impurities for reducing nickel also serves as the step of lowering the resistance of the lower electrode of the storage capacitor. With such a configuration, it is possible to increase the capacity of the storage capacitor without increasing the area.

According to the manufacturing process of this embodiment, the final active layer (semiconductor layer) of the TFT is formed of a crystalline silicon film having a unique crystal structure having continuity in a crystal lattice. The features will be described below.

The active layer formed according to the above-described manufacturing process is
Microscopically, it has a crystal structure in which a plurality of needle-shaped or rod-shaped crystals (hereinafter, abbreviated as rod-shaped crystals) are gathered and arranged.
This was easily confirmed by TEM (transmission electron microscopy) observation.

Further, electron diffraction and X-ray (X-ray)
By using diffraction, it was confirmed that the surface of the active layer (portion where a channel is formed) had a {110} plane as a main orientation plane although the crystal axis contained some deviation. As a result of the applicant's detailed observation of an electron beam diffraction photograph with a spot diameter of about 1.5 μm, diffraction spots corresponding to the {110} plane clearly appear, but each spot has a distribution on a concentric circle. confirmed.

Further, the present applicant has observed by HR-TEM (High Resolution Transmission Electron Microscopy) the grain boundaries formed by the contact of individual rod-shaped crystals, and found that there is continuity in the crystal lattice at the grain boundaries. It was confirmed. This was easily confirmed from the fact that the observed lattice fringes were continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

As a result of the applicant's detailed observation of the crystalline silicon film obtained by carrying out the present example using a TEM, it was found that most of the crystal grain boundaries (90% or more, typically 95% or more) were found. The corresponding grain boundary of {3}, that is, {211} twin grain boundary was found.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3.

In the crystalline silicon film of this embodiment, each lattice fringe of adjacent crystal grains at the crystal grain boundary is continuous at an angle of about 70.5 °, and therefore, this crystal grain boundary is {211}.
We arrived at the conclusion of twin boundaries.

When θ = 38.9 °, a corresponding grain boundary of Σ9 is obtained, but such other crystal grain boundaries also exist.

Such corresponding grain boundaries are formed only between crystal grains having the same plane orientation. That is, since the crystalline silicon film obtained by carrying out this embodiment has a plane orientation of approximately {110}, such a corresponding grain boundary can be formed over a wide range.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, a semiconductor thin film having such a crystal structure can be regarded as having substantially no crystal grain boundaries.

Further, it was confirmed by TEM observation that defects existing in the crystal grains were almost completely eliminated by the heat treatment step (which corresponds to the thermal oxidation step or the gettering step in this embodiment) at a high temperature of 700 to 1150 ° C. Has been confirmed. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, the spin density of the crystalline silicon film manufactured according to the manufacturing process of this embodiment is at least
5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³
Below). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

As described above, since the crystalline silicon film obtained by carrying out this embodiment has substantially no inside of the crystal grains and no crystal grain boundary, the single-crystal silicon film or the substantially single-crystal silicon Think of it as a membrane.

(Knowledge Regarding Electrical Characteristics of TFT) The TFT manufactured in this example exhibited electrical characteristics comparable to those of MOSFETs. The following data is obtained from a TFT (the active layer has a thickness of 30 nm and the gate insulating film has a thickness of 100 nm) prototyped by the present applicant.

(1) The sub-threshold coefficient which is an index of the switching performance (the agility of switching on / off operation) is 60 to 100 mV / decade (typically 60 to 85 mV) for both the N-channel TFT and the P-channel TFT. / decade)
And small. (2) The field effect mobility (μ _FE ) as an index of the operation speed of the TFT is 200 to 650 cm ² / Vs for the N-channel TFT.
(Typically 300-500cm ² / Vs), P-channel type TFT
In (typically ^{150~200cm 2 / Vs) 100~300cm 2 /} Vs greater the. (3) The threshold voltage (V
_th ) is as small as -0.5 to 1.5 V for an N-channel TFT and -1.5 to 0.5 V for a P-channel TFT.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

(Knowledge on Circuit Characteristics) Next, the frequency characteristics of a ring oscillator manufactured using the TFT formed by carrying out this embodiment will be described. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape, and is used to determine a delay time per one stage of the inverter circuit. The configuration of the ring oscillator used in the experiment is as follows. Number of steps: 9 steps Thickness of gate insulating film of TFT: 30 nm and 50 nm Gate length (channel length) of TFT: 0.6 μm

As a result of examining the oscillation frequency with this ring oscillator, it was possible to obtain an oscillation frequency of about 1 GHz as the maximum value. Further, a shift register, which is one of the TEGs of the LSI circuit, was actually manufactured, and the operating frequency was confirmed. As a result, the thickness of the gate insulating film was 30 nm, and the gate length was 0.6.
An output pulse with an operating frequency of 100 MHz was obtained in a shift register circuit having 50 μm, a power supply voltage of 5 V and 50 stages.

The surprising data of the ring oscillator and the shift register as described above is that the TFT of this embodiment is a MOS transistor.
Performance comparable to or superior to FET (electrical characteristics)
Has been shown.

[Embodiment 2] In the embodiment 1, in the step of selectively removing the gate insulating film 206, it is preferable that the removal in a region serving as a storage capacitor is performed as shown in FIG. In FIG. 5A, a dotted line A in the top view of the pixel portion
A cross section taken along the line -A 'corresponds to a cross-sectional view of the pixel portion in FIG. FIG. 5B is a simplified equivalent circuit diagram of FIG. The reference numerals used in FIGS. 5A and 5B are the same as those in FIGS. 5A, reference numeral 502 denotes an end of the gate insulating film 205, 211 denotes a gate wiring, 212 denotes an upper wiring of a storage capacitor, and 257 denotes a black mask.

As shown in FIG. 5A, in a portion 505 where the gate wiring goes over the semiconductor layer, it is desirable to leave the gate insulating film at the end of the semiconductor layer.

At the end of the semiconductor layer, a phenomenon called edge thinning occurs when a thermal oxidation step is performed later. this is,
This is a phenomenon in which an oxidation reaction proceeds so as to go under the edge of the semiconductor layer, and the edge becomes thinner and simultaneously rises upward. For this reason, when the edge thinning phenomenon occurs, there is a problem that the gate wiring is easily broken when the gate wiring gets over.

However, if the gate insulating film 206 is removed so as to have the structure as shown in FIG. 5A, the edge thinning phenomenon can be prevented in the portion 505 over which the gate wiring runs. Therefore, a problem such as disconnection of the gate wiring can be prevented beforehand.

[Embodiment 3] In this embodiment, an example in which an AM-LCD is manufactured by a process different from that of Embodiment 1 will be described with reference to FIGS.

First, a silicon oxide film (underlying film 602) and an amorphous silicon film (not shown) are continuously formed on a quartz substrate 601 according to the manufacturing process of the first embodiment.
After nickel was selected as a catalyst element and the amorphous silicon film was crystallized by using the technique described in Japanese Patent Publication No. 0, active layers 603 and 604 made of a crystalline silicon film were formed. (FIG. 6
(A)) FIG. 6A is the same as FIG. 2A of the first embodiment.

Next, a gate insulating film 606 is formed by a plasma CVD method or a sputtering method. The gate insulating film 606 is an insulating film that functions as a gate insulating film of the pixel TFT, and has a thickness of 50 to 200 nm.
In this embodiment, a silicon oxide film having a thickness of 100 nm is used. Also,
Not only a silicon oxide film but also a stacked structure in which a silicon nitride film is provided over a silicon oxide film may be used, or a silicon oxynitride film in which nitrogen is added to a silicon oxide film may be used.

After forming the gate insulating film 606, FIG.
As shown in (C), using a photomask on the active layer
To form resist masks 605a and 605b,
For adding an element belonging to group 15 of the present invention (phosphorus in this embodiment)
I do. Here, the through-dope
Let me The concentration of phosphorus to be added is 5 × 10¹⁸~ 1 × 1
0 ²⁰atoms / cm^Three(Preferably 1 × 10¹⁹~ 5 × 10¹⁹ato
ms / cm^ThreeIs preferred. However, the concentration of phosphorus to be added is
Temperature, time, and
Because this varies depending on the area of the
It is not specified. Area where phosphorus is added in this way
(Hereinafter referred to as phosphorus-doped regions) 603b and 604b
It is formed. (FIG. 6 (C))

Note that the resist masks 605a and 605b
It is preferable that the surface of the active layer is oxidized before the formation. By providing the silicon oxide film, the adhesion between the active layer and the resist mask can be improved, and the active layer can be prevented from being contaminated with an organic substance.

Next, the gate insulating film 606 is selectively removed using the resist masks 605a and 605b used for adding phosphorus as they are. Resist mask 60
5a is provided on the active layer of the driver TFT, and is arranged so as to expose a part (or all) of a region which will later become a source region or a drain region. Further, the resist mask 605b is arranged so as to expose a part (or the whole) of the source region or the drain region of the pixel TFT. At this time, a region serving as a storage capacitor is exposed.

Next, resist masks 605a, 605
After removing b, heat treatment at 500 to 650 ° C. is applied for 2 to 16 hours to perform gettering of the catalyst element (nickel in this embodiment) used for crystallization of the silicon film. As described in the first embodiment, a temperature of about ± 50 ° C. from the highest temperature of the heat history is required to achieve the gettering action, but the heat treatment for crystallization is performed at 550 to 600 ° C. For,
The gettering action can be sufficiently exhibited by the heat treatment at 500 to 650 ° C.

In this embodiment, heat treatment at 600 ° C. for 8 hours causes nickel to move in the direction of the arrow (shown in FIG. 6 (D)), and the phosphorus-doped regions 603b, 604
b. Thus, a gettering region is formed. This gettering region remains as the lower electrode of the storage capacitor and remains as part or all of the source region or drain region of the driver TFT and pixel TFT. (FIG. 6 (D))

Next, a heat treatment step at a temperature of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). . In this embodiment, 9
A heat treatment step was performed at 50 ° C. for 30 minutes. In this heat treatment step, an effect of repairing defects and the like in the crystal grains of the active layer is obtained, so that extremely good crystallinity is formed.

The oxidizing atmosphere may be a dry oxygen atmosphere, a wet oxygen atmosphere, or an oxygen atmosphere containing a halogen element. This thermal oxidation step in an atmosphere containing a halogen element is effective because an effect of removing nickel can be expected.

By performing the thermal oxidation process in this manner, a surface of the semiconductor layer exposed in the region that becomes the pixel TFT, the driver TFT, and the storage capacitor has a 5-50 nm (preferably 10-30 nm) silicon oxide film (thermal oxide film). ) 607 is formed. (FIG. 7A) Finally, the silicon oxide film 607
Functions as a dielectric of the storage capacitor, and the silicon oxide film 606 functions as a gate insulating film of the pixel TFT and the driver TFT.

Although not shown, an oxidation reaction also proceeds at the interface between the gate insulating film 606 made of a silicon oxide film remaining in the pixel TFT and the driver TFT, and the semiconductor layers 603 and 604 thereunder. Therefore, finally, the thickness of the gate insulating film 606 of the pixel TFT is 50 to 200 nm.
(Preferably 100 to 150 nm).

Since this step may follow the steps of the first embodiment, detailed description will be omitted.

After the thermal oxidation step is completed, the gate wirings 609 to 611, the upper wiring 612 of the storage capacitor, and the silicon nitride film 613 covering these wirings are formed in the same manner as in the first embodiment. (FIG. 7 (B))

Next, an amorphous silicon film is formed, anisotropic etching is performed to form sidewalls 614 to 618, and an element belonging to Group 15 of the periodic table (phosphorus in this embodiment).
Is added, and the impurity regions 619 to 619 are self-aligned.
623 are formed. (FIG. 7 (C))

Next, the sidewalls 614 to 618 are removed, and a phosphorus addition step is performed again to form low-concentration impurity regions 625, 632, 629a, and 629b. (FIG. 7 (D))

Next, the region other than the region to be the PTFT of the CMOS circuit is hidden by the resist masks 633 and 634, and a step of adding an element belonging to Group 13 of the periodic table (boron in this embodiment) is performed, so that impurities exhibiting P-type conductivity are obtained. Form an area.
(FIG. 8A)

As in the first embodiment, the doping order is not limited to this embodiment. For example, after the step shown in FIG. 7B, phosphorus is added before forming the side walls 614 to 618. May be performed to form a low-concentration impurity region. In addition, the step of adding phosphorus may be performed separately for a region to be a storage capacitor and a region to be a driver TFT and a pixel TFT having a thick gate insulating film.

After the formation of all the impurity regions, the resist masks 633 and 634 are removed, and phosphorus or boron added to each impurity region is subjected to a heat treatment (300
(700 ° C., several hours) or by laser light or the like. (FIG. 8 (B)) This activation is performed at 800 to 1150 ° C.
(Preferably 900 to 1100 ° C.) for 15 minutes to 8
A heat treatment process for a period of time (preferably 30 minutes to 2 hours) may be performed to diffuse an impurity below the gate wiring to form an impurity region as in the first embodiment.

When the state shown in FIG. 8B is obtained,
A first interlayer insulating film 649 is formed. Then, after forming contact holes, source wirings 650 to 652 and drain wirings 653 and 654 are formed.

Then, a passivation film 655 is formed. After forming the passivation film 655, an acrylic film having a thickness of 1 μm is formed as the second interlayer insulating film 656. Then, a titanium film is formed thereon to have a thickness of 200 nm and is patterned to form a black mask 657.

Next, as the third interlayer insulating film 658, 1
A contact hole is formed by forming an acrylic film having a thickness of μm, and a pixel electrode 659 made of an ITO film is formed. Thus, an AM-LCD having a structure as shown in FIG. 8C is completed.

The difference between the first embodiment and this embodiment is that the mask used in the step of adding phosphorus, which is performed for the gettering step, removes the insulating film in order to expose the lower electrode of the storage capacitor. The point is that it also serves as the used mask. In this way, the number of masks can be reduced.

The structure of this embodiment can be freely combined with any one of Embodiments 1 and 2.

[Embodiment 4] In the fabrication process of Embodiment 1 shown in FIG. 2C, after removing the resist masks 205a and 205b, before the heat treatment (gettering process), the gate insulating layer was previously formed by covering the active layer. A film (equivalent to the gate insulating film 206 in FIG. 2D) can be formed in advance.

That is, the gettering step is performed while the active layer is covered with the gate insulating film. After the gettering step is completed, the gate insulating film is patterned, and FIG.
The structure is similar to that of FIG.

The advantage of this embodiment is that the active layer is not exposed during the gettering step. When the active layer is exposed, phosphorus present in the phosphorus-doped region may diffuse in the atmosphere depending on conditions such as a processing temperature and a processing atmosphere, and may be added to a region to be a channel formation region later. However, such a problem does not occur if the semiconductor device is covered with the gate insulating film as in this embodiment.

The configuration of this embodiment can be freely combined with any of the first to third embodiments.

[Embodiment 5] In this embodiment, a TFT is formed on a substrate by the manufacturing process shown in Embodiment 1, and an AM-
A case where an LCD is manufactured will be described.

After the state shown in FIG. 4C is obtained, an alignment film is formed on the pixel electrode 259 to a thickness of 80 nm. Next, a color filter, a transparent electrode (counter electrode), and an alignment film are formed on a glass substrate as a counter substrate, and a rubbing process is performed on each alignment film to form a sealing material (sealing material). Then, the substrate on which the TFT is formed and the counter substrate are bonded to each other. Then, the liquid crystal is held in the meantime. Since a well-known means may be used for this cell assembling step, a detailed description is omitted.

Note that a spacer for maintaining the cell gap may be provided as needed. Therefore, when the cell gap can be maintained without the spacer as in the case of an AM-LCD having a diagonal of 1 inch or less, it is not necessary to particularly provide the cell gap.

Next, the AM-L manufactured as described above was used.
FIG. 9 shows the appearance of the CD. As shown in FIG. 9, an active matrix substrate and a counter substrate face each other, and a liquid crystal is sandwiched between these substrates. The active matrix substrate includes a pixel portion 901, a scan line driver circuit 902, and a signal line driver circuit 903 formed over a substrate 900.

The scanning line driver circuit 902 and the signal line driver circuit 903 are connected to the pixel portion 901 by a scanning line 930 and a signal line 940, respectively. These driver circuits 902 and 903 are mainly constituted by CMOS circuits.

A scanning line is formed for each row of the pixel portion 901, and a signal line 940 is formed for each column. Scan line 9
30 and a pixel TFT 91 near the intersection of the signal line 940.
0 is formed. The gate electrode of the pixel TFT 910 is connected to the scanning line 930, and the source is connected to the signal line 940. Further, a pixel electrode 960 and a storage capacitor 970 are connected to the drain.

The opposite substrate 980 has a transparent conductive film such as an ITO film formed on the entire surface of the substrate. The transparent conductive film is a pixel portion 90
The liquid crystal material is driven by an electric field formed between the pixel electrode and the counter electrode. The opposing substrate 980 has an alignment film as necessary,
A black mask and a color filter are formed.

The substrate on the active matrix substrate side has F
IC chip 93 using the surface on which PC 931 is mounted
2,933 are attached. These IC chips 932 and 933 are configured by forming circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate.

Further, in this embodiment, a liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device or an EC (electrochromics) display device as long as it is an active matrix type display device. It is also possible to apply the invention.

This embodiment can be freely combined with any of the first to fourth embodiments.

[Embodiment 6] In this embodiment, a case where another means is used for forming a crystalline silicon film in Embodiment 1 will be described.

Specifically, the crystallization of an amorphous silicon film is disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 (US Patent No. 08/32).
9, 644) is used. According to the technique described in the publication, a catalyst element (typically, nickel) that promotes crystallization is selectively retained on the surface of an amorphous silicon film, and crystallization is performed using the portion as a seed for nucleus growth. Technology.

According to this technique, a specific directionality can be given to crystal growth, so that a crystalline silicon film having extremely high crystallinity can be formed.

The structure of this embodiment can be freely combined with any of the structures of the first to fifth embodiments.

[Embodiment 7] The present invention relates to a conventional MOSFE.
It is also possible to form an interlayer insulating film on T and use it when forming a TFT thereon. That is, it is also possible to realize a semiconductor device having a three-dimensional structure in which a reflective AM-LCD is formed on a semiconductor circuit.

The semiconductor circuit is SIMOX, Sm
art-Cut (registered trademark of SOITEC), ELTRAN
(A registered trademark of Canon Inc.) may be formed on an SOI substrate.

In implementing this embodiment, any of the configurations of Embodiments 1 to 6 may be combined.

[Embodiment 8] In this embodiment, an example in which a source region and a drain region are formed by adding an element belonging to Group 13 of the periodic table or Group 15 of the periodic table in a different order from that of Embodiment 1 will be described. I do. In the doping sequence of Example 1,
First, a high-concentration phosphorus is added, second, a low-concentration phosphorus is added, and third, boron is added. In this embodiment, after the state shown in FIG. First, an example of adding boron will be described.

First, in accordance with the steps of Embodiment 1, FIG.
Get the state of.

Next, a resist mask covering a region other than the PTFT is formed. Then, a boron addition step is performed.
At this time, the concentration of boron to be added is 1 × 10 ^{20 to} 3 × 1.
0 ²¹ atoms / cm ³ . Thus, the source region, the drain region, and the channel formation region of the PTFT are defined.

Next, the resist mask was removed, and
A sidewall is formed in the same manner as described above. Then, a phosphorus addition step is performed. At this time, the concentration of phosphorus added is 5
× 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ .

Next, the side wall is removed, and the step of adding phosphorus is performed again. At this time, the added phosphorus concentration is 5 ×
It is 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ .

The following steps may follow the manufacturing steps of the first embodiment. The configuration of this embodiment can be freely combined with any one of Embodiments 1 to 8.

In this embodiment, prior to the step of forming the sidewall, a step of adding phosphorus to form an impurity region (the concentration of phosphorus is 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ) is performed. After the formation of the sidewall, phosphorus is added again to form an impurity region (the concentration of phosphorus is 5 × 10 ¹⁹ to 1 × 10
²¹ atoms / cm ³ ) may be formed.

When applied to Embodiment 3, doping may be performed in the same manner after obtaining the state of FIG. 7B.

[Embodiment 9] In this embodiment, an example in which a source region and a drain region are formed by adding an element belonging to Group 13 of the periodic table or Group 15 of the periodic table in a different order from that of Embodiment 1 will be described. I do. In the doping sequence of Example 1,
First, a high-concentration phosphorus is added, second, a low-concentration phosphorus is added, and third, boron is added. In this embodiment, after the state shown in FIG. , First add phosphorus,
Secondly, an example in which boron is added and thirdly, phosphorus is added again will be described.

First, in accordance with the steps of Embodiment 1, FIG.
Get the state of.

Next, a step of forming an impurity region (phosphorus concentration is 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ) by adding phosphorus is performed.

Next, a resist mask covering a region other than the PTFT is formed. Then, a boron addition step is performed.
At this time, the concentration of boron to be added is 1 × 10 ^{20 to} 3 × 1.
0 ²¹ atoms / cm ³ . Thus, the source region, the drain region, and the channel formation region of the PTFT are defined.

Next, the resist mask was removed, and Example 1 was repeated.
A sidewall is formed in the same manner as described above. Then, a phosphorus addition step is performed. At this time, the concentration of phosphorus added is 5
× 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ .

The following steps may follow the manufacturing steps of the first embodiment. The configuration of this embodiment can be freely combined with any of the first to seventh embodiments.

[Embodiment 10] In the manufacturing steps shown in Embodiments 1 and 3, the sidewall is used for forming the LDD region. However, the LDD region can be formed by patterning using a normal resist mask. It is.

The structure of this embodiment can be freely combined with any of the first to ninth embodiments.

In this case, the width (length) of the LDD region can be freely designed as compared with the case where the sidewall is used. Therefore, it can be said that this is an effective technique when the width of the LDD region is designed to be 0.1 μm or more.

[Embodiment 11] In this embodiment, an example in which the first interlayer insulating film is formed by a method different from that in Embodiment 1 will be described. FIG. 10 is used for the description.

First, the steps up to the step shown in FIG. 4B are completed according to the first embodiment. Next, a silicon nitride oxide film (A) 1701 having a thickness of 50 to 100 nm (70 nm in this embodiment) is used.
Is formed thereon, and a silicon nitride oxide film (B) 1702 having a thickness of 600 nm to 1 μm (80 nm in this embodiment) is formed thereon. Further, a resist mask is formed thereon. (Figure 1
0 (A))

Note that the silicon nitride oxide film (A) 1701 and the silicon nitride oxide film (B) 1702 have different composition ratios of nitrogen, oxygen, hydrogen, and silicon. The silicon nitride oxide film (A) 1701 contains 7% nitrogen, 59% oxygen, 2% hydrogen, and 32% silicon, and the silicon nitride oxide film (B) contains 3% nitrogen.
3%, oxygen 15%, hydrogen 23%, silicon 29%. Of course, it is not limited to this composition ratio.

Since the resist mask 1703 has a large thickness, the undulations on the surface of the silicon nitride oxide film (B) 1702 can be completely flattened.

Next, a resist mask 170 is formed by dry etching using a mixed gas of carbon tetrafluoride and oxygen.
3 and the silicon nitride oxide film (B) 1702 are etched. In the case of this embodiment, in dry etching using a mixed gas of carbon tetrafluoride and oxygen, the etching rates of the silicon nitride oxide film (B) 1702 and the resist mask 1703 are almost equal.

By this etching step, the resist mask 1703 is completely removed as shown in FIG.
Part of the silicon oxynitride film (B) 1702 (from the surface to a depth of 300 nm in this embodiment) is etched. As a result, the flatness of the surface of the resist mask 1703 is reflected on the flatness of the surface of the silicon nitride oxide film (B) etched as it is.

Thus, the first interlayer insulating film 1704 having extremely high flatness is obtained. In the case of the present embodiment, the first interlayer insulating film 1
The film thickness of 704 is 500 nm. Subsequent steps may refer to the preparation step of the first embodiment.

The structure of this embodiment is similar to that of the first to fifteenth embodiments.
Any embodiment can be freely combined.

[Embodiment 12] A CMOS circuit and a pixel portion formed by carrying out the present invention are not limited to various electro-optical devices (active matrix type liquid crystal display, active matrix type EL display, active matrix type E).
C display). That is, the invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIG. 11, FIG. 12, and FIG.

FIG. 11A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 11B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal control circuits.

FIG. 11C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 11D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 11E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 11F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 12A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 12B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 12D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 12C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 12D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 12, a case where a transmission type electro-optical device is used is shown, and examples of application to a reflection type electro-optical device and an EL display device are not shown.

FIG. 13A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.

FIG. 13B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 13C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 11.

Embodiment 13 In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 14A is a top view of an EL display device using the present invention. In FIG. 14A, 4010
Denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, 4013 denotes a gate side driver circuit,
Each driver circuit reaches the FPC 4017 via wirings 4014 to 4016 and is connected to an external device.

At this time, the cover member 6 is formed so as to surround at least the pixel portion, preferably the driver circuit and the pixel portion.
000, sealing material (also called housing material) 700
0, a sealing material (second sealing material) 7001 is provided.

FIG. 14B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
The FT may use a known structure (top gate structure or bottom gate structure).

The present invention is directed to a TFT 4022 for a driving circuit,
It can be used for the TFT 4023 for the pixel portion.

By using the present invention, the TFT 402 for the driving circuit
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

[0215] Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 4030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Furthermore, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0223] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can relieve the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light transmitting property.

The wiring 4016 is made of the sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 4.
Further, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic apparatus of Embodiment 12.

[Embodiment 14] In the liquid crystal display device of the present invention described in Embodiment 5, it is possible to use various liquid crystals other than the nematic liquid crystal. For example, 1998, SID, "Characte
ristics and Driving Scheme of Polymer-Stabilized M
onostable FLCD Exhibiting Fast ResponseTime and Hi
gh Contrast Ratio with Gray-Scale Capability "by
H. Furue et al., 1997, SID DIGEST, 841, "A Full-C
olor Thresholdless Antiferroelectric LCD Exhibitin
g Wide Viewing Angle with Fast Response Time "by
T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 6
71-673, "Thresholdless antiferroelectricity in liq
uid crystals and its application to displays "by
The liquid crystal disclosed in S. Inui et al. And US Pat. No. 5,594,569 can be used.

Ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 15 shows the electro-optical characteristics of a monostable FLC in which a cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage, and the cone edge substantially matches the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 15 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 15 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Tsuki, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 19, No. 19
See page 0 for details.

As shown in FIG. 15, it is understood that the use of such a ferroelectric mixed liquid crystal enables low-voltage driving and gradation display. A ferroelectric liquid crystal having such electro-optical characteristics can be used in the liquid crystal display device of the present invention.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low-voltage driving can be realized, so that low power consumption can be realized.

[0235]

According to the present invention, the AM-L
In manufacturing a pixel portion of a CD, a dielectric of a storage capacitor can be thinned without increasing the number of steps, and a storage capacitor having a large area and a large capacity can be formed. Therefore, even in an AM-LCD having a diagonal of 1 inch or less, it is possible to secure a sufficient storage capacity without lowering the aperture ratio.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of an AM-LCD.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 5 is a top view of a pixel portion and a diagram showing a circuit arrangement.

FIG. 6 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 7 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 8 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 9 is a diagram showing an appearance of an AM-LCD.

FIG. 10 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 11 illustrates an example of an electronic device.

FIG. 12 illustrates an example of an electronic device.

FIG. 13 illustrates an example of an electronic device.

FIG. 14 illustrates an EL display device.

FIG. 15 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 616L 617S (72) Inventor Kenji Fukunaga 398 Hase, Atsugi-shi, Kanagawa Pref. F-term (reference) 2H092 GA59 JA25 JA29 JA33 JA35 JA38 JA39 JA40 JA42 JA43 JA44 JA46 JB13 JB23 JB24 JB27 JB32 JB33 JB36 JB38 JB43 JB51 JB57 JB63 JB69 KA04 KA07 KA12 KA16 KA18 MA15 MA19 MA15 MA15 MA19 MA15 MA19 NA22 NA25 NA27 NA28 PA06 PA07 PA08 PA10 PA13 RA05 5F052 AA17 CA07 DA01 DB02 DB03 DB07 FA24 JA01 5F110 AA01 AA30 BB02 BB04 CC02 DD01 DD03 DD05 DD13 EE01 EE04 EE05 EE09 EE15 EE28 EE45 FF28 GG03 FF03 GG03 FF03 GG03 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 FF03 GG04 HJ04 HJ13 HJ18 HJ23 HL03 HL04 HL12 HM15 NN03 NN04 NN22 NN23 NN24 NN35 NN45 NN73 PP1 0 PP34 QQ09 QQ25 QQ28

Claims (22)

[Claims] A source region, a drain region, a channel forming region formed between the source region and the drain region on an insulating surface, and a gate insulating film formed at least on the channel forming region. And a wiring formed in contact with the gate insulating film, and a part of the source region and the drain region contains an element which promotes crystallization of silicon. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the wiring includes at least one layer mainly composed of one element selected from tantalum, molybdenum, tungsten, titanium, chromium, and silicon. 3. The device according to claim 1, wherein a part of the source region and the drain region has 1 × 10 ¹⁹ atoms.
Nickel, cobalt, palladium at a concentration of s / cm ³ or more,
A semiconductor device including an element selected from germanium, platinum, iron, and copper or a plurality of elements. 4. A semiconductor device having a driver circuit and a pixel portion formed on the same substrate, wherein a thickness of a dielectric of a storage capacitor included in the pixel portion is equal to a gate of a pixel TFT included in the pixel portion. A semiconductor device having a thickness smaller than a thickness of an insulating film. 5. The semiconductor device according to claim 4, wherein the dielectric of the storage capacitor included in the pixel portion is formed through at least a step of thermal oxidation. 6. The storage capacitor according to claim 4, wherein one of the electrodes of the storage capacitor is a semiconductor film, and the electrode has 1 ×
A semiconductor device comprising an element selected from nickel, cobalt, palladium, germanium, platinum, iron, and copper at a concentration of 10 ¹⁹ atoms / cm ³ or more. 7. The electrode according to claim 6, wherein the electrode has 5 × 10
A semiconductor device comprising an element belonging to Group 15 of the periodic table at a concentration of ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ . 8. The pixel TFT according to claim 4, wherein the gate insulating film of the pixel TFT has a thickness of 50 to 2 nm.
And the thickness of the dielectric of the storage capacitor is 5 to 5 nm.
A semiconductor device having a thickness of 0 nm. 9. The pixel TFT according to claim 4, wherein the pixel TFT comprises an active layer, an insulating film in contact with the active layer, and a wiring in contact with the insulating film. The layer has a channel forming region, and a source region and a drain region formed on both sides of the channel forming region, and a part of the source region and the drain region has 1 × 1
A semiconductor device comprising an element selected from nickel, cobalt, palladium, germanium, platinum, iron, and copper at a concentration of 0 ¹⁹ atoms / cm ³ or more. 10. A low-concentration impurity region according to claim 9, wherein at least one between said channel formation region and said source region or at least one between said channel formation region and said drain region is provided. A semiconductor device characterized by the above-mentioned. 11. The semiconductor device according to claim 1, wherein the semiconductor device is an active matrix type liquid crystal display, an active matrix type EL display, or an active matrix type EC display. apparatus. 12. A semiconductor device comprising the semiconductor device according to claim 1 as a display unit. 13. A semiconductor device according to claim 12, wherein the semiconductor device is a video camera, a digital camera, a projector,
A semiconductor device, which is a goggle-type display, a car navigation system, a personal computer, or a portable information terminal. 14. A method for manufacturing a semiconductor device having a driver circuit and a pixel portion on the same substrate, comprising: a first step of forming a semiconductor layer on a substrate using a catalytic element; A second step of selectively adding an element belonging to Group 15 of the periodic table of the periodic table, a third step of collecting the catalyst element in a region to which an element belonging to Group 15 of the periodic table is added by heat treatment, A fourth step of forming an insulating film on the semiconductor layer, a fifth step of removing a part of the insulating film and exposing a part of the active layer, and applying heat to a part of the exposed active layer. Sixth forming oxide film
A step of forming a wiring on the insulating film and the thermal oxide film; an eighth step of forming a sidewall on a side surface of the wiring; and the active layer using the wiring and the sidewall as a mask. A ninth step of adding an element belonging to Group 15 of the periodic table, a tenth step of removing the sidewalls,
An eleventh step of adding an element belonging to Group 5; a twelfth step of forming a resist mask on a region to be NTFT and adding an element belonging to Group 13 of the periodic table; and the periodic table added to the active layer. 13. A method for manufacturing a semiconductor device, comprising: performing a process of activating an element belonging to Group 13 and Group 15 of the periodic table. 15. The method according to claim 14, wherein the third step is 5
A method for manufacturing a semiconductor device, which is performed at a temperature of 00 to 650 ° C. 16. The concentration of an element belonging to Group 15 of the periodic table added in the eleventh step is higher than the concentration of an element belonging to Group 15 of the periodic table added in the ninth step. A method for manufacturing a semiconductor device, which is low. 17. A method for manufacturing a semiconductor device having a driver circuit and a pixel portion on the same substrate, comprising: a first step of forming a semiconductor layer on a substrate by using a catalytic element; A second step of forming an insulating film; a third step of selectively adding an element belonging to Group 15 of the periodic table to the semiconductor layer using a mask; and a part of the insulating film using the mask. A fourth step of removing the active layer and exposing a part of the active layer; a fifth step of collecting the catalytic element in a region to which an element belonging to Group 15 of the periodic table is added by heat treatment; The sixth step of forming a thermal oxide film on a part of the layer
A step of forming a wiring on the insulating film and the thermal oxide film; an eighth step of forming a sidewall on a side surface of the wiring; and the active layer using the wiring and the sidewall as a mask. A ninth step of adding an element belonging to Group 15 of the periodic table, a tenth step of removing the sidewalls,
An eleventh step of adding an element belonging to Group 5; a twelfth step of forming a resist mask on a region to be NTFT and adding an element belonging to Group 13 of the periodic table; and the periodic table added to the active layer. 13. A method for manufacturing a semiconductor device, comprising: performing a process of activating an element belonging to Group 13 and Group 15 of the periodic table. 18. The method according to claim 17, wherein the fifth step is 5
A method for manufacturing a semiconductor device, which is performed at a temperature of 00 to 650 ° C. 19. The method according to claim 14, wherein
The method of manufacturing a semiconductor device, wherein the sixth step is performed at a temperature of 800 to 1150 ° C. 20. The semiconductor device according to claim 14, wherein the catalyst element is an element selected from nickel, cobalt, palladium, germanium, platinum, iron, and copper. Method of manufacturing. 21. The method for manufacturing a semiconductor device according to claim 14, wherein a part of the active layer includes at least a region serving as a storage capacitor of the pixel portion. 22. The method according to claim 14, wherein
The method for manufacturing a semiconductor device, wherein the sidewall is formed of a semiconductor film.