JP2000269318A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor device capable of improving effective element characteristics or preventing exposure of a substrate surface in an element region, and a method for manufacturing the same. SOLUTION: A silicon oxide film 102 is formed on a surface of a semiconductor substrate 101, and a silicon nitride film 103 serving as a planarization stopper material for a buried oxide film is formed on the surface. After forming the trench 105 in the semiconductor substrate 101,
The side surface of the silicon oxide film 102 is etched and receded. The exposed surface of the semiconductor substrate 101 is oxidized to round the surface of the element region. Thereby, the effective dimension of the element region can be made larger than the actual dimension.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a device having a buried element isolation region and a method of manufacturing the same.

[0002]

2. Description of the Related Art SRAM (Static Random Access Memor)
In semiconductor memory devices such as y) and logic ICs, etc., an embedded element isolation region is formed by a method generally called shallow trench isolation (hereinafter, referred to as STI). STI is a technique of etching a surface portion of a semiconductor substrate to form a trench for element isolation, filling the trench with a silicon oxide film, and then performing chemical mechanical polishing (CMP).
This is an element isolation method in which an oxide film for element isolation is buried in a desired region by flattening by using such a method. Usually, a silicon nitride film is used as a stopper for flattening after forming the trench. 8A, 8B, 9A, and 9B show a conventional method of manufacturing a semiconductor device and the structure of the device.
This will be described with reference to FIG.

As shown in FIG. 8A, a silicon oxide film 302 having a thickness of about 150 Å is formed on a semiconductor substrate 301 by a thermal oxidation method. A silicon nitride film (or polycrystalline silicon film) 303 as a stopper material is formed on the surface thereof by CVD (Chemical Vapor Depos).
)), and deposited to a thickness of about 1500 Å. Further, a resist is applied on the surface, and a resist film 305 patterned by photolithography is formed.

As shown in FIG. 8B, anisotropic etching is performed using the resist film 305 as a mask to pattern the silicon nitride film 303 and the silicon oxide film 302. Further, anisotropic etching is performed on the surface of the semiconductor substrate 301 to form a trench 309 having a depth of about 4000 angstroms. After that, the resist film 305 is peeled off.

[0005] As shown in FIG. 8 (c), the inner wall of the trench 309 is oxidized by a thermal oxidation method to form a silicon oxide film 306 having a thickness of about 350 Å.

[0008] As shown in FIG. 8 D, a TEOS film 307 is deposited on the entire surface as a filling material for the trench 309.

[0007] Alternatively, as shown in FIG.
On the silicon nitride film 303 as a stopper material for planarization, a silicon oxide film 304 of about 1000 angstroms may be further formed as a trench forming mask. In this case, a resist film 305 is formed on the silicon oxide film 304, and the silicon oxide film 304 is patterned by performing anisotropic etching as shown in FIG. 9B.

[0009] As shown in FIG. 9 C, anisotropic etching is performed on the semiconductor substrate 301 using the silicon oxide film 304 as a mask to form a trench 309. After removing the resist film 305, the silicon oxide film 30 is formed on the inner wall of the trench 309 by thermal oxidation as shown in FIG.
6 is formed.

As shown in FIG. 9E, a TEOS film 307 is deposited on the entire surface as a filling material for the trench 309.

After the step shown in FIG. 8D or FIG. 9D, the TEOS film 307 is etched back or CM
P is performed, and a planarization process is performed until the surface of the silicon nitride film 303 is exposed. After the planarization, the silicon nitride film 303 is peeled off as shown in FIG. 10A, and the element isolation region 30 made of the TEOS film 307 embedded in the trench 309.
7 and an element region 311 are formed.

FIG. 10B is a perspective view of the longitudinal sectional view shown in FIG. 10A as viewed from obliquely above. This figure 1
As shown in FIG. 0B, an electrode material is deposited on the surface and patterned to form a wiring such as the gate electrode 308. Further, elements such as transistors are formed to complete a semiconductor device.

However, in the conventional device formed as described above, the surface of the element region 311 is flat. Therefore, the effective size when an element is formed in the element region 311 matches the actual size of the element region 311. For this reason, the performance of the element could not be increased beyond the actual dimensions. More specifically, when a transistor is formed in the element region 311, the W / L of the transistor becomes the element region 31.
However, it was determined by the actual size of No. 1 and the driving ability could not be increased. FIG. 1 shows a conventional semiconductor device.
Some were manufactured through the steps shown in FIG. As shown in FIG. 11A, a silicon oxide film 402, a silicon nitride film 403 as a stopper material for planarization, and a resist film 404 for forming a trench are formed on the surface of a semiconductor substrate 401.

As shown in FIG. 11B, anisotropic etching is performed using the resist film 404 as a mask.
The silicon nitride film 403 and the silicon oxide film 402 are patterned. A trench 408 is formed in the semiconductor substrate 401 using the silicon nitride film 403 as a mask.

As shown in FIG. 11C, the silicon oxide film 4
02 is subjected to wet etching in the lateral direction and receded.

As shown in FIG. 11D, the inner wall of the trench 408 of the semiconductor substrate 401 is oxidized by a thermal oxidation method to form a silicon oxide film 4 of about 350 Å.
05 is formed. Thus, the corner 409 of the element region is rounded.

As shown in FIG. 11E, TEOS
The film 406 is deposited so as to fill the trench 408 using the filling material.

As shown in FIG. 11F, a TEOS film 307 is formed.
Then, etching back or CMP is performed to planarize until the surface of the silicon nitride film 403 is exposed. After flattening
The silicon nitride film 403 is peeled off as shown in FIG. As a result, the element isolation region 410 and the element region 411
Are formed.

Here, the processing for rounding the corner 409 of the element region 411 is performed because the gate oxide film thereafter is not sufficiently formed on the corner if the corner is left sharp, and the film thickness is reduced. If the thickness of the gate oxide film is small, the breakdown voltage is reduced, and the off-leak current characteristics are deteriorated. In addition, there is a possibility that a transistor having a kink characteristic in which a threshold is generated in two steps at a lower voltage in addition to a preset voltage may be formed. Therefore, the corner 4 of the element region 411
09 is rounded to secure the thickness of the gate oxide film.

However, as shown in FIG.
If the silicon oxide film 402 on the surface of the element region 411 is removed and a gate oxide film is formed on this portion, the silicon oxide film is removed and oxidized. As a result, the upper surface and side surfaces of the silicon oxide film 406 filling the element isolation region 410 are removed by etching. Then, a portion 407 shown in the corner 409 of the element region 411 is illustrated.
As described above, the silicon oxide film 406 burying the element isolation region 410 falls below the corner 409 of the element region 411, and the surface of the semiconductor substrate 401 is exposed. This allows
The corner 409 of the element region 411 is covered with the silicon oxide film 406 for embedding and the gate oxide film thinner than the silicon oxide film 405, resulting in a decrease in breakdown voltage and an increase in off-leak current.

[0020]

As described above, the conventional semiconductor device has a problem that the surface of the element region has a flat shape and the effective element characteristics cannot be improved more than the actual dimensions. Alternatively, there is a problem that the silicon oxide film burying the element isolation region falls below the corners of the element region, and this portion is covered with a thin gate oxide film, which causes a decrease in breakdown voltage and an increase in off-leak current. .

In view of the above circumstances, the present invention provides a semiconductor device capable of forming an element having an effective dimension larger than the actual dimension of the element region, or preventing a reduction in breakdown voltage and an increase in off-leakage current. And a method for producing the same.

[0022]

According to the present invention, there is provided a semiconductor device comprising:
Forming first and second insulating films on the surface of the semiconductor substrate in order, patterning the first and second insulating films and the surface portion of the semiconductor substrate to form a trench, A step of etching the side surface of the insulating film to retreat a predetermined amount, a step of oxidizing an exposed surface of the semiconductor substrate to round the surface of the element region, and a step of filling the inside of the trench. Depositing the third insulating film, flattening the third insulating film using the second insulating film as a stopper material, removing the second insulating film, and removing the second insulating film from the surface of the element region. Removing the first insulating film, wherein the effective size of the element region is larger than the actual size.

Further, the method of manufacturing a semiconductor device according to the present invention
Forming a trench by forming first and second insulating films on a surface of a semiconductor substrate in order, patterning the first and second insulating films and a surface portion of the semiconductor substrate; The first side of the insulating film is etched to
A step of etching the corners of the element region of the semiconductor substrate to remove it by a second amount, and a step of oxidizing the exposed surface of the semiconductor substrate to remove the surface of the element region. Rounding off, depositing a third insulating film so as to fill the inside of the trench, flattening the third insulating film using the second insulating film as a stopper material, and forming the second insulating film. The method includes a step of removing a film and a step of removing the first insulating film on a surface of the element region, wherein an effective dimension of the element region is larger than an actual dimension.

Further, in the method of manufacturing a semiconductor device according to the present invention, first and second insulating films are sequentially formed on a surface of a semiconductor substrate, and the first and second insulating films and a surface portion of the semiconductor substrate are formed. Forming a trench by patterning the first and second insulating films, etching the side surfaces of the first and second insulating films so as to recede by a first amount, and oxidizing the exposed surface of the semiconductor substrate. To round the corners of the element region, etch the side surfaces of the first and second insulating films to further recede by a second amount, and perform a third process to fill the trench. Depositing an insulating film, planarizing the third insulating film using the second insulating film as a stopper material, removing the second insulating film, and removing the second insulating film from the surface of the element region. Removing the first insulating film. The more corners of the device region first and third insulating films is characterized in that it does not retract.

In a semiconductor device according to the present invention, an element region and an element isolation region are provided, a semiconductor substrate having a trench formed in the element isolation region, an oxide film formed on an inner wall of the trench, and an inside of the trench. An insulating film formed so as to be buried, wherein the surface of the element region is rounded by an oxidation step for forming the oxide film on the inner wall of the trench, and the effective size of the element region is larger than the actual size. It is characterized by being large.

Further, the semiconductor device of the present invention has an element region and an element isolation region, and a semiconductor substrate having a trench formed in the element isolation region; an oxide film formed on an inner wall of the trench; An insulating film formed so as to bury the inside thereof, wherein a corner of the element region is rounded by an oxidation step for forming the oxide film on the inner wall of the trench, and a corner of the element region is further rounded. Further, the insulating film and the oxide film are not receded.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

The structure of the semiconductor device according to the first embodiment of the present invention and the method of manufacturing the same will be described with reference to FIGS.

As shown in FIG. 1A, a silicon oxide film 102 is formed on a semiconductor substrate 101 to a thickness of about 150 angstroms by a thermal oxidation method. On the surface thereof, a silicon nitride film (or polycrystalline silicon film) 103 is deposited as a stopper material to a thickness of about 1500 angstroms by a CVD method. A resist film 106 serving as a mask material for forming a trench is formed on the surface.

Anisotropic etching is performed using the resist film 106 as a mask, and the silicon nitride film 103 and the silicon oxide film 102 are patterned. Further, anisotropic etching is performed on the surface portion of the semiconductor
A trench 105 having a depth of 0 Å is formed. After that, the resist film 106 is peeled off.

As shown in FIG. 1B, the silicon oxide film 10
2 is subjected to wet etching in the lateral direction and receded. This etching amount needs to be set so large that not only the corner of the element region but also the entire surface is rounded within a range where the silicon oxide film 102 is not completely removed.

As shown in FIG. 1C, the inner wall of the trench 105 of the semiconductor substrate 101 is oxidized by a thermal oxidation method to form a silicon oxide film 10 of about 350 angstroms.
8 is formed. As a result, the entire surface of the element region 111 is rounded as illustrated.

As shown in FIG. 1D, a silicon oxide film (or TEOS film) 107 is deposited so as to fill the trench 105 by a CVD method.

Alternatively, as shown in FIG.
On the surface of the silicon nitride film 103 serving as a stopper material, a silicon oxide film 10 serving as a mask material for forming a trench is formed.
4 may be formed. In this case, the silicon oxide film 104 is etched using a resist film (not shown). Using the silicon oxide film 104 as a mask, the semiconductor substrate 101 is anisotropically etched to form a trench 105.
To form

The subsequent steps are shown in FIGS. 1 (b) to 1 (d).
Is the same as the process shown in FIG. As shown in FIG. 2B, the silicon oxide film 102 is laterally wet-etched and receded.

As shown in FIG. 2C, the inner wall of the trench 105 of the semiconductor substrate 101 is oxidized by a thermal oxidation method to form a silicon oxide film 10 of about 350 Å.
8 is formed. As a result, the entire surface of the element region 111 is rounded as illustrated.

As shown in FIG. 2D, a silicon oxide film (or TEOS film) 107 is deposited so as to fill the trench 105 by a CVD method.

As a step after that shown in FIG. 1D or FIG. 2D, the silicon oxide film 107 is etched back or CMP to flatten it until the surface of the silicon nitride film 103 is exposed. After the planarization, the silicon nitride film 103 is peeled off as shown in FIG. T as embedding material
For those having low heat resistance, such as when an EOS film is used, it is desirable to perform densification for increasing the density by annealing.

Further, the silicon oxide film 102 on the surface of the element region 111 is removed by wet etching. Thereby, a structure in which the element region 111 is separated by the trench is obtained. In this case, the etching amount is desirably set to a necessary and sufficient value within a range in which a desired element isolation withstand voltage can be secured.

Thereafter, an element is formed by injecting impurities into the element region and the like, and the device is completed through a step of forming electrode wiring and the like.

According to the present embodiment, the surface of the element region is rounded as shown in FIG. Therefore, when an element is formed in the element region, the effective dimension can be made larger than the actual dimension. More specifically, the cross-sectional area of the channel region of the transistor is increased, so that the transistor size W can be further increased.

Here, the following steps can be added so that the surface of the element region can be more rounded. At the stage shown in FIG. 1B or FIG. 2B, the semiconductor substrate 10 at the corner 112 of the element region is
1 is isotropically etched to remove an appropriate amount as shown in FIG. 4 or FIG. Subsequent steps are the same as those in FIG. 1C or FIG. By adding this step, the surface of the element region 111 can be more rounded, so that the effective dimension of the element can be further increased.

Next, a configuration of a semiconductor device according to a second embodiment of the present invention and a method of manufacturing the same will be described with reference to FIG.

As shown in FIG. 6A, a silicon oxide film 202, a silicon nitride film 203 as a planarization stopper material, and a resist film 204 as a trench forming mask material are formed on the surface of a semiconductor substrate 201. I do. Anisotropic etching is performed using the resist film 204 as a mask to pattern the silicon nitride film 203 and the silicon oxide film 202. Furthermore, anisotropic etching is performed on the semiconductor substrate 201 to form a trench 209.

As shown in FIG. 2B, the side surfaces of the silicon nitride film 203 and the silicon oxide film 204 are wet-etched using, for example, hot phosphoric acid, and are retreated by, for example, 200 angstroms.

As shown in FIG. 2C, the inner wall of the trench 209 of the semiconductor substrate 201 is oxidized by a thermal oxidation method, and the silicon oxide film 20 of about 350 Å is formed.
5 is formed. As a result, the corners 210 of the element region are rounded. Here, it should be noted that if the oxidation amount is too large, the element region becomes narrow as described later. To avoid excessive oxidation,
For example, it is conceivable to remove a small amount of the semiconductor substrate 201 at a corner of the element region before performing thermal oxidation.

As shown in FIG. 2D, wet etching is again performed on the side surfaces of the silicon nitride film 203 and the silicon oxide film 204, and the side surfaces are retracted. This etching is performed to facilitate the subsequent filling in the trench 209 and to prevent the silicon oxide film buried in the subsequent step from being receded from the corner of the element region in the etching step. Then, the TEOS film 206
Is deposited so as to fill the trench 209 using the filling material.

As shown in FIG. 2E, etch back or CMP is performed on the TEOS film 206, and planarization is performed until the surface of the silicon nitride film 203 as a stopper material is exposed. After the planarization, the silicon nitride film 2
03 is peeled off. As a result, an element isolation region 210 and an element region 211 are formed.

As shown in FIG. 2F, the element region 2
The silicon oxide film 202 on the surface of No. 11 is removed. By this processing, the silicon oxide film 206 buried in the element isolation region 210 is removed, and the silicon oxide film 206 is retracted as shown.

As shown in FIG. 2G, the gate oxide film 20 is formed on the surface of the element isolation region 207 by using a thermal oxidation method.
7 is formed. Furthermore, electrode material is deposited on the entire surface,
The gate electrode wiring 208 is formed by patterning.

Conventionally, as shown in FIG.
In the step of removing the silicon oxide film 402 on the element region 411, the silicon oxide film 406 embedded in the element isolation region 410 recedes from the corner 409 of the element region 411,
The surface of the semiconductor substrate 411 was exposed at the corner 409. As a result, the corner 409 of the element region 411 is covered with the gate oxide film having a smaller thickness than the buried silicon oxide film 406, which causes a decrease in breakdown voltage and an increase in off-leak current.

On the other hand, according to the present embodiment, FIG.
In the step of removing the silicon oxide film 202 on the element region 211 as shown in (f), the silicon oxide film 206 embedded in the element isolation region 210 does not recede, and the corners of the element region 211 are exposed. Is prevented. This is shown in FIG.
6D, the corners of the element region 211 are rounded, and the side surfaces of the silicon nitride film 203 and the silicon oxide film 204 are further receded in the step of FIG. This is because the film 206 is embedded. As a result, the corners of the element region 211 are covered with the thick silicon oxide film 206 for embedding.
A decrease in breakdown voltage and an increase in off-leak current can be prevented.

Here, as described above, if the etching amount for removing the side surfaces of the silicon nitride film 203 and the silicon oxide film 204 in the step of FIG. 6B is too large, the following problem occurs.

As shown in FIG. 7A, after forming a trench 229 in the surface portion of the semiconductor substrate 221, the side surfaces of the silicon oxide film 222, the silicon nitride film 223, and the resist film 224 are recessed by etching. . If the retreat amount is too large, as shown in FIG.
When the silicon oxide film 225 is formed in the thermal oxidation process,
The corner 230 of the semiconductor substrate 221 is largely rounded.

As shown in FIG. 7C, the trench 229 is buried with the silicon oxide film 226 and is planarized until the surface of the silicon nitride film 223 is exposed.

As shown in FIG. 7D, the silicon nitride film 223 is formed.
Is removed, and the silicon oxide film 222 on the surface of the element region 231 is further removed. 7A, the silicon oxide films 225 and 226 remain at the peripheral portion of the element region 231 as shown in a portion 233 because the amount of retreat of the silicon nitride film 222 in FIG.

Thereafter, as shown in FIG.
1, a gate oxide film 227 is formed, and a gate electrode wiring 228 is formed on the surface.

Here, as shown in FIG. 7E, the silicon oxide films 225 and 2
26 are present. Therefore, the width 4a of the element region 231 is smaller than the original width 4b, and the effective element area decreases.

In order to avoid such a situation, in the step shown in FIG. 6B in the second embodiment, the amount of retreat of the side surface of the silicon nitride film 203 is not excessively large. It is necessary to set the etching amount.

The above embodiment is an example and does not limit the present invention. For example, the materials shown as the trench forming mask material, the planarization stopper material, and the trench filling material in the first and second embodiments are merely examples, and other materials may be used. Further, the method of forming the film, the thickness of the film, and the like may be different from those in the above-described embodiment as necessary.

[0061]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, of the first and second insulating films formed on the surface of the semiconductor substrate, the first insulating film is formed after the trench is formed. By retreating the side surface of the film and oxidizing the substrate surface to round the surface of the element region, it is possible to make the effective size of the element larger than the actual size.

Further, according to the semiconductor device and the method of manufacturing the same of the present invention, after the side surfaces of the first and second insulating films are receded and oxidized, the corners of the element region are rounded, and 1. By recessing the side surface of the second insulating film and filling the trench, the insulating film filling the element isolation region falls below the corner of the element region, exposing the corner surface of the element region and burying oxidation. Since it is possible to prevent the gate oxide film having a smaller thickness than the film from being covered, it is possible to improve the breakdown voltage and reduce the off-leak current.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention and a method of manufacturing the same in each step.

FIG. 2 is a longitudinal sectional view showing the configuration of the semiconductor device according to the first embodiment and a method of manufacturing the same in each step.

FIG. 3 is a vertical sectional view showing the configuration of the semiconductor device according to the first embodiment and a method for manufacturing the same according to steps;

FIG. 4 is a longitudinal sectional view showing a step of removing a corner of the element region by etching in the method of manufacturing the semiconductor device according to the first embodiment.

FIG. 5 is a longitudinal sectional view showing a step of removing a corner of the element region by etching in the method of manufacturing the semiconductor device according to the first embodiment.

FIG. 6 is a longitudinal sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention and a method of manufacturing the same in each step.

FIG. 7 is a longitudinal sectional view showing a problem in the case where the amount of recession of the silicon nitride film is too large in the same embodiment for each process.

FIG. 8 is a longitudinal sectional view showing a configuration of a conventional semiconductor device and a method of manufacturing the same in each step.

FIG. 9 is a longitudinal sectional view showing the configuration of another conventional semiconductor device and a method of manufacturing the same for each process.

FIG. 10 is a longitudinal sectional view showing a subsequent step of the method of manufacturing the conventional semiconductor device shown in FIGS. 8 and 9;

FIG. 11 is a longitudinal sectional view showing a configuration of still another conventional semiconductor device and a method of manufacturing the same for each process.

[Explanation of symbols]

101, 201, 221 Semiconductor substrate 102, 104, 107, 108, 202, 205, 2
06, 222, 225, 227, 230, 231 Silicon oxide film 103, 203, 223 Silicon nitride film 204, 224 Resist film 105, 209, 229 Trench 207 Gate oxide film 208, 228 Gate electrode wiring 210 Element isolation region 111, 211 Element area 112, 210, 230 Corner

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA35 AA36 AA45 BA05 DA24 DA27 DA53 5F083 GA06 GA30 NA01 PR05 PR12 PR21

Claims (5)

[Claims] A first insulating film is formed on a surface of a semiconductor substrate in order, and a trench is formed by patterning the first and second insulating films and a surface portion of the semiconductor substrate. A step of etching the side surface of the first insulating film to recede by a predetermined amount; a step of oxidizing an exposed surface of the semiconductor substrate to round the surface of the element region; Depositing a third insulating film so as to fill the gap, flattening the third insulating film using the second insulating film as a stopper material, removing the second insulating film, Removing the first insulating film on the surface of the region, wherein the effective size of the element region is larger than the actual size. 2. A first and a second insulating film are sequentially formed on a surface of a semiconductor substrate, and a pattern is formed on the first and the second insulating film and a surface portion of the semiconductor substrate to form a trench. A step of performing etching on a side surface of the first insulating film to retreat by a first amount, and a step of performing etching on a corner of an element region of the semiconductor substrate and removing the second amount by a second amount; A step of oxidizing the exposed surface of the semiconductor substrate to round the surface of the element region, depositing a third insulating film so as to fill the trench, and using the second insulating film as a stopper material A step of flattening the third insulating film; a step of removing the second insulating film; and a step of removing the first insulating film on a surface of the element region. Note that the effective dimensions are larger than the actual dimensions. A method for manufacturing a semiconductor device. 3. A trench is formed by sequentially forming first and second insulating films on a surface of a semiconductor substrate, and patterning the first and second insulating films and a surface portion of the semiconductor substrate. A step of etching the side surfaces of the first and second insulating films to recede by a first amount; and oxidizing an exposed surface of the semiconductor substrate to form a rounded corner at the element region. A step of performing etching on the side surfaces of the first and second insulating films to further recede by a second amount; depositing a third insulating film so as to fill the inside of the trench; Flattening the third insulating film by using the insulating film as a stopper material, removing the second insulating film, and removing the first insulating film on the surface of the element region. And the first region from the corner of the element region. And a method of manufacturing a semiconductor device, wherein the third insulating film does not recede. 4. A semiconductor substrate provided with an element region and an element isolation region, a trench formed in the element isolation region, an oxide film formed on an inner wall of the trench, and formed to fill the inside of the trench. Wherein the surface of the element region is rounded by an oxidation process for forming the oxide film on the inner wall of the trench, and the effective size of the element region is larger than the actual size. Semiconductor device. 5. A semiconductor substrate provided with an element region and an element isolation region, a trench formed in the element isolation region, an oxide film formed on an inner wall of the trench, and formed to fill the inside of the trench. Wherein the corners of the element region are rounded by an oxidation process for forming the oxide film on the inner wall of the trench, and the insulating film and the A semiconductor device, wherein the oxide film is not receded.