JP2000267885A - Computer-readable recording medium recording breakpoint setting method and breakpoint setting program - Google Patents

Abstract

(57) [Summary] [Problem] RO can be performed without adding dedicated hardware
A breakpoint is set for the program stored in the ROM without rewriting M. SOLUTION: A block including an address at which a breakpoint is to be set is copied from a ROM 30 to a RAM 32 via a monitor RAM 36, a break execution instruction is written on the RAM 32, a break instruction is executed, and the break instruction is taken into the cache 20. , The ROM 30 and the like are returned to the original state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for setting a breakpoint without rewriting a program stored in a ROM and a computer-readable recording medium recording such a breakpoint setting program.

[0002]

2. Description of the Related Art Conventionally, setting of a breakpoint is performed by using a rewritable memory, that is, a RAM (random access memory).
ory) memory, which can be realized only for the instruction code in the area and cannot be normally rewritten, that is, ROM
nly memory).

Recently, systems equipped with electrically rewritable memories, ie, flash ROMs, in units of blocks have been increasing, and there are many cases where a user program is directly written and operated on the mounted flash ROM. In such a case, a breakpoint can be realized at a desired address by rewriting the contents of the flash ROM.

Further, the entire area where a breakpoint is to be set is allocated to a RAM area by setting of a memory controller, and the contents of a program are copied to that area,
A method equivalent to that of M was also used.

[0005]

However, if a breakpoint is realized by rewriting the contents of the flash ROM, it takes time to set. Also, Flash R
OM has a finite number of times of writing. For this reason, it has been practically impossible to set a breakpoint on such a program by rewriting the contents of the debug target program and the like stored in the flash ROM and perform debugging.

In addition, the entire area in which a breakpoint is to be set is allocated to a RAM area by setting of a memory controller, and the contents of a program are copied to that area.
When using a method similar to M, when setting a plurality of breakpoints, the size of the RAM area is limited.
There has been a problem that the AM and the memory controller are exclusively used to realize a breakpoint.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide a breakpoint setting method for enabling a software break in a program in a ROM area, and a method for setting such a breakpoint. An object of the present invention is to provide a computer-readable recording medium on which a program is recorded.

[0008]

In order to achieve the above object, a method for setting a breakpoint according to the present invention comprises the steps of: (1) assigning an address of a ROM area of a block including an address at which a breakpoint is to be set in a program to a RAM area; Assigning, address assignment changing step, (2) the RA
Writing the block of the program stored in the ROM area to the M area; and writing the block of the program stored in the ROM area to the RAM area;
An instruction code rewriting step of rewriting the instruction code for setting a breakpoint; (4) a step of writing the instruction code in a cache memory by executing the instruction code for setting a breakpoint; ROM area and RA
Return the change of the address assignment with the M area to the original state,
Address assignment change release step.

A part of the program stored in the ROM is transferred to the RAM, and an instruction code at a desired address in the part is replaced with an instruction code for setting a breakpoint (hereinafter referred to as an instruction code).
"Break code". ), Execute this break code, and write it to the cache memory. Normally, the instruction code stored in the cache memory is the same as the instruction code stored in the address on the ROM corresponding to the address specified by the index, tag, or the like of the cache memory. However, in the present invention, the instruction code stored in the cache memory is different from the instruction code on the ROM stored at an address specified by an index, a tag, or the like. That is, a break code is stored in the cache memory, but an instruction code originally written in the debug target program is stored in the corresponding address on the ROM.

In this way, it is possible to set a breakpoint at a desired address in the ROM area without rewriting the contents of the ROM.

Further, in the break point setting method of the present invention, (1) in the RAM writing step, the data in the RAM area is saved before writing to the RAM area, and (2) the address allocation change release. In the step, it is preferable that the save data is returned to an original address of the RAM area after the change is released.

By temporarily saving the data in the RAM area and returning the saved data to the original address after the assignment change is released, the RAM area can be used by a target program or the like. That is, a part of the RAM area is temporarily used for setting a breakpoint. After the breakpoint is set, even if the target program or the like is being executed (before the break), the RAM area is used for executing the break code. Is not required. That is, a dedicated RAM is not required for setting a breakpoint and for executing a break.

Further, in the breakpoint setting method of the present invention, it is preferable that the cache memory is provided with a lock function, and after the breakcode is stored in the cache memory, the index in which the breakcode is stored is locked. The lock function refers to a function of preventing the contents of a locked index from being rewritten by an instruction code of another address having the same index but a different tag. If the cache memory is not locked, the contents of the cache memory may be rewritten by an instruction code of another address having the same index but a different tag.

However, by using the lock function of the cache memory, it is possible to prevent the block in which the breakpoint is set from being replaced from the cache memory.

The recording medium according to the present invention further comprises: an address assignment changing step of assigning an address of a ROM area of a block including an address at which a breakpoint is desired to be set in the program to the RAM area; Writing the block of the program stored in the area, a RAM writing step;
By executing the instruction code rewriting step of rewriting an instruction code at a desired address in the block of the program written in the RAM area into a breakpoint setting instruction code, and executing the breakpoint setting instruction code, Executing an instruction code in a cache memory, a cache memory writing step, and restoring an address assignment change between the ROM area and the RAM area to an original state, and an address assignment change canceling step. A program for recording a software break is recorded.

According to such a recording medium, storage and execution of a useful program that enables a breakpoint to be easily set in the ROM area without rewriting the ROM,
Transportation and the like can be performed easily, and breakpoints can be set more easily.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below. FIG. 1 shows a configuration of a ROM, a RAM, and the like used in the present embodiment. 10 is a CPU (Central Processing Unit) 20 is an instruction cache, 30 is RO
M and 32 are RAMs, 34 is a monitor ROM, 36 is a monitor RAM, 40a and b are memory controllers, 50 is an address bus, and 52 is a data bus.

The ROM 30 stores a program to be debugged (target program). RAM3
2 is used by the target program. Monitor RO
M34 stores a program (monitor program) for realizing the debugging function. The monitor RAM 36 is used by the monitor program in principle, but is used to temporarily store a part of the target program. The memory controller 40a makes the CS (chip select) signal of the ROM 30 valid. Memory controller 40b
Makes the CS signal of the RAM 32 valid.

The address width of the CPU 10 is k bits, and the data width is w bits. The capacity of the ROM 30 is 2
ⁿ words, and the capacity of the RAM 32 is 2 ^m words.
The instruction cache 20 has one block composed of ^2b words and ²ⁱ blocks. Each block has an address tag having a width of t bits, a V bit (valid bit) indicating that the content is valid, and an L bit (lock bit) indicating that the content is locked.

If the instruction code at the designated address is stored in the instruction cache 20, the CPU 10 fetches the instruction code from the instruction cache 20 and executes it. When the bkp instruction stored at the address (breakpoint) where execution is to be stopped is executed, the execution of the target program is interrupted and the execution of the monitor program is started.

The ROM 30 uses the lower n bits of the CS signal, the read signal and the address line, and outputs the data of the address specified by the lower n bits to the data bus 52 when the CS signal is valid and the read signal is valid. I do.

The RAM 32 uses the lower m bits of the CS signal, the read signal, the write signal, and the address line,
When the signal is valid and the read signal is valid, the data at the address specified by the lower m bits is output to the data bus 52. On the other hand, when the CS signal is valid and the write signal is valid, the contents of the data bus 52 are written to the address specified by the lower m bits.

When the CPU 10 executes the monitor program, the instruction cache 20 is always invalidated.

Generally, an address is divided into a tag (upper part) and an index (lower part). Based on the index of the address, the corresponding block of the cache 20 is selected. Then, the tag of the address is compared with the tag of the cache 20 to determine a cache hit or miss.

If the tag of the address and the tag of the cache 20 are equal and the V bit is set to ON, the reference request becomes a cache hit, and the corresponding word is passed to the CPU 10. Otherwise, the reference request will be missed.

In the present embodiment, the (b + i-1) bits from the b bits which are a part of the instruction address become the index address, and the (kt) bits to the (k-1) bits.
The bit becomes the tag address.

If the tag in the cache 20 does not match the tag in the instruction address or if the V bit is off, a cache miss occurs and the ROM 30 or RA
The instruction code is read from M32. The read instruction code is passed to the CPU 10 and stored in the cache 20, and at the same time, the V bit is turned on.

The memory controllers 40a and 40b
An address area of the OM 30 or the RAM 32 is designated, and it is determined which area of the ROM 30 or the RAM 32 the input address belongs to.
Enable the S signal. The designation of the address area is performed by writing the designated address from the data bus 52 to the registers of both memory controllers 40a and 40b.

Next, referring to FIG. 2 and FIG.
The procedure of copying an instruction code from 0 to the cache 20 via the monitor RAM 36 and the RAM 32 will be described by taking as an example a case where a breakpoint is set at address 121h of the target program. All addresses are 16
Notation in base.

In this example, the width of the address tag is 8
And the instruction cache 20 has 2 blocks for one block.
It is composed of ² (= 4) words, has 2 ² (= 4) blocks, and has a capacity of 2 ⁵ (= 32) words, ROM
The capacity of 30 is 2 ⁹ (= 512) words.

First, a block starting from address 120h on the ROM 30 (addresses from 120h to 123h) is stored in the save area in the monitor RAM 36 (step S).
1).

Next, addresses 120h to 123h are:
The memory controller 40 is set to the area of the RAM 32.
The address register b is set (step S2).

Further, the contents of addresses 120h to 123h on the RAM 32 and the contents of the monitor RAM 3
6 is exchanged with the contents stored in the save area (step S
3).

As a result, the instruction stored in the ROM 30 at addresses 120h to 123h is moved from the address 120h, which has been reallocated to the RAM 32, to 123h, and the data originally in the RAM 32 is stored in the monitor RA.
It is saved in the save area of M36. That is, the instruction from the address 120h to the address 123h is sent from the ROM 30 to the monitor RA.
M36 is transferred to the RAM 32 via M36.
Evacuated to

Next, the address 121h on the RAM 32 is changed to "
"add" is rewritten to "bkp" (breakpoint setting instruction code) (step S4).

Next, when the execution of the target program is started from the address 121h, the instruction codes from the addresses 120h to 123h are fetched into the instruction cache 20, and at the same time, the "bkp" instruction at the address 121h is executed. Is interrupted (step S5).

The change of the address assignment between the ROM 30 and the RAM 32 is restored. That is, 1 from address 120h
The setting of the address register of the memory controller 40b is returned so that the address 23h becomes the ROM 30 (step S6). The contents saved in the monitor RAM 36 are stored in the RAM 3
2 (step S7).

As a result, 121h of the instruction cache 20
The “bkp” instruction is stored in the location corresponding to the address, and the RO
M30, RAM 32 and monitor RAM 36 return to the initial state. When the instruction cache 20 and the ROM 30 are compared, the instruction codes at addresses 120h, 122h, and 123h are the same, but at address 121h, the instruction cache 20 is “bkp”, but the ROM 30
Becomes "add".

Next, the target program is executed (step S8). 1 while the target program is running
When the execution of the instruction at the address 21h is requested, the "add" instruction stored at the address 121h in the ROM 30 is not executed, but the index "in the instruction cache 20".
The "bkp" instruction stored in the block of "0" is executed, and as a result, the execution of the target program is interrupted (step S9).

By using such a method, R
It is possible to set a breakpoint in the area of the ROM 30 and perform a software break without rewriting the OM 30.

The RAM 32 and the monitor RAM 36
Is used temporarily for setting breakpoints. However, during execution of the target program after the breakpoint is set, the RAM 32 and the monitor RAM 36
Each is used for the target program or monitor program, and is not used for software breaks. That is, there is no need for a dedicated RAM for a software break.

To release a breakpoint,
The V bit at index 0 of the instruction cache 20 may be turned off. Then, even if execution of the instruction at address 121h is requested again, a cache miss occurs because the V bit at index 0 is off, and
The instruction code “add” is read from the address 1h, the “bkp” instruction is swept out of the instruction cache 20, and “
add "is stored. Thereby, the break point is released.

(Second Embodiment) Next, a case where a cache lock function is used will be described. Instruction cache 20
Turns on the lock bit to lock the fetched block if the lock status is set and the block to which the fetched instruction code belongs is lockable. When the lock bit of the index is turned on, the instruction code fetched from the ROM 30 at the time of instruction fetch is not stored in the locked index. Hereinafter, a case where a breakpoint is set at address 121h and locked will be described.

First, when the breakpoint setting instruction code is set at the address 121h of the RAM 32 according to the processing procedure of the above-described steps 1 to 4, the cache 2
Set the status of the lock to zero.

Next, the instruction is executed from address 121h,
The block to which address 21h belongs (123 from address 120h)
When address h) is taken into index 0, the lock bit of index 0 is turned on. Thereby, a breakpoint is set.

When the target program is executed again,
When the instruction at address 121h is executed, the execution of the target program is broken.

By using the lock function in this manner, even if the instruction code at another address (for example, address 180h) using index 0 is fetched during execution of the target program, the instruction code at address 180h is stored in the cache 20. And the tag of index 0 retains 12.

If the index 0 is not locked, for example, when the instruction code at the address 180h is executed, the tag and the block of the index 0 are rewritten. Then, when the instruction at the address 121h is called, a cache miss occurs, and the "add" instruction is read from the address 121h in the ROM 30, so that the break of the target program cannot be realized.

However, if the lock function is used, the "bkp" instruction is not flushed from the cache 20, and a software break is reliably realized.

When the "bkp" instruction is locked at index 0, it is preferable to clear the lock status so that it will not be locked in the execution of the following target program. That is, the indexes 0 to 3 are not locked while the index 0 is locked. This is because if the indexes 1 to 3 are locked, the cache 20 is not effectively used and the processing speed is reduced. To release the break point, the V bit and the L bit at index 0 may be cleared.

The software having such steps is, for example, a magnetic recording medium such as a floppy disk 83 or a cassette tape 86 or a CD-ROM as shown in FIG.
In addition to an optical disk such as the ROM 84, the information can be recorded on a computer-readable recording medium such as a memory device such as the ROM 85. In this case, the program is installed or the program is backed up by inserting the recording medium storing the software into a device such as a floppy disk drive 81 or a CD-ROM drive 82 of the computer main body 80. Can be.

According to the recording medium on which such a program is recorded, it is possible to easily store, execute, and transport a useful program that can easily set a breakpoint in the ROM area without rewriting the ROM. ,
Breakpoint setting can be made simpler and faster.

[0053]

As described above, according to the software break method and the computer readable recording medium storing the software break program of the present invention, the program stored in the ROM can be executed without rewriting the ROM. You can set breakpoints. Also, a software break can be performed without preparing hardware such as a dedicated RAM for realizing a breakpoint. In addition, by using the cache lock function, it is possible to prevent a break code from being swept out by an instruction at another address using the same index, so that a software break can be reliably performed. Also, the cache memory can be set in almost all address spaces,
Multiple breakpoints can be set without being restricted by the area. Further, the RAM and the memory controller can be used in a target program or the like. Further, storage, execution, transportation, and the like of a program for realizing such a method are simple and quick.

[Brief description of the drawings]

FIG. 1 shows a ROM used in an embodiment of the present invention;
FIG. 2 is a diagram illustrating a configuration of a RAM and the like.

FIG. 2 shows a ROM used in an embodiment of the present invention;
FIG. 4 is a diagram for explaining an allocation state of addresses such as a RAM.

FIG. 3 is a flowchart showing a processing procedure of a break method used in the embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a computer-readable recording medium on which a software break program used in the embodiment of the present invention is recorded.

[Explanation of symbols]

10 CPU, 20 instruction cache, 30 ROM
32 RAM, 34 monitor ROM, 36 monitor RA
M, 40a, b ... memory controller

Claims (4)

[Claims] 1. A method for setting a breakpoint in a program stored in a ROM without rewriting the ROM, wherein an address of a ROM area of a block including an address at which the breakpoint is to be set in the program is changed to a RAM area. An address allocation changing step; writing the block of the program stored in the ROM area to the RAM area; writing a RAM; and writing the block of the program written in the RAM area to the RAM area. An instruction code rewriting step of rewriting an instruction code at a desired address into a breakpoint setting instruction code; and writing the instruction code into a cache memory by executing the breakpoint setting instruction code. Step and is returned to the original state allocation change of the address of the ROM region and the RAM region, the breakpoint setting method characterized by having the address allocation change release step. 2. In the RAM writing step,
2. The method according to claim 1, wherein data in the RAM area is saved before writing to the RAM area, and the saved data is returned to an original address in the RAM area after the address assignment change release step. 3. How to set breakpoints. 3. The cache memory has a lock function, and in the cache memory writing step,
The breakpoint setting method according to claim 1, wherein after the breakpoint setting instruction code is stored, an index storing the breakpoint setting instruction code is locked. 4. An address assignment changing step of assigning an address of a ROM area of a block including an address at which a break point in a program stored in the ROM is desired to be set to the RAM area; RAM writing step of writing the stored block of the program, and rewriting an instruction code of a desired address in the block of the program written in the RAM area into an instruction code for setting a breakpoint; Writing the instruction code to a cache memory by executing the instruction code for setting a breakpoint; and writing the instruction code to a cache memory; and restoring the change of the address assignment between the ROM area and the RAM area to the original state. Computer readable recording medium storing a breakpoint setting program, characterized in that to execute the address assignment change release step, these processes include the computer.