JP2000267595A - Method of manufacturing array substrate for display device - Google Patents

Abstract

(57) Abstract: In a method of manufacturing an array substrate for a display device, a contact hole can be efficiently formed in a multilayer insulating film composed of a silicon oxide film and a silicon nitride film, and a method of manufacturing an array substrate. An object which can improve a pixel aperture ratio is provided. In a method for manufacturing an array substrate for a display device of a pixel-mounted type capable of reducing the number of steps, a contact hole (129) for exposing a source electrode (126b) of a TFT;
Upper metal wiring (125b) and lower metal wiring layer (111b)
In forming the contact holes (163-166) simultaneously exposing the silicon nitride film (127, 117) by dry etching and the removal of the silicon oxide film (115) by wet etching under one resist pattern. Is performed continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an array substrate used for a flat panel display such as a liquid crystal display.

[0002]

2. Description of the Related Art In recent years, flat-panel display devices replacing CRT displays have been actively developed. Among them, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, low power consumption, and low eye fatigue. I am collecting.

[0003] For example, a light-transmitting active-matrix liquid crystal display device in which a switch element is arranged for each display pixel will be described as an example. The active matrix type liquid crystal display device has a configuration in which a liquid crystal layer is held between an array substrate and a counter substrate via an alignment film. In the array substrate, a plurality of signal lines and scanning lines are arranged in a grid on a transparent insulating substrate such as glass or quartz, and amorphous silicon (hereinafter abbreviated as a-Si: H) is provided at each intersection. (Hereinafter abbreviated as TFT) using a semiconductor thin film of the above. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to a transparent conductive material constituting the pixel electrode, for example, ITO (Indium-Tin-Oxide). Have been.

[0004] The opposing substrate is configured such that an opposing electrode made of ITO is disposed on a transparent insulating substrate such as glass, and a color filter layer is disposed for realizing color display.

Here, usually, on the gate electrode and the scanning line, in order to insulate a semiconductor layer and the like above the gate electrode and the scanning line,
A first gate insulating film made of silicon oxide is provided, and a second gate insulating film made of silicon nitride is further provided. Further, an interlayer insulating film made of silicon nitride is arranged between the transparent conductive material layer and a metal wiring layer such as a signal line.

In order to reduce the manufacturing cost of such an active matrix liquid crystal display device, there is a problem that the number of steps for manufacturing an array substrate is large and the cost ratio of the array substrate is high.

Therefore, in Japanese Patent Application No. 8-260572, a pixel electrode is arranged on the uppermost layer, and accordingly, a signal line,
After collectively patterning the semiconductor film and the like together with the source and drain electrodes based on the same mask pattern, a contact hole for the source electrode connecting the source electrode and the pixel electrode is formed, and a signal line and a scanning line are formed. It has been proposed to simultaneously form an outer peripheral contact hole for exposing a connection end. As a result, the productivity can be improved with a small number of masks, and the manufacturing yield is not reduced.

[0008]

If the above-described method of manufacturing an array substrate is adopted, the first gate insulating film made of silicon oxide and the silicon nitride are formed so as to expose the connection ends of the signal lines and the scanning lines. It is necessary to make a contact hole in a multilayer film composed of the second gate insulating film and the interlayer insulating film.

However, when an attempt is made to form a contact hole in the multilayer film by dry etching (plasma etching or RIE etching), the overall etching rate, particularly the etching rate for the first gate insulating film made of silicon oxide, is extremely low. Therefore, the process time required for forming the contact hole becomes extremely long.

On the other hand, in the case of wet etching (wet chemical etching), even when an attempt is made to form a contact hole in the above-mentioned multilayer film by using an etching solution generally used industrially in the field of manufacturing a liquid crystal display device or a semiconductor, oxidation is not performed. It has been difficult to obtain a desired contact hole with practical efficiency because the etching rates of silicon and silicon nitride cannot be balanced.

In Japanese Patent Application No. 10-63254, a hydrogen fluoride-ammonium fluoride buffer (buffered hydrofluoric acid, BHF) is used as an etching solution for wet etching.
It has been proposed that a contact hole be formed in the multilayer film by only a single etching step using a single etching agent by selecting (1).

However, when a contact hole is formed in a multilayer film composed of a silicon oxide film and a silicon nitride film only by wet etching using buffered hydrofluoric acid, the etching time increases in proportion to the thickness of the multilayer film. Therefore, there is a problem that side etching becomes large. In order to increase the side etching and the blur width, it is necessary to increase the size of the contact hole forming portion.

In particular, since a part of the pixel electrode layer is of a pixel-placed type that covers the source electrode, it is necessary to make a region for forming a contact hole between the pixel electrode and the source electrode as large as the side etching and the blur width. Therefore, the size of the source electrode, which is an opaque portion, must be increased accordingly. Therefore, the ratio of the light transmitting portion, that is, the aperture ratio of the pixel is reduced accordingly.

FIGS. 8 and 9 schematically show a case where a contact hole is formed using only buffered hydrofluoric acid. Here, in the pattern formation of the array substrate, the description of the steps (first to fifth steps, interlayer insulating film formation before the sixth step, and seventh step) other than the contact hole forming step (the latter step of the sixth step) will be described. Omitted.

FIG. 8 schematically shows the state at the beginning of the etching, when the size of the opening for the contact hole (129, 165, 166) is almost the size of the resist pattern. FIG. 9 schematically shows a state after the completion of the etching. With the progress of the side etching, an opening having a size considerably larger than the original size is formed so as to form the contact holes (129, 164-166). Therefore, as shown in the figure, when the thickness of the multilayer film is large, significant side etching occurs, so that the source electrode (126b)
It is necessary to increase the dimensions such as.

When using buffered hydrofluoric acid,
For example, an etching time of about 6 to 7 minutes is required to penetrate a multilayer film having a thickness of 600 nm, and the production efficiency cannot be sufficiently improved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to efficiently form a contact hole in a multilayer insulating film including a silicon oxide film and a silicon nitride film, and to sufficiently increase an aperture ratio. It is intended to provide a method for manufacturing an array substrate, which can be kept at a high temperature.

[0018]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a scanning line disposed on a substrate; a first insulating film disposed thereon; a semiconductor film disposed thereon; A thin film transistor including a source electrode and a drain electrode that are electrically connected, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and formed two-dimensionally;
A pixel electrode electrically connected to the source electrode, a conductive layer pattern formed at the same time as the extension of the scan line or the scan line, and a conductive layer pattern formed at the same time as the extension of the signal line or the signal line; And a connection wiring formed in the same step as the pixel electrode, for electrically connecting the conductive layer pattern via a first contact hole formed on the scanning line. In the manufacturing method, the first contact hole penetrates a multilayer film including at least one silicon nitride film and at least one silicon oxide film, and partially removing the silicon nitride film by dry etching. And a step of partially removing the silicon oxide film by wet etching.

According to the above configuration, side etching when forming a contact hole can be suppressed, thereby eliminating the need for a dimensional margin of the contact hole between the source electrode and the pixel electrode, thereby improving the pixel aperture ratio. . Further, the manufacturing efficiency when forming the contact hole can be improved, and the process load and the manufacturing cost can be reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Structure of Array Substrate> The structure of an array substrate for a display device according to the present invention will be described below with reference to FIGS. 1 to 2 and FIG.

FIG. 1 is a schematic plan view of the array substrate (100), in which the lower side in the figure is located at the upper side of the screen of the liquid crystal display device, and the lower side in the figure is from the lower side to the upper side. The scanning lines are sequentially selected.

The array substrate (100) includes 480 scanning lines (111) arranged on a glass substrate (101).
One end of 1) is drawn out to one end side (101a) of the glass substrate (101), and is electrically connected to the scanning line pad (152) via the oblique wiring section (150).

The array substrate (100) includes 1920 signal lines (110) which are substantially orthogonal to the scanning lines (111) on the glass substrate (101), and each signal line (110) is provided on the glass substrate (101). The other end (101
It is drawn out to the b) side and is electrically connected to the signal line pad (162) via the oblique wiring portion (160).

A TFT (112) is arranged near the intersection of the scanning line (111) and the signal line (110).

(1) Structure of TFT Part The laminated structure of the TFT (112) will be described with reference to the left half of the schematic diagram of FIG.

The TFT (112) is of an inverted stagger type with the scanning line (111) as a lower metal wiring as a gate, and a portion extending from the signal line (110) as an upper metal wiring is a drain electrode. (126a), and has a channel protective film (122) in the channel portion. Further, the TFT (112) is of a pixel-placed type, and the source electrode (126b) is connected to the pixel via a contact hole (129) provided in the interlayer insulating film (127) so as to expose the upper surface. Connected to electrode (131).

(2) Structure of the Outer Peripheral Part on the Signal Line Side The structure near the outer peripheral part of the signal line (110) will be described with reference to FIGS.

As shown in FIG. 1, a lower wiring portion (111b) formed of the same material in the same step as the scanning line (111) is provided on the glass substrate (101) in correspondence with each signal line (110). The oblique wiring part (160) of the signal line (110) on one end side (101b) side and the signal line pad (16)
2) is located.

As shown in FIG. 7, in the diagonal wiring portion (160), a two-layer insulating film (11) is formed on the lower wiring portion (111b).
5) and (117) are arranged. In addition, these two insulating films (1
15), (117), semiconductor film (119), low-resistance semiconductor film
(123) and an upper wiring portion (125b) extending from the signal line (110)
Are stacked, and an interlayer insulating film (1) is formed on the upper wiring portion (125b).
27) is located.

In the oblique wiring portion (160), the signal line (110)
An upper wiring portion (125b) extending from the first wiring portion and a lower wiring portion (111b) formed of the same material in the same step as the scanning line (111) are stacked and arranged. The base (160) is electrically connected to the signal line pad (162).

Therefore, in the diagonal wiring part (160), even if one of the upper wiring part (125b) or the lower wiring part (111b) is broken, the other is connected. The occurrence of defects is reduced.

At the base of the oblique wiring portion (160) and the signal line pad (162), the first contact hole (164) is formed in the region where the second contact holes (163) and (165) are formed, respectively. ) And (166) are formed. And
By providing a signal line connection layer (131b) formed of ITO of the same material in the same step as the pixel electrode (131) in the region of these contact holes, an upper layer extending from the signal line (110) is provided. The wiring part (125b) and the lower wiring part (111b) are electrically connected. The first contact hole (16
4) and (166) are two layers of insulating films (115) and (117) and a semiconductor film (11) so as to expose a part of the main surface of the lower wiring portion (111b).
9), an opening penetrating the low-resistance semiconductor film (123) and the upper wiring portion (125b), the second contact hole (163) and
An opening (165) penetrates the interlayer insulating film (127) so as to expose a part of the main surface of the upper wiring portion (125b).

As schematically shown in the longitudinal sectional perspective view of FIG. 2, the bottom surface (163b) of the second contact hole (163) has a donut shape and the outer edge (164) of the first contact hole (164).
b) is the inner edge of the donut-shaped bottom surface (163b) at the same time.

As described above, since the first contact hole is arranged in the region where the second contact hole is formed,
The area for forming the contact hole can be the minimum area in the case where both contact holes are connected by the connection layer (131b).

Although the connection layer (131b) is made of ITO and has a high resistivity, the connection layer (131b) covering the lower wiring portion (111b) at the bottom of the first contact hole and the second contact hole Connection layer that covers the upper wiring section (125b) at the bottom
The (131b) portion is coupled only via the connection layer (131b) portion on the step surface of the first contact hole. Therefore, the wiring length of the connection layer (131b) is minimized. In addition, such connection is made over the entire periphery of the outer edge of the first contact hole. Therefore, the connection layer (131
b) The display resistance such as crosstalk is not caused by the resistance of the portion.

The structure of the outer peripheral portion on the scanning line side is the same as the above-described outer peripheral structure near the signal line.

In this embodiment, as shown in FIG.
Although the storage capacitor (Cs) has been described as being formed by the scanning line extending portion (113), a configuration in which a storage capacitor line (Cs line) parallel to the scanning line (111) is also provided. it can. In this case, one end or both ends of each auxiliary capacitance line (Cs line) formed of the same material in the same step as the scanning line (111) is connected to the Cs formed of the same material in the same step as the signal line (110). It is connected to the binding wire via a contact hole.
This contact hole can have exactly the same structure as that described above in the outer peripheral portion on the signal line side.

<Manufacturing Process of Array Substrate> Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS. In the following description, the manufacturing process of the outer peripheral portion near the scanning line is exactly the same as the manufacturing process of the outer peripheral portion near the signal line, and thus the description is omitted.

(1) First Step A Mo-W film (molybdenum-tungsten alloy film) is deposited on a glass substrate (101) to a thickness of 300 nm by a sputtering method.

On this laminated film, a scanning line pattern and a part of the auxiliary capacitance wiring are formed by photolithography,
Dry etching is performed in a tapered shape by F ₄ / O ₂ system CDE (chemical dry etching) to complete a scanning line and an auxiliary capacitance wiring pattern (first patterning).

As a result, 480 pieces are placed on the glass substrate (101).
While making the scanning line (111), one end side (101a)
On the side, the oblique wiring portion (150) of the scanning line (111) and the lower wiring portion (111a) constituting the scanning line pad (152), one end side (101b)
At the same time, the oblique wiring portion (160) of the signal line (110) and the lower wiring portion (111b) constituting the signal line pad (162) are simultaneously produced.

Further, in the TFT region, a gate electrode is formed integrally with the scanning line (111) and led out in a direction perpendicular to the scanning line (111). Further, an extension region (113) which is derived in a direction orthogonal to the scanning line (111) when patterning the scanning line (111) and forms an auxiliary capacitance (Cs) is also prepared at the same time (FIG. 1). reference).

(2) Second Step After the first step, the glass substrate (101) is heated to 300 ° C. or higher, and then a first gate made of a silicon oxide film (SiOx film) having a thickness of 350 nm is formed by a normal pressure plasma CVD method. Insulating film
After the deposition of (115), a second gate insulating film (117) made of a 50-nm-thick silicon nitride film, a 50-nm-thick a-Si: H semiconductor film (119) and a 200-nm-thick A channel protective film (121) made of a silicon nitride film is formed without being continuously exposed to the air.

Instead of a SiOx film, a glass substrate (101)
Is heated to 300 ° C. or more, and then SiO 2 is formed by thermal CVD.
_Two films may be used.

(3) Third Step After the second step, the channel protective film is self-aligned with the scanning line (111) by the back surface exposure technique using the scanning line (111) as a mask.
The (121) is patterned, further exposed using a second mask pattern so as to correspond to the TFT region, developed, and patterned (second patterning) to form an island-shaped channel protective film (122). .

(4) Fourth Step After the third step, as shown in FIG. 3, the exposed surface of the semiconductor film (119) is treated with a hydrofluoric acid (HF) -based solution to obtain a good ohmic contact. 30 nm-thick n ⁺ a-S containing phosphorus as an impurity by plasma CVD
i: depositing a low-resistance semiconductor film (123) consisting of H;
A Mo film (molybdenum film) (125) having a thickness of 0 nm is deposited by sputtering.

(5) Fifth Step After the fourth step, as shown in FIG. 4, after exposing and developing using a third mask pattern, a Mo film (125), a low-resistance semiconductor film (123) and The semiconductor film (119) is patterned (third patterning). At this time, the Mo film (1
In 25), patterning is performed by wet etching using a mixed acid of phosphoric acid, nitric acid, acetic acid and water. In addition, the low resistance semiconductor film (123) and the semiconductor film (119) are selectively etched by the first gate insulating film (115) or the second gate insulating film (117) made of a silicon nitride film and the channel protective film (122). By controlling the ratio, patterning is performed by plasma etching.

Thus, in the TFT region, the source electrode (126b) and the low resistance semiconductor film portion (124a) thereunder are integrally formed, and the signal line (110) and the drain electrode (126a) are formed.
And the low resistance semiconductor film portion (124b) thereunder are integrally formed.

At the base of the signal line pad (162) and the oblique wiring portion (160), the Mo film (1) extends along the lower wiring portion (111b).
25) is patterned to form an upper wiring portion (125b) extending from the signal line (110), and a low-resistance semiconductor film (123) and a semiconductor film (119) are formed along the upper wiring portion (125b). Patterning is performed at once.

At the same time, the upper wiring portion (125b) corresponding to the first contact holes (164) and (166) described above,
Openings (164a) and (166a) penetrating the low resistance semiconductor film (123) and the semiconductor film (119) are formed.

Here, the Mo film (125), the low-resistance semiconductor film (123) and the semiconductor film (119) are patterned by a continuous process of wet etching and subsequent dry etching. Alternatively, it can be performed only by wet etching.

(6) Sixth Step After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited thereon.

Then, exposure and development are performed using the fourth mask pattern to form a resist pattern. Formation of contact holes (129, 164-166) (fourth patterning)
Is performed by successively performing dry etching and wet etching in this order on the same resist pattern formed using the fourth mask pattern.

Hereinafter, the two-stage etching process for forming the contact holes (129, 164-166) will be described in detail with reference to FIGS.

A. Removal of Silicon Nitride Film by Dry Etching (FIG. 5) Chemical dry etching (CDE) is performed for 20 seconds with the above resist pattern formed.

As a result, as shown in FIG. 5, the interlayer insulating film (127) is removed in a part of the TFT region corresponding to the source electrode (126b), and the contact hole (129) is removed.
Is formed.

On the other hand, at this time, the openings (164a), (166a),
Then, the interlayer insulating film (127) is collectively removed at the opening edge portions surrounding these openings (164a) and (166a). This allows
First, the second contact holes (163) and (165) are formed. At the bottom of the openings (164a) and (166a), the interlayer insulating film
Subsequent to the removal of (127), the second gate insulating film (117) is continuously removed.

The dry etching may be general plasma etching or reactive ion etching in addition to the above-mentioned chemical dry etching.

B. Removal of Silicon Oxide Film by Wet Etching (FIG. 6) Following the above dry etching, with the same resist pattern formed, a hydrogen fluoride-ammonium fluoride buffer (buffered hydrofluoric acid) was used. , BHF) for 60 seconds.

Buffered hydrofluoric acid is prepared by adding hydrogen fluoride to 6
%, And an aqueous solution containing 30% of ammonium fluoride. As an etching agent for performing wet etching, a hydrogen fluoride-based agent other than buffered hydrofluoric acid can be used. For example, an acetic acid solution of hydrogen fluoride-ammonium fluoride, a hydrogen fluoride-amine fluoride buffer and the like can be used.

The signal line pad is formed by wet etching.
(162) and an opening (164) at the base of the oblique wiring portion (160).
The first gate insulating film is removed at the bottoms of a) and (166a) to form first contact holes (164) and (166) (FIG. 6).

The contact holes (164-166)
At the same time, scan line side pad (152) and scan line side diagonal wiring
Similarly, at the base of (150), a contact hole connecting the upper layer wiring and the lower layer wiring is formed.

At the completion of the etching shown in FIG.
The dimensions of the contact hole (129) and the second contact holes (163) and (165) of the source electrode portion are substantially the same as the contact hole portion in the resist pattern formed according to the mask pattern. Since the time of the wet etching is sufficiently short, about 60 seconds, the enlargement and displacement of the dimensions due to the side etching are suppressed to a level that causes almost no problem.

Therefore, it is not necessary to incorporate a margin due to side etching when forming the contact hole (129) in the area dimension of the source electrode (126b).
The minimum dimensions required for the formation of 2) and sufficient conduction to the pixel electrode (131) can be set.

(7) Seventh Step After the sixth step, as shown in FIG. 7, an ITO film having a thickness of 40 nm is deposited thereon by sputtering at a substrate temperature of 230 ° C., and is exposed using a fifth mask pattern. After developing,
Patterning for producing the pixel electrode (131) is performed (fifth patterning). The patterning of the ITO film may be wet etching or dry etching.

As shown in FIG. 7, the source electrode (12) is formed through the contact hole (129) formed in the sixth step.
6b) and the pixel electrode (131) are connected.

At the same time, at the bases of the signal line pad (162) and the oblique wiring portion (160), as shown in FIG. 7, the second contact holes (163) and (165) and the first contact hole
The patch-like connection layer (131) covers the regions (164) and (166).
Form b). As a result, the signal line (110) and the signal line connection pad (162) are separated from the lower wiring portion (111b) and the upper wiring portion (125b).
Are electrically connected by the two-layer diagonal wiring portion (160). The same applies to the peripheral portion on the scanning line side.

In the array substrate (1) according to the above embodiment, the contact holes (129, 1) are formed only by wet etching.
63-66), and the area dimensions of the source electrode (126b) can be reduced as compared with the comparative example (the manufacturing method of the above-mentioned Japanese Patent Application No. 10-63254, see FIGS. 8 to 9). As a result, the pixel aperture ratio could be improved by 0.2%.

Since the silicon nitride film and the silicon oxide film can be removed by the most efficient etching, the time required for the entire etching can be minimized. The manufacturing efficiency can be improved and the manufacturing cost can be reduced.

In the manufacturing method of the above embodiment, although two types of etching are performed by switching, the etching is continuously performed while the same resist pattern is formed, so that the process load hardly increases due to the switching. .

Therefore, according to the method of manufacturing an array substrate according to the above-described embodiment, it is possible to simultaneously improve the pixel aperture ratio and the manufacturing efficiency, and to reduce the process load and the manufacturing cost.

In the above embodiment, the semiconductor film (119)
Has been described using a-Si: H, but the same applies to a polycrystalline silicon film or the like. Further, the signal line pad (162) and the scanning line pad (152) have been described as being provided in the peripheral region of the array substrate, and the pads (152) and (162) are provided. And an input connection to the drive circuit may be formed.

[0073]

According to the method of manufacturing an array substrate of the present invention, the pixel aperture ratio can be improved, the manufacturing efficiency can be improved, and the processing load and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a partial schematic plan view of an array substrate according to one embodiment of the present invention.

FIG. 2 is a schematic cross-sectional perspective view showing a stacked structure of a contact hole forming region in a connection pad portion on a peripheral edge of an array substrate according to an example.

FIG. 3 is a cross-sectional view of a stacked structure after a fourth step in the method of manufacturing an array substrate according to the example.

FIG. 4 is a cross-sectional view of a layered structure after a fifth step in the method of manufacturing an array substrate according to the example.

FIG. 5 is a cross-sectional view of a stacked structure at the time of completion of dry etching in a sixth step in the method of manufacturing an array substrate according to the example.

FIG. 6 is a cross-sectional view of a layered structure after completion of a sixth step (at the time of completion of wet etching) in the method of manufacturing an array substrate according to an example.

FIG. 7 is a cross-sectional view of a layered structure after a seventh step in the method of manufacturing an array substrate according to the example.

FIG. 8 is a cross-sectional view illustrating a state of an initial stage of etching during a sixth step in the method of manufacturing an array substrate according to a comparative example.

FIG. 9 is a cross-sectional view showing a state after a sixth step in a method of manufacturing an array substrate according to a comparative example.

[Explanation of symbols]

 110 signal line 111 scanning line 111b lower wiring section 112 thin film transistor 113 extension area 115 first gate insulating film 117 second gate insulating film 120 semiconductor film 125 three-layer laminated metal film 125b upper wiring section 126a drain electrode 126b source electrode 131 pixel electrode 132 ITO connection layer 111 signal line 164,166 first contact hole 163,165 second contact hole 164b outer edge of first contact hole 163b bottom surface of second contact hole

Continued on the front page (72) Inventor: Akira Kubo 50, Kamiyube, Amebe-ku, Himeji-shi, Hyogo Pref. Inside the Toshiba Himeji Plant (72) Inventor: Madoka Nakajima 50, Kamiyobe, Amebe-ku, Himeji-shi, Hyogo Co., Ltd. Inside the factory (72) Inventor Yasuyuki Imamura 7-1 Nisshin-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa F-term (reference) in Toshiba Electronics Engineering Co., Ltd. 2H092 GA59 JA26 JA29 JA35 JA36 JA38 JA42 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB69 KA05 KA07 KA12 KA16 KA18 KB14 KB25 MA05 MA08 MA13 MA14 MA15 MA18 MA19 MA20 MA27 MA35 MA37 MA41 NA07 NA15 NA25 NA27 NA29 PA06 5C094 AA10 AA42 AA43 BA03 BA43 CA19 DA15 EA03 EA04 EA07 FB02 EB02 EE02 BB02 GB01 5F110 A FF03 FF09 FF29 FF30 FF32 GG02 GG13 GG15 GG25 GG47 HK04 HK09 HK16 HK25 HK33 HK35 HK41 HL07 HL23 NN03 NN04 NN12 NN14 NN23 NN24 NN35 NN73 QQ01 QQ04 QQ05 QQ09 QQ12

Claims (6)

[Claims] 1. A scanning line disposed on a substrate, a first insulating film disposed thereon, a semiconductor film disposed thereon, a source electrode and a drain electrode electrically connected to the semiconductor film A signal line derived from the drain electrode and substantially orthogonal to the scanning line; a pixel electrode formed two-dimensionally and electrically connected to the source electrode; A first contact hole formed on the scanning line by forming an existing portion or a conductive layer pattern formed simultaneously with the scanning line, and an extending portion of the signal line or a conductive layer pattern formed simultaneously with the signal line; And a connection wiring formed in the same step as the pixel electrode, which is electrically connected through the first contact hole. A step of removing a part of the silicon nitride film by dry etching, and a step of removing a part of the silicon oxide film by wet etching. A method for manufacturing an array substrate for a display device, wherein the method is formed by continuously performing a removing step. 2. The method according to claim 1, wherein the first insulating film has a laminated structure of the silicon oxide film and the silicon nitride film. 3. The pixel electrode is electrically connected to the source electrode via a second contact hole of a second insulating film disposed on the source electrode, and the first contact hole is connected to the first insulating film. 2. The method according to claim 1, further comprising penetrating the second insulating film. 4. The method according to claim 3, wherein the first insulating film includes the silicon oxide film, and the second insulating film includes the silicon nitride film. 5. The method according to claim 4, wherein the first insulating film includes another silicon nitride film on the silicon oxide film. 6. A scanning line disposed on a substrate, first and second insulating films disposed thereon, a semiconductor film disposed thereon, and a source electrode electrically connected to the semiconductor film. A thin film transistor including: a drain electrode; a signal line derived from the drain electrode and substantially orthogonal to the scanning line; and a pixel electrode formed two-dimensionally and electrically connected to the source electrode. In a method of manufacturing an array substrate for a display device, the method comprises the steps of: forming a contact hole penetrating a multilayer film including at least one silicon nitride film and a silicon oxide film; A method of manufacturing an array substrate for a display device, comprising: continuously removing a film and removing the silicon oxide film by wet etching. Method.