JP2000260785A - Vertical semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a method for manufacturing IEGT without reducing area efficiency. SOLUTION: A single-crystal silicon layer 45 is selectively removed by etching, so that a buried gate electrode 11,
13, 15, 17 are formed. Next, an amorphous silicon layer 55 is formed between the buried gate electrodes. And
The amorphous silicon layer 55 is turned into a single crystal silicon layer 57 by solid phase epitaxial growth.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vertical semiconductor device having a base layer formed between buried gate electrodes and a method for manufacturing the same.

[0002]

BACKGROUND ART IGBT (Insulated Gate)
Bipolar Transistor is a bipolar transistor having a MOS gate. The IGBT has a high-speed switching characteristic and a voltage driving characteristic of a MOSFET and a low ON voltage characteristic of a bipolar transistor. The IGBT is an element that has attracted attention in the field of power electronics. FIG. 16 is a sectional view of an example of the IGBT. This IGBT is a transistor technology special
al No. 54 (CQ Publishing Company), page 34.

First, the structure of the IGBT will be described. The IGBT 100 has a structure in which a collector electrode 102, a p ⁺ -type collector layer 104, an n ⁺ -type buffer layer 106, an n ^-- type epitaxial layer 108, and a p-type base layer 110 are stacked. In the IGBT 100, trenches 124 and 126 that penetrate the p-type base layer 110 and reach the n ⁻ -type epitaxial layer 108 are formed at predetermined intervals. A buried gate electrode 116 is formed in the trench 124. The buried gate electrode 11 is formed in the trench 124.
6, a gate oxide film 120 is formed. On the surface of p-type base layer 110, n ⁺ -type emitter layer 1
12 are formed. N ⁺ type emitter layer 112 is in contact with trench 124. A buried gate electrode 118 is formed in the trench 126. A gate oxide film 122 is formed in trench 126 so as to cover buried gate electrode 118. An n ⁺ -type emitter layer 114 is formed on the surface of the p-type base layer 110. N ⁺ type emitter layer 114 is in contact with trench 126.

Next, the operation of the IGBT will be described. (1) A positive voltage is applied to the buried gate electrodes 116 and 118. Thus, an n-type channel is formed in the p-type base layer 110 and near the gate oxide films 120 and 122. (2) p ⁺ type collector layer 104
And n ⁻ -type epitaxial layer 108 is forward-biased. As a result, holes are injected from the p ⁺ -type collector layer 104 into the n ⁻ -type epitaxial layer 108. (3) as many electrons as injected holes of positive charges the n ^- so gather -type epitaxial layer 108, n ^- resistance type epitaxial layer 108 is lowered. (1) above,
The IGBT 100 is turned on by (2) and (3).

[0005] Incidentally, the IGBT is required to have a low ON voltage. When the concentration of the n ⁻ -type epitaxial layer 108 is increased, the ON voltage can be reduced. However, this lowers the breakdown voltage of the IGBT. As described above, as many electrons as the positive charges of the injected holes are collected in the n ⁻ -type epitaxial layer 108. Therefore, when the density of holes injected into the n ⁻ -type epitaxial layer 108 is increased, the breakdown voltage can be maintained while lowering the resistance of the n ⁻ -type epitaxial layer 108.

As a structure that can increase the density of holes injected into the n ⁻ -type epitaxial layer 108, the distance between the buried gate electrodes 116 and 118 is reduced, and the buried gate electrodes 116 and 11 are formed.
There is a structure in which the lateral length of 8 is increased. This is disclosed in IEDM93 at pages 679-682. As specific parameters, according to this document, the distance between the buried gate electrodes is 3 μm, and the lateral length of the buried gate electrode is 10 μm.

By the way, in order to form a buried gate electrode having a horizontal length of 10 μm, a horizontal length of 1 μm is required.
A film (for example, a polysilicon film) serving as a buried gate electrode must be buried in the 0 μm trench.
In this case, the trench cannot be completely filled with the polysilicon film unless the polysilicon film has the same thickness as the lateral length of the trench. However, this thickness is equivalent to 10 to 20 times the thickness of the polysilicon film used in the ordinary semiconductor device manufacturing technology.
It is difficult to realize a polysilicon film having such a thickness in a process.

[0008] Therefore, IEGT, which is an improved type of IGBT,
(Injection-Enhanced Gate
BipolarTransistor) was developed.
FIG. 17 is a three-dimensional sectional view of the IEGT disclosed in the IEDM 93. IEGT 200 has an anode electrode 202,
It has a structure in which a p-type emitter layer 204, an n-type buffer layer 206, an n ⁻ -type base layer 208, and a p-type base layer are stacked. The IEGT 200 has trenches 222, 224, 2, which penetrate the p-type base layer and reach the n ⁻ -type base layer 208.
26, 228 and 230 are formed at predetermined intervals.
With these trenches, the p-type base layer becomes the p-type base layer 2.
10, 212, 214, and 216. On the surface of p-type base layer 210, n-type source layer 218 is formed. On the surface of p-type base layer 216, n-type source layer 220 is formed. Trenches 222, 224, 2
Buried gate electrodes 232, 234, 236, 238, 240 are formed in 26, 228, 230, respectively. These buried gate electrodes are covered with a gate oxide film.

In IEGT 200, the distance between the buried gate electrodes is, for example, 3 μm, and the lateral length of the buried gate electrodes is, for example, 1 μm. All the buried gate electrodes are electrically connected to each other.
All p-type base layers 210, 212, 214, 216
No source layer is formed, and one source layer is formed for every ten p-type base layers. Thus, a structure equivalent to a structure in which the distance between the buried gate electrodes is 3 μm and the length of the buried gate electrode in the horizontal direction is 10 μm is realized.

[0010]

However, in the structure shown in FIG. 17, there are a number of p-type base layers in which no n-type source layer is formed (for example, p-type base layers 212 and 21).
4). Such a p-type base layer becomes a dead space, resulting in poor area efficiency. This is a factor that hinders a reduction in the ON voltage of the IEGT, for example.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a vertical semiconductor device which does not reduce the area efficiency and a method for manufacturing the same.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a vertical semiconductor device in which a base layer of a first conductivity type is formed between buried gate electrodes. A step of forming a first insulating film serving as a first gate insulating film on the second layer in a stacked structure including a certain first layer and a second layer of a second conductivity type; (B) a step of forming a third layer to be a buried gate electrode on the first insulating film; and (c) a step of selectively etching and removing the third layer so that the buried gate electrode becomes the first layer. (D) forming a second gate insulating film on the side surface of the buried gate electrode; and (e) forming a first gate insulating film on the side surface of the buried gate electrode.
Forming a fourth layer including a single crystal layer between the buried gate electrodes, (f) forming a base layer in the fourth layer, and (g) a second conductivity type. Forming a fifth layer in the base layer.

In the method of manufacturing a vertical semiconductor device according to the present invention, a buried gate electrode is not formed in a trench. First, a buried gate electrode is formed by selectively etching away the third layer. And a fourth layer including the first single crystal layer between the buried gate electrodes.
Is formed. Therefore, a structure in which the distance between the buried gate electrodes is shortened and the length of the buried gate electrode in the lateral direction can be increased without reducing the area efficiency.

In the method for manufacturing a vertical semiconductor device according to the present invention, in the step (e), the sixth layer including the first amorphous layer is located between the buried gate electrodes and is exposed. A step of forming a sixth layer on the second layer, a step of single-crystallizing the sixth layer by solid phase epitaxial growth to form a fourth layer,
It is preferable to provide In this step, the fourth layer including the first single crystal layer is not formed directly between the buried gate electrodes. First, a sixth layer including a first amorphous layer is formed between the buried gate electrodes and on the exposed second layer. The sixth layer is single-crystallized by solid phase epitaxial growth using the second layer as a seed crystal part, and is turned into a fourth layer.

In the method for manufacturing a vertical semiconductor device according to the present invention, (h) the first insulating film below the buried gate electrode formation region is left between the steps (a) and (b). ,
Preferably, the method further includes a step of forming an opening for exposing the second layer by removing the first insulating film below the formation region of the base layer.

In the method of manufacturing a vertical semiconductor device according to the present invention, in the step (b), the third layer preferably includes a second single crystal layer. An example of a method for forming the second gate insulating film on the side surface of the buried gate electrode is thermal oxidation. In this case, the withstand voltage of the second gate insulating film (oxide film) is higher when the buried gate electrode layer is single crystal than when it is polycrystalline.

In the method of manufacturing a vertical semiconductor device according to the present invention, in the step (b), the seventh layer including the second amorphous layer is exposed on the first gate insulating film and at the opening. Preferably, the method includes a step of forming the third layer on the second layer and a step of single-crystallizing the seventh layer by solid phase epitaxial growth to form a third layer. In this step, the third layer including the second single crystal layer is not formed directly between the buried gate electrodes. First, a seventh layer including a second amorphous layer is formed between the buried gate electrodes and on the exposed second layer. The second amorphous layer is converted into a second single crystal layer by solid phase epitaxial growth using the second layer as a seed crystal part.

In the method for manufacturing a vertical semiconductor device according to the present invention, in the step (d), a second insulating film is formed on the upper surface of the buried gate electrode. Further, the method for manufacturing a vertical semiconductor device preferably includes a step of forming a third insulating film on the second insulating film.

In the method of manufacturing a vertical semiconductor device according to the present invention, in the step (h), the horizontal length of the first gate insulating film is made larger than the horizontal length of the opening. preferable. In the method of manufacturing a vertical semiconductor device according to the present invention, it is preferable that, in the step (c), the length of the buried gate electrode in the horizontal direction is larger than the distance between the buried gate electrodes.

According to the present invention, a first layer of the first conductivity type, a second layer of the second conductivity type located on the first layer, and a first layer of the second conductivity type located on the second layer are provided. A first gate insulating film and a first
A buried gate electrode located on the first gate insulating film and including the second single crystal layer, a second gate insulating film located on a side surface of the buried gate electrode, and a first conductive material located between the buried gate electrodes A base layer that is a mold, and a fifth layer that is a second conductivity type located in the base layer, wherein the length of the buried gate electrode in the horizontal direction is greater than the distance between the buried gate electrodes. Semiconductor device. The vertical semiconductor device having this structure can be manufactured by the method for manufacturing a vertical semiconductor device according to the present invention. The lateral length of the buried gate electrode is preferably 3 μm or more. The distance between the buried gate electrodes is preferably 3
μm or less.

In the vertical semiconductor device according to the present invention, it is preferable that a side portion of the buried gate electrode is a second single crystal layer. When the second gate insulating film is formed on the side surface of the buried gate electrode by thermal oxidation, if the side surface portion of the buried gate electrode is a single crystal layer, the withstand voltage of the second gate insulating film becomes relatively large. is there.

A vertical semiconductor device according to the present invention comprises a second insulating film in contact with an upper surface of a buried gate electrode;
And a third insulating film located on the first insulating film. For example, when the seventh layer is single-crystallized by solid phase epitaxial growth using the second layer as a seed crystal part to form a third layer including the second single crystal layer, the central part of the buried gate electrode is It may be a polycrystalline layer. This is because single crystallization hardly proceeds in the lateral direction. For this reason, when the second gate insulating film is formed on the side surface of the buried gate electrode by thermal oxidation, there is a possibility that a problem may occur in the film quality of the second insulating film formed on the upper surface of the buried gate electrode. That is, as described above, a region located on the central portion of the buried gate electrode on the upper surface of the buried gate electrode may become a polycrystalline layer. The withstand voltage of the second gate insulating film (oxide film) formed on the polycrystalline layer is smaller than the withstand voltage of the second gate insulating film (oxide film) formed on the single crystal layer. Since the vertical semiconductor device according to the present invention includes the third insulating film located on the second insulating film, even if the second gate insulating film (oxide film) has a low withstand voltage, the third insulating film is formed. The presence of the film makes it possible to maintain a predetermined breakdown voltage.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Description of Structure] FIG.
It is sectional drawing of one Embodiment of such a vertical semiconductor element. Vertical
The type semiconductor device is an IEGT. IEGT1 is a collector
Electrode 3, p⁺Type collector layer 5, n⁺Type buffer layer 7, n^-
It has a structure in which the epitaxial layers 9 are stacked. p ⁺
The type collector layer 5 is an example of a first layer. n^-Type epita
The axial layer 9 is an example of a second layer. n^-Epitaxy
On the shallow layer 9, buried gate electrodes 11, 13, 1
5 and 17 are formed at intervals. Embedded game
The distance D between the electrodes is 3 μm or less. Embedded gate
The lateral length of the electrode is 3 μm or more. Embedded game
Between the gate electrode 11 and the buried gate electrode 13.
The source layer 19 is formed, and is buried with the buried gate electrode 13.
P-type base layer 21 is formed between embedded gate electrode 15
Buried gate electrode 15 and buried gate electrode 1
7, a p-type base layer 23 is formed. p-type
The bottom surfaces of the base layers 19, 21 and 23 are embedded gate electrodes.
11, 13, 15, and 17 are located above the bottom surface.

On the lower surface of the buried gate electrode 13, a first gate oxide film 25 is located. The first gate oxide film 25 is an example of a first gate insulating film. Second gate oxide films 27 and 29 are located on the side surfaces of the buried gate electrode 13. The second gate oxide films 27 and 29 are an example of a second gate insulating film. The silicon oxide film 31 is located on the upper surface of the buried gate electrode 13. The silicon oxide film 31 is formed simultaneously with the formation of the second gate oxide films 27 and 29. The silicon oxide film 31 is
1 is an example of the insulating film. The silicon oxide film 33 is located so as to cover the silicon oxide film 31. The silicon oxide film 33 is an example of a third insulating film. A similar film is formed around the buried gate electrodes 11, 15, and 17.

On the surface of the p-type base layer 19 and the surface of the p-type base layer 21, n ⁺ -type emitter layers 35 and 37 are formed. The n ⁺ type emitter layer 35 is in contact with the second gate oxide film 27. The n ⁺ -type emitter layer 37 is in contact with the second gate oxide film 29. The n ⁺ -type emitter layers 35 and 37 are an example of a fifth layer. Similar n ⁺ -type emitter layers are also formed around the buried gate electrodes 11, 15 and 17. An emitter electrode 39 electrically connected to the n ⁺ -type emitter layers in the p-type base layers 19, 21, and 23 is located on the silicon oxide film 33.

[Description of Operation] Next, the operation of one embodiment of the vertical semiconductor device according to the present invention will be described. (1) A positive voltage is applied to the buried gate electrodes 11, 13, 15, and 17. Thereby, the p-type base layers 19, 2
1 and 23 and the second gate oxide films 27 and 29
, An n-type channel is formed. (2) A forward bias is applied between the p ⁺ type collector layer 5 and the n ⁻ type epitaxial layer 9. As a result, the p ⁺ -type collector layer 5 to n ⁻
Hole injection into the epitaxial layer 9 occurs. (3) as many electrons as injected holes of positive charges the n ^- so gather -type epitaxial layer 9, n ^- resistance type epitaxial layer 9 is reduced. In this embodiment, the distance D between the embedded gate electrodes is relatively small, and the lateral length L of the embedded gate electrode is relatively large. Therefore, the density of electrons gathering in the n ⁻ -type epitaxial layer 9 near the buried gate electrode becomes higher than that in the case of the IGBT. Therefore, the resistance of n ⁻ type epitaxial layer 9 further decreases. According to the above (1), (2) and (3), the IEGT1
Is turned on, and the p ⁺ -type collector layer 5 to the n ⁺ -type emitter layer 3
A current flows through 5, 37.

[Description of Manufacturing Method] A manufacturing method of a vertical semiconductor device according to an embodiment of the present invention will be described. As shown in FIG. 2, a structure in which ap ⁺ -type collector layer 5, an n ⁺ -type buffer layer 7, and an n ^-- type epitaxial layer 9 are sequentially stacked is prepared. The crystal plane of main surface 10 of n ⁻ -type epitaxial layer 9 is (100). In this embodiment, single crystal silicon is used as the material of the n ⁻ -type epitaxial layer 9.

A silicon oxide film 12 having a thickness of 0.05 to 0.2 μm is formed on main surface 10. The silicon oxide film 12 becomes the first gate oxide film 25. The silicon oxide film 12 is an example of a first insulating film. Examples of a method for forming the silicon oxide film 12 include a CVD method and a thermal oxidation method. Since the silicon oxide film 12 becomes the first gate oxide film 25, a thermal oxidation method is preferable.

As shown in FIG. 3, the silicon oxide film 12 is patterned by, for example, a photolithography technique and an etching technique to form a first gate oxide film 25. There is an opening 41 exposing main surface 10 between first gate oxide films 25. The main surface 10 exposed at the opening 41 becomes a seed crystal part. Opening 41
Has a horizontal length d ₁ of 3 μm or less. The lateral length d ₂ of the first gate oxide film 25 is 3 μm or more.

As shown in FIG. 4, an amorphous silicon layer 43 having a thickness of 2 to 3 μm doped with an n-type impurity, for example, phosphorus is formed. The amorphous silicon layer 43 is the seventh
FIG. As a method for forming the amorphous silicon layer 43, for example, there is a CVD method.

As shown in FIG. 5, the amorphous silicon layer 43 is monocrystallized by solid phase epitaxial growth into a single crystal silicon layer 45 using the main surface 10 exposed at the opening 41 as a seed crystal part. . Single crystal silicon layer 4
5 is an example of a third layer. The temperature condition for the solid phase epitaxial growth is 550 to 620 ° C. In addition, in order to improve the film quality of the single crystal silicon layer 45, 900 to 1000 ° C.
Heat treatment.

As shown in FIG. 6, the single-crystal silicon layer 45 is patterned by, for example, a photolithography technique and an etching technique to
13, 15, and 17 are formed. Buried gate electrode 11
A trench 47 is formed between the gate electrode 13 and the buried gate electrode 13. A trench 49 is formed between the buried gate electrode 13 and the buried gate electrode 15.
A trench 51 is formed between the buried gate electrode 15 and the buried gate electrode 17.

As shown in FIG. 7, the second gate oxide films 27, 29 (thickness: 0.05 to 0.2) are formed on the side surfaces of the buried gate electrodes 11, 13, 15, 17 by thermal oxidation, for example.
μm). By this thermal oxidation, the silicon oxide film 3 is formed on the upper surfaces of the buried gate electrodes 11, 13, 15, and 17.
1 (thickness: 0.05 to 0.2 μm) is formed. Further, silicon oxide film 53 is also formed on main surface 10 exposed at opening 41.

As shown in FIG. 8, the silicon oxide film 53 is removed by, for example, a photolithography technique and an etching technique to expose the main surface 10 in the opening 41.

As shown in FIG. 9, an amorphous silicon layer 55 having a thickness of 2 to 3 μm is formed. Thereby, the trench 4
7, 49, and 51 are buried with an amorphous silicon layer 55. The amorphous silicon layer 55 is an example of a sixth layer. As a method for forming the amorphous silicon layer 55, for example, there is a CVD method.

As shown in FIG. 10, the amorphous silicon layer 55 is monocrystallized by solid phase epitaxial growth into a single crystal silicon layer 57 using the main surface 10 exposed at the opening 41 as a seed crystal part. . Single crystal silicon layer 5
7 is an example of a fourth layer. The temperature condition for the solid phase epitaxial growth is 550 to 620 ° C. Since the single crystallization in the vertical direction is easy to proceed, the amorphous silicon layer 55 in the trenches 47, 49, and 51 is all monocrystallized. In addition,
900 to 100 to improve the film quality of the single crystal silicon layer 57
A heat treatment at 0 ° C. was performed.

As shown in FIG. 11, the single crystal silicon layer 5
7 is etched back to expose the silicon oxide film 31. Note that a line indicating the main surface 10 in the opening 41 will be omitted hereinafter.

As shown in FIG. 12, boron as a p-type impurity is ion-implanted into the single crystal silicon layer 57. Then, boron is thermally diffused at about 1100 ° C. As a result, the p-type base layers 19, 21 and 23 are formed in the single-crystal silicon layer 57.

As shown in FIG. 13, the p-type base layer 19,
Using a resist that partially exposes 21 and 23 as a mask, phosphorus or arsenic that is an n-type impurity is
Ions are implanted into 9, 21, and 23. Then, the n-type impurity is thermally diffused at about 900 ° C. Thus, the n ⁺ -type emitter layers 35 and 37 are formed in the p-type base layers 19, 21, and 23.

As shown in FIG. 14, a silicon oxide film 33 having a thickness of 0.5 to 1.0 μm is formed by, for example, a CVD method so as to cover the buried gate electrodes 11, 13, 15, and 17. For example, the silicon oxide film 33 is selectively removed by a photolithography technique and an etching technique to expose a part of the n ⁺ -type emitter layers 35 and 37.

As shown in FIG. 15, an emitter electrode 39 made of Al containing Si is formed by, for example, a sputtering method. The emitter electrode 39 is a p-type base layer 1
9, 21, and 23 are electrically connected to the n ⁺ -type emitter layers 35 and 37. Further, for example, the collector electrode 3 made of Ti-Ni-Au is formed by an electron beam evaporation method. Through the above steps, IEGT1 is completed.

[Explanation of Effects] (Effect 1) In the method of manufacturing a vertical semiconductor device according to the present embodiment, a buried gate electrode is not formed in a trench. As shown in FIGS. 5 and 6, first, the single-crystal silicon layer 45 is selectively removed by etching.
Buried gate electrodes 11, 13, 15, and 17 are formed. Then, as shown in FIG. 10, a single-crystal silicon layer 57 is formed between the buried gate electrodes. Therefore,
A structure in which the distance between the buried gate electrodes is reduced and the lateral length of the buried gate electrodes is increased without reducing the area efficiency. Therefore, it is possible to reduce the ON voltage of the IEGT without reducing the area efficiency.

(Effect 2) In the method of manufacturing a vertical semiconductor device according to the present embodiment, the embedded gate electrodes 11, 13, 15, and 17 are formed of a single-crystal silicon layer by the steps shown in FIGS. You. As shown in FIG. 7, by thermal oxidation,
The second gate oxide films 27 and 29 serve as the buried gate electrode 1.
1, 13, 15, and 17 are formed on the side surfaces. in this case,
The breakdown voltage of the second gate oxide film is higher when the layer forming the buried gate electrode is single crystal than when it is polycrystalline. For example, the dielectric breakdown electric field of a silicon oxide film formed on a single crystal silicon layer by thermal oxidation is 8 to 10 MV / c.
m. On the other hand, the dielectric breakdown electric field of the silicon oxide film formed on the polycrystalline silicon layer by thermal oxidation is 1-2 MV /
cm. The higher the breakdown electric field, the higher the breakdown voltage of the silicon oxide film. Therefore, a silicon oxide film formed over a single crystal silicon layer can be said to be a more preferable gate insulating film.

(Effect 3) By the steps shown in FIGS.
The amorphous silicon layer 43 is turned into a single crystal silicon layer 45 by solid phase growth using the surface 10 as a seed crystal part. At this time, the amorphous silicon layer 43 located at the position corresponding to the central portion 59 of the embedded gate electrode may become a polycrystalline silicon layer. This is because single crystallization hardly proceeds in the lateral direction. Therefore, there is a possibility that a problem may occur in the film quality of the silicon oxide film 31 formed on the upper surfaces of the buried gate electrodes 11, 13, 15, and 17 due to thermal oxidation in the step shown in FIG. That is, as described above, the region located on the central portion of the buried gate electrodes 11, 13, 15, 17 on the upper surface of the buried gate electrodes 11, 13, 15, 17 may become a polycrystalline layer. is there. The withstand voltage of the silicon oxide film formed on the polycrystalline layer is smaller than the withstand voltage of the silicon oxide film formed on the single crystal layer.

As shown in FIG. 14, the vertical semiconductor device according to the present embodiment includes the silicon oxide film 33 located on the silicon oxide film 31, so that even if the withstand voltage of the silicon oxide film 31 is low, The presence of the silicon oxide film 33 makes it possible to maintain a predetermined breakdown voltage.

[Explanation of Modification] (Modification 1) As shown in FIG. 7, in this embodiment, the silicon oxide films 25, 27 and 29 are used as gate oxide films. However, the present invention is not limited to this, and an insulating film including a silicon nitride film and a silicon oxide film formed therearound may be used instead of the silicon oxide films 25, 27, and 29. According to this, the dielectric constant of the gate insulating film is higher than in the case of using only the silicon oxide film. Therefore, the threshold voltage of the vertical semiconductor element can be reduced without lowering the breakdown voltage of the gate insulating film. Thereby, the loss of the vertical semiconductor element can be reduced.

(Modification 2) As shown in FIG. 4, in the present embodiment, when the amorphous silicon layer 43 is formed,
The amorphous silicon layer 43 is doped with an n-type impurity. However, the present invention is not limited to this. After the amorphous silicon layer 43 is formed, the amorphous silicon layer 43 may be doped by diffusion including ion implantation.

After the formation of the silicon single crystal layer 45 shown in FIG. 5, the silicon single crystal layer 45 may be doped by diffusion including ion implantation. According to this, at the time of single crystallization of silicon, the influence of impurities can be avoided.

(Modification 3) As shown in FIGS. 4 and 5, in the present embodiment, first, an amorphous silicon layer 43 is formed,
The amorphous silicon layer 43 is turned into a single crystal silicon layer 45 by solid phase epitaxial growth. However, the present invention is not limited to this, and the single crystal silicon layer 45 may be directly formed. When the amorphous silicon layer is changed to a single crystal silicon layer, a volume change occurs. This generates stress. According to this modification, this can be avoided.

(Modification 4) As shown in FIG. 6, in the present embodiment, buried gate electrodes 11, 13, 15, and 17 are provided.
Is composed of a single crystal silicon layer. However, the present invention is not limited to this. After the step shown in FIG. 2, a polycrystalline silicon layer is formed on the silicon oxide film 12 and the polycrystalline silicon layer is patterned to form the buried gate electrodes 11 and 13. , 15, 17 may be formed.

(Modification 5) In this embodiment, the single-crystal silicon layer 57 is formed between the buried gate electrodes by the steps shown in FIGS. However, the present invention is not limited to this. After the step of FIG. 8, the single crystal silicon layer 5 is formed between the buried gate electrodes by selective epitaxial growth.
7 may be formed.

(Modification 6) In this embodiment, the single-crystal silicon layer 57 is formed between the buried gate electrodes by the steps shown in FIGS. However, the present invention is not limited to this, and after the step of FIG.
Is etched back to expose the silicon oxide film 31.
After that, the amorphous silicon layer 55 may be changed to the single crystal silicon layer 57 by solid phase epitaxial growth.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of one embodiment of a vertical semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a first manufacturing step of one embodiment of the vertical semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing a second manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing a third manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a fourth manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 6 is a sectional view showing a fifth manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 7 is a sectional view showing a sixth manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view showing a seventh manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 9 is a sectional view showing an eighth manufacturing step of the vertical semiconductor device according to one embodiment of the present invention;

FIG. 10 is a sectional view showing a ninth manufacturing step of the vertical semiconductor device according to one embodiment of the present invention;

FIG. 11 is a sectional view showing a tenth manufacturing step of the vertical semiconductor device according to one embodiment of the present invention;

FIG. 12 is a cross-sectional view showing an eleventh manufacturing step of one embodiment of the vertical semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view showing a twelfth manufacturing step of one embodiment of the vertical semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view showing a thirteenth manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 15 is a cross-sectional view showing a fourteenth manufacturing step of the embodiment of the vertical semiconductor device according to the present invention.

FIG. 16 is a cross-sectional view of an example of an IGBT.

FIG. 17 is a three-dimensional sectional view of an example of the IEGT.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 IEGT 3 collector electrode 5 p ⁺ -type collector layer 7 n ⁺ -type buffer layer 9 n ^-- type epitaxial layer 10 main surface 11 buried gate electrode 12 silicon oxide film 13 buried gate electrode 15 buried gate electrode 17 buried gate electrode 19 p-type base Layer 21 p-type base layer 23 p-type base layer 25 first gate oxide film 27 second gate oxide film 29 second gate oxide film 31 silicon oxide film 33 silicon oxide film 35 emitter layer 37 emitter layer 39 emitter electrode 41 Opening 43 Amorphous silicon layer 45 Single crystal silicon layer 47 Trench 49 Trench 51 Trench 53 Silicon oxide film 55 Amorphous silicon layer 57 Single crystal silicon layer 59 Central part

Claims (8)

[Claims] 1. A method of manufacturing a vertical semiconductor device in which a base layer of a first conductivity type is formed between buried gate electrodes, comprising: (a) a first layer of a first conductivity type and a second layer; A step of forming a first insulating film to be a first gate insulating film on the second layer in the stacked structure including the second layer having the conductivity type of (b); Forming a third layer on the first insulating film, and (c) selectively removing the third layer by etching so that the buried gate electrode is formed on the first insulating film. (D) forming a second gate insulating film on the side surface of the buried gate electrode; and (e) forming a fourth layer including a first single crystal layer into the buried gate. Forming between the electrodes; and (f) forming the base layer in the fourth layer. And (g) forming a fifth layer of a second conductivity type in the base layer. 2. The method according to claim 1, wherein the step (e) comprises exposing a sixth layer including a first amorphous layer between the buried gate electrodes and exposing the second layer. A method of manufacturing a vertical semiconductor device, comprising: a step of forming the fourth layer; and a step of single-crystallizing the sixth layer by solid phase epitaxial growth to form the fourth layer. 3. The method according to claim 1, wherein between the step (a) and the step (b), (h) the first insulating film below a formation region of the buried gate electrode is left; and Removing the first insulating film under the formation region of the base layer to form an opening exposing the second layer.
A method for manufacturing a vertical semiconductor device. 4. The method according to claim 1, wherein, in the step (d), a second insulating film is formed on an upper surface of the buried gate electrode. 3. A method for manufacturing a vertical semiconductor device, comprising a step of forming an insulating film of No. 3 on the second insulating film. 5. The vertical semiconductor device according to claim 1, wherein in the step (c), a length of the buried gate electrode in a horizontal direction is larger than a distance between the buried gate electrodes. Manufacturing method. 6. A first layer of a first conductivity type, a second layer of a second conductivity type located on the first layer, and a first layer located on the second layer. A gate insulating film; a buried gate electrode located on the first gate insulating film and including a second single crystal layer; a second gate insulating film located on a side surface of the buried gate electrode; A base layer of a first conductivity type located between the electrodes, and a fifth layer of a second conductivity type located in the base layer, wherein the embedded gate electrode has a lateral length of A vertical semiconductor device having a distance greater than the distance between the buried gate electrodes. 7. The vertical semiconductor device according to claim 6, wherein a side portion of the buried gate electrode is the second single crystal layer. 8. The semiconductor device according to claim 6, further comprising: a second insulating film in contact with an upper surface of the buried gate electrode; and a third insulating film located on the second insulating film. , Vertical semiconductor device.