JP2000260782A - High frequency integrated circuit - Google Patents

Abstract

(57) Abstract: A high-frequency integrated circuit that has high driving capability per unit area and can be miniaturized by configuring a switch circuit using a bidirectional heterojunction bipolar transistor as a switching element. SOLUTION: An n-type G is formed on a semi-insulating GaAs substrate 10.
An aAs sub-collector layer 11 is formed, and an n-type AlGaAs collector layer 12 and a p-type Ga
As base layer 13, n-type AlGaAs emitter layer 14,
An n-type GaAs emitter contact layer 15 and the like are stacked in a mesa shape. The base-emitter junction is a heterojunction, and the base-collector junction is also a heterojunction. Further, each parameter is designed so that the transistor characteristics are the same between the forward operation and the reverse operation. The circuit is configured so that the transistor is saturated by the base potential and a signal is transmitted between the emitter and the collector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high frequency integrated circuit using a heterojunction bipolar transistor (HBT) as a high frequency switching element.

[0002]

2. Description of the Related Art In mobile communication devices such as cellular phones, G
In many cases, microwaves in the Hz band are used. Therefore, for example, as shown in FIG.
Is used for a switching circuit for switching between a case where the signal is connected to the receiving circuit Rx and a case where the signal is connected to the transmitting circuit Tx.
The high-frequency switching element 1 that handles a relatively high output becomes indispensable (for example, Japanese Patent Application Laid-Open No. 9-181624). Conventionally,
In this field, gallium arsenide (GaAs) replaces silicon.
In many cases, a field effect transistor (FET) using s) is used, and accordingly, a monolithic microwave integrated circuit (MMIC) in which GaAs FETs are integrated is being developed.

FIG. 5 is a sectional view of a GaAs FET used as the high-frequency switching element 1. In this device, n + layers 3 and 4 for source / drain, a p− layer 5 for back gate and an n layer 6 for channel are provided on a surface of a semi-insulating GaAs substrate 2, and an n layer 6 for a channel is provided on the surface of the n layer 6. This is a structure in which a gate electrode 7 is arranged. A normally-on type in which a depletion layer is expanded inside the n-layer 6 by applying a voltage to the gate electrode 7, thereby controlling a source / drain current flowing between the n + layer 3 and the n + layer 4. Element.

The high-frequency switching element 1 shown in FIG. 4 switches a large power of, for example, about 1 W, particularly during transmission. For this reason, the current capacity is increased by expanding the gate width W, for example, by forming the gate electrode 7 of the transistor in a comb shape and extending it to a long length.

[0005]

SUMMARY OF THE INVENTION The above GaAs FET
Are the source and the source in the horizontal direction with respect to the surface of the
Since the element is a lateral element in which a drain current flows, the current capacity per unit area is small. Therefore, there is a disadvantage that the chip size is increased by expanding the gate width W.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has a connection point to an antenna, a first switch element for connecting the connection point to an internal circuit at the time of reception, and a transmission element. A high frequency integrated circuit including a second switch element for connecting the connection portion and an internal circuit,
The first and second switch elements are heterojunction bipolar transistors each having a base, an emitter, and a collector layer, and have bidirectional symmetric heterobipolar transistors having the same operation characteristics in forward operation and reverse operation. Is used.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a bidirectional symmetric heterojunction bipolar transistor (HBT). H
The BT has an emitter / base junction of AlGaAs or G
By using a junction made of a different material such as aInP / GaAs, the electron mobility is high and the band gap of the emitter is larger than the band gap of the base, so that the electron injection efficiency can be increased. For this reason, the element can easily obtain a high output characteristic of about 1 to 2 W in the GHz band.

Referring to FIG. 1, an n-type GaAs subcollector layer 11 is formed on a semi-insulating GaAs substrate 10,
On the sub-collector layer 11, an n-type AlGaAs collector layer 12, a p-type GaAs base layer 13, an n-type AlGaAs emitter layer 14, an n-type GaAs emitter contact layer 15
Are stacked in a mesa shape.

The sub-collector layer 11 is formed on the substrate 10 by an epitaxial growth method, and has a thickness of 3 to 6E18 at.
oms · cm−3 silicon (S
i) A doped N-type GaAs layer. Its thickness is 7000-8000 °. The collector layer 12 is an N-type AlGaAs layer which is formed on a partial region of the sub-collector layer 11 and is doped to a concentration of about 3 to 5E17 atoms · cm −3 by silicon doping.
The thickness is 1000-2000 °. The base layer 13
This is a P-type GaAs layer formed on the collector layer 12 and doped with carbon (C) to an impurity concentration of about 1 to 3E19 atoms / cm-3. The thickness is 1000-2000 °. The emitter layer 14 is an N-type AlGaAs layer formed on a partial region of the base layer 13 and doped with silicon to an impurity concentration of about 3 to 5E17 atoms · cm −3. The thickness is 1000-2000 °. Emitter contact layer 1
Reference numeral 5 denotes an N-type AlGaAs layer formed on the emitter layer 14 and doped by silicon doping with an impurity concentration of about 3 to 6E18 atoms · cm−3. The thickness is 2000-3000 °.

On the surface of the sub-collector layer 11, a collector electrode 16 made of an AuGe / Ni / Au layer is arranged at a position sandwiching the collector layer 12. On the surface of the base layer 13, the AuGe / N
A base electrode 17 made of an i / Au layer is arranged. An emitter electrode 18 also made of an AuGe / Ni / Au layer is arranged above the emitter layer 15.

In this transistor, the emitter layer 14 and the base layer 13 form an AlGaAs / GaAs heterojunction, and the collector layer 12 and the base layer 1
3 is characterized by forming an AlGaAs / GaAs heterojunction. Then, during the forward operation in which the emitter layer 14 operates as the emitter,
Each parameter is controlled so that the transistor characteristics are substantially the same as in the reverse operation in which the transistor 4 operates as a collector. Specifically, the current transfer rate β is configured to be the same between the forward operation and the reverse operation, and in order to realize this, first, the impurity concentration of the emitter layer 14 and the collector layer 12 Are set to substantially equal values. It is also relatively important that the emitter layer 14, the base layer 13, and the collector layer 12 each have a uniform impurity concentration distribution in the thickness direction. When the base bias is applied, the operating current flows from the collector electrode 16 to the sub-collector layer 1 during the forward operation.
1, collector layer 12, base layer 13, emitter layer 14,
It flows to the emitter electrode via the emitter contact layer 15 in this order. That is, the operating current flows in a direction perpendicular to the substrate 10. The maximum current value is determined mainly by the area of the emitter layer 14 and is a bipolar operation in which conductivity modulation is performed.
It has ten times the current driving capability. It should be noted that, as a heterojunction, instead of an AlGaAs / GaAs junction, G
An aInP / GaAs junction may be used.

The emitter layer 14, the berth layer 13, and the collector layer 12 having the mesa structure formed on the subcollector layer 11 are used as one unit transistor, and a large number of the unit transistors are arranged on the common subcollector layer 11. ,
Each of these electrodes 16, 17 and 1 having these extended in a comb shape
8 to form a single high-power high-frequency switching element. A large number of such high-frequency switching elements are formed on a common substrate 10 (chip), and elements such as resistance elements are formed. These elements are connected to, for example, a circuit configuration shown in FIG. hand,
Configure the MMIC.

FIG. 2A shows an example of a switch circuit using the HBT element of FIG. 1 as a switching element. This circuit includes a first switch transistor 20 having an emitter connected to the antenna ANT, and a second switch transistor 21 having a collector connected to the antenna ANT, and the collector of the first switch transistor 20 is used for transmission. The emitter of the second switch transistor 21 is connected to the receiver circuit Rx, and the bases of the transistors 20 and 21 are connected via the resistor 22 to the reception control signal CtrlRx and the transmission control circuit C.
It has a configuration connected to each of trlTx. Reception control signal CtrlRx and transmission control circuit CtrlTx
Are signals complementary to each other, and the control signal for reception Ctrl
When Rx is at the H level (for example, 3 V), the transmission control signal C
trlTx becomes L level (for example, 0 V). Now, when the reception control signal CtrlRx is at the H level, the first switch transistor 20 is turned on and the second switch transistor 21 is turned off, and the high-frequency signal applied to the antenna ANT is transferred to the reception-side circuit Rx. On the other hand, when the transmission control signal CtrlTx is at the H level, the first switch transistor 20 is turned off and the second switch transistor 21 is turned on, and a high-frequency signal is applied from the transmission side circuit Tx to the antenna ANT.

In this switch circuit, while the emitter potential (potential of the antenna ANT) fluctuates depending on the potential of a signal at the time of reception / transmission, the base potential Vb is fixed to fix the first and second switch transistors 20 and 20. 21 is operated in full saturation. FIG. 2B shows the characteristic diagram. The transmission of the high-frequency signal 22 is performed in a linear region (Vr to Vp) in which the base-emitter potential VBE changes from the positive side (+) to the negative side (-). The region on the negative side (-) indicates a reverse operation in which the emitter region 14 operates as a collector. At this time, by matching the characteristics of the positive side (+) and the characteristics of the negative side (−) transistor, the linear characteristics are improved, and high-frequency signals can be transmitted without transmission distortion.

FIG. 3 shows a second example of the switch circuit.
This circuit comprises first and second switch transistors 20,
21 are cascade-connected to each other by connecting a plurality of emitters and corrects. By connecting the transistors in cascade, the linear region (Vr-Vp) in FIG. 2B is expanded, and the maximum amplitude of the high-frequency signal 22 can be expanded. Other switching operations are the same as those in FIG.

[0017]

As described above, the HBT element allows a current to flow in the vertical direction with respect to the substrate 10 and has a current driving capability 5 to 10 times that of the horizontal GaAs FET element. This has the advantage that the occupied area can be reduced and the chip size of the MMIC can be reduced. In addition, by equalizing the transistor characteristics during forward operation and reverse operation of the transistor, there is an advantage that the switching element can be configured to suppress distortion of the transmitted waveform.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIGS. 2A and 2B are circuit diagrams for explaining the present invention; FIGS.
It is a characteristic diagram.

FIG. 3 is a circuit diagram for explaining the present invention.

FIG. 4 is a circuit diagram for explaining a conventional example.

FIG. 5 is a cross-sectional view for explaining a conventional example.

Claims (7)

[Claims] 1. A connection point to an antenna, a first switch element for connecting the connection point and an internal circuit at the time of reception,
What is claimed is: 1. A high-frequency integrated circuit comprising: a second switch element for connecting said connection point and an internal circuit during transmission; wherein said first and second switch elements are a heterojunction type having a base, an emitter, and a collector layer. A high-frequency transistor characterized in that a current transfer rate is substantially equal between a forward operation when the emitter layer operates as an emitter and a reverse operation when the emitter operates as a collector when the emitter layer operates as an emitter. Integrated circuit. 2. A connection point to an antenna, a first switch element for connecting the connection point and an internal circuit during reception,
What is claimed is: 1. A high-frequency integrated circuit comprising: a second switch element for connecting said connection point and an internal circuit during transmission; wherein said first and second switch elements are a heterojunction type having a base, an emitter, and a collector layer. A high frequency integrated circuit, which is a bipolar transistor, wherein the emitter layer and the collector layer have substantially the same impurity concentration. 3. A connection point to an antenna, a first switch element connecting the connection point and an internal circuit during reception,
What is claimed is: 1. A high-frequency integrated circuit comprising: a second switch element for connecting said connection portion and an internal circuit during transmission; wherein said first and second switch elements are a heterojunction type having a base, an emitter, and a collector region. A bipolar transistor, wherein the hetero-junction bipolar transistor is a one-conductivity type sub-collector layer formed on a semi-insulating semiconductor substrate; a one-conductivity type collector layer formed on the sub-collector layer; A base layer of the opposite conductivity type formed on the collector layer, an emitter layer of one conductivity type formed on the base layer, and an emitter contact layer of one conductivity type formed on the emitter layer were laminated. A high-frequency integrated circuit having a structure, wherein a current flows in a vertical direction from the emitter contact layer to the subcollector layer. 4. The method according to claim 1, wherein the emitter layer and the collector layer
4. The high frequency integrated circuit according to claim 3, wherein the high frequency integrated circuit is an lGaAs layer. 5. The method according to claim 1, wherein the emitter layer and the collector layer
4. The high-frequency integrated circuit according to claim 3, wherein the high-frequency integrated circuit is an aInP layer. 6. The high frequency integrated circuit according to claim 3, wherein said emitter layer and said collector layer have the same impurity concentration. 7. The high frequency integrated circuit according to claim 3, wherein an impurity concentration distribution of said base layer is uniform in a film thickness direction.