JP2000260772A - Semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To reduce a chip area, prevent a contact failure between a pad and an evaluation device in an inspection process, and electrically connect a front surface side conductor to a back surface pad in an integrated circuit forming process. To provide a technology that can easily create a means for connecting to a computer. SOLUTION: An Al wiring (first conductor) 4 formed on a surface side of a semiconductor substrate 10 and electrically connected to an integrated circuit.
0 and an N + layer (high impurity concentration added layer) 1 formed inside the semiconductor substrate 10 and electrically connected to the Al wiring (first conductor) 40 and highly doped with N-type impurities.
4, 26 and 28, and formed on the back side of the substrate 10,
An Al wiring (second conductor) 41 electrically connected to the N + layers (high impurity concentration added layers) 14, 26 and 28;
Al wiring (second conductor) formed on the back surface of substrate 10
And a pad 42 that is electrically connected to the pad 41.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device provided with test pads and bonding pads on the back surface.

[0002]

2. Description of the Related Art FIG. 16 is a cross-sectional view for explaining an inspection of a conventional semiconductor integrated circuit device using a die sorter inspection needle (D / S needle). Conventional semiconductor integrated circuit device 50
Since the integrated circuit and the pad 52 are arranged on the same surface of the semiconductor substrate 50, the pad 5
Two areas were needed. For this reason, the pad area must be reduced in order not to increase the chip area.

[0003]

However, in the conventional semiconductor integrated circuit 50, if the area of the pad 52 is too small, a problem such as a contact failure occurs in a die sorter inspection process using the D / S needle 54. .

[0004]

In order to solve the above-mentioned problems, a feature of the present invention is to provide a semiconductor integrated circuit device in which an integrated circuit is formed on a semiconductor substrate, wherein the integrated circuit is formed on the front side of the semiconductor substrate. A first conductor electrically connected to the semiconductor substrate, and at least one N-type or P-type impurity doped at a high concentration formed inside the semiconductor substrate and electrically connected to the first conductor; An impurity-doped layer, a second conductor formed on the back surface of the substrate and electrically connected to the impurity-doped layer, and a second conductor formed on the back surface of the substrate and electrically connected to the second conductor; And a pad to be connected.

[0005] Here, the "semiconductor" includes silicon, germanium, gallium arsenide, gallium phosphorus, indium antimony and the like. The “conductor” includes aluminum, copper, polysilicon, and the like. Further, “N-type impurities” include phosphorus, arsenic, antimony, and the like, and “P-type impurities” include boron, indium, and the like.

According to the above configuration, the pads can be provided on the back surface of the chip instead of the front surface of the chip, so that the chip area can be reduced and the degree of integration can be improved. In addition, by providing the pads on the back surface of the chip, the pad area can be increased, so that a contact failure between the pads and the evaluation device in the inspection process can be prevented.

Further, after forming an integrated circuit, a hole is formed in the substrate by physical or etching, and a conductive material is filled in the hole. Since the structure is such that a high-concentration impurity-doped layer for electrically connecting the surface conductor to the back surface pad is formed in the formation process, the formation is easy.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 13 are cross-sectional views showing respective steps in a process of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 14 is a sectional view of the semiconductor integrated circuit device according to the present embodiment. FIG. 15 is a perspective view of the semiconductor integrated circuit device shown in FIG. In the drawings, the same reference numerals indicate the same or corresponding parts.

As shown in FIG. 14, a semiconductor integrated circuit device according to the present embodiment is a semiconductor integrated circuit device in which an integrated circuit is formed on a semiconductor substrate 10.
Al formed on the front surface side and electrically connected to the integrated circuit
A wiring (first conductor) 40 and an N + layer formed inside the semiconductor substrate 10 and electrically connected to the Al wiring (first conductor) 40 and highly doped with an N-type impurity; (High impurity concentration added layer) 14, 26 and 28 and substrate 10
N + layer (high impurity concentration added layer) 1
An Al wiring (second conductor) 41 that is electrically connected to 4, 26, and 28;
And a pad 42 electrically connected to the wiring (second conductor) 41.

The “front side” of the semiconductor substrate 10 is
The “back side” of the semiconductor substrate 10 means the side opposite to the side on which the integrated circuit is formed. Further, “formed inside the semiconductor substrate 10” does not mean that “only formed” inside the semiconductor substrate 10, but also includes a case formed inside the semiconductor substrate 10 and the N layer 16.

The manufacturing process of the apparatus will be described below in the order of steps. FIG. 1 shows a cross-sectional view of a silicon wafer 10. The silicon wafer 10 is placed in a high-temperature atmosphere, and SiO ₂ oxide films 12 and 13 are grown on the front and back surfaces of the wafer 10 (FIG. 2). Next, buried patterning is performed,
An N + buried region is formed in the SiO ₂ oxide film 12 (FIG. 3). Next, thermal diffusion of arsenic or antimony impurities is performed to form an N + buried layer 14 in the buried region patterned in FIG. 3 (FIG. 4).

Next, the SiO ₂ oxide film 1 on the entire surface of the wafer 10
2 was peeled off, it is grown an N layer 16, further after growing an SiO ₂ oxide film 18 is removed SiO ₂ oxide film 18 of the isolation region buried patterning a similar manner. Thereafter, the entire surface of the wafer 10 is covered with boron silicate glass (BS).
G) is grown at a low temperature in a vapor phase to form a BSG film 20 (FIG. 5).

Next, N layer islands 22 are formed by thermal diffusion of boron.
After the SiO ₂ oxide film 18 and the BSG film 20 are peeled off, an oxide film 24 is grown. And the oxide film 2
4 is removed to form an N + buried region (FIG. 6). Next, thermal diffusion of arsenic or antimony is performed to make N +
A layer 26 is formed (FIG. 7).

The same operation as that described with reference to FIGS. 6 and 7 is performed on the back surface of the wafer 10 to form the N + layer 28 (FIG. 8).

The SiO ₂ oxide film 24 extends from the surface of the wafer 10.
Is stripped, a SiO ₂ oxide film 30 is grown, and after patterning the base, a BSG film 32 is formed, and thermal diffusion of boron is performed to form a P layer 34 (FIG. 9).

After removing the SiO ₂ oxide film 30 and the BSG film 32 in the emitter region by emitter patterning,
Phosphorus / arsenic / silicate glass (P · AsSG) is vapor-phase grown to form a P · AsSG film 36. Thermal diffusion of phosphorus and arsenic into the patterned emitter region,
An N + layer 38 is formed (FIG. 10).

Contact patterning is performed to form an oxide film 30, a BSG film 32, and a P.AsSG film 3 in a contact region.
6 is removed. S of the contact area on the back surface of the wafer 10
The iO ₂ oxide film 13 is also removed (FIG. 11).

Aluminum is deposited and etched on the front and back surfaces of the wafer 10 to form wirings 40 and 41 (FIG. 12). Next, bonding pads 42 are provided on the back surface of the wafer 10 (FIG. 13). Finally, a vapor phase growth of phosphorus silicate glass (PSG) is performed, and a PSG film 44 is formed.
To form The PSG film 44 is provided as a protective film (FIG.
4). Thereby, the semiconductor integrated circuit device of the present embodiment is obtained.

FIG. 15 is a perspective view of the back surface of the semiconductor integrated circuit device of this embodiment. By providing the pads 42 on the back surface of the chip as shown in the figure, the chip area can be reduced and the degree of integration can be improved. In addition, since the pad area can be increased, the contact with the evaluation device in the wafer inspection process can be changed from point contact to surface contact, and the problem of poor contact can be avoided. Furthermore, the formation of the N + layers 14, 26 and 28 facilitates the manufacture of the means for connecting the integrated circuit to the pad 42.

[0020]

As described above, according to the present invention,
By providing the pads on the back surface instead of the front surface of the semiconductor integrated circuit device, it is possible to reduce the area of the semiconductor integrated circuit device and improve the degree of integration. In addition, since the pad area can be increased by providing the pad on the back surface, a contact failure with the evaluation device in the inspection process can be prevented. Further, since the structure is such that a means for connecting the front side integrated circuit and the back surface pad is formed in the process of manufacturing the semiconductor integrated circuit, for example, a hole penetrating from the front surface to the back surface after the manufacture of the semiconductor integrated circuit device is formed, It is easier to manufacture than a structure in which a means for connecting the front side integrated circuit and the back surface pad is formed by filling a conductive material into the substrate.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 5 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 6 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 7 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 8 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 9 is a sectional view for explaining the method of manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 10 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 11 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 12 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 13 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 14 is a sectional view for explaining the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 15 is a perspective view illustrating a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 16 is a cross-sectional view for explaining an inspection using a D / S needle of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

10 ... silicon wafer (substrate) 12, 13 ... SiO ₂ oxide film 14,26,28 ... N + layer (impurity heavily-doped layer) 40, 41 ... Al wiring (first, second conductor) 42, 52 ... pad

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference)

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which an integrated circuit is formed on a semiconductor substrate, a first conductor formed on a surface side of the semiconductor substrate and electrically connected to the integrated circuit; At least one heavily doped N-type or P-type impurity layer formed therein and electrically connected to the first conductor, and formed on a rear surface side of the substrate; A second conductor electrically connected to the impurity-doped layer, and a pad formed on the back surface of the substrate and electrically connected to the second conductor. A semiconductor integrated circuit device characterized by the above-mentioned.