JP2000260191A - Method of writing and erasing data in semiconductor memory - Google Patents

Abstract

[PROBLEMS] To provide a method of writing and erasing data in a semiconductor memory, which can effectively reduce the total time required for writing data to the semiconductor memory. A method for writing and erasing data in an electrically writable and erasable nonvolatile semiconductor memory includes:
An initial pulse is given at the first time of the write process, and an additional pulse is given at the second and subsequent write processes, and the pulse is continuously applied until the write determination voltage level is reached. A writing and erasing method for controlling the pulse width given to the next memory cell later according to the number of times of writing. In writing to the next cell, the number of times of writing is counted and measured for pulse width correction. The additional pulse is also corrected for the memory cell according to the number of times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for writing and erasing data in a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory device (Electric) capable of electrically writing and erasing.
The present invention relates to a method for writing and erasing data to an ally erasable programmable ROM (EEPROM) and a flash type (batch erase type) EEPROM.

[0002]

2. Description of the Related Art Basic write control in a method of writing data to a nonvolatile memory will be described below with reference to the drawings. FIG. 3 is a block diagram showing an example of a general device for writing data to a nonvolatile memory, FIG. 4 is a flowchart of a data writing procedure in the device shown in FIG. 3, and FIG. 5 is a write time and write voltage in the device shown in FIG. FIG. 6 is a graph showing the relationship between levels, FIG. 6 is a graph showing the write time characteristics of each memory cell of the nonvolatile memory chip, and FIG. 7 is a graph showing the write time characteristics of each nonvolatile memory chip.

In FIG. 3, 1 is a write / erase pulse width setting circuit, 2 is a write / erase pulse generation circuit, 3 is a memory cell, and 4 is a verify circuit. The procedure of writing data to the memory cell 3 is as follows. After the start of the operation, the write / erase pulse width setting circuit 1 sets the write pulse width given to the memory cell 3 to the write / erase pulse generator 2, and the write / erase pulse generator 2 gives the write pulse to the memory cell 3. Thereafter, the verify circuit 4 determines whether or not the data has reached the write / erase level, and if the data has not reached the write / erase voltage level, repeats the write / erase operation again. Only when the verify circuit 4 reaches the write level, the write / erase operation ends.

The data writing procedure will be described in detail with reference to the flowchart of FIG. Note that reference numerals 301 and thereafter all denote some processing steps, but in order to avoid complication of the expression, the term “step” will be omitted and only the functional expression will be used. In FIG. 4, first, a pulse width to be given to writing is set in a pulse width setting process 303. Next, write voltage switching processing 305
To switch to the voltage for writing. Next, in a write / erase pulse generation process 306, a write pulse having the pulse width set in the pulse width setting process 303 is applied to the memory cell. Next, in a verify voltage switching process 307, the voltage is switched to a verify voltage. Then, it is determined in a verify process 308 whether or not the write level has been reached. If the write level has been reached, the write process is terminated. If the write level has not been reached, a series of write processing is repeated from the pulse width setting processing 303 again. If this is expressed as a relationship between the write time (pulse width) and the write voltage level, as shown in FIG. 5, as the write time increases, the write voltage level increases, and when the normal write voltage level is reached, the write processing is started. Will end.

On the other hand, the nonvolatile memory has a feature that the writing time varies for each memory cell alone, and the time characteristic is as shown in FIG. In FIG. 6, the vertical axis represents the number of cells and the horizontal axis represents the writing time. As can be seen from the write time characteristics, the write time not only varies within the nonvolatile memory chip, but also in FIG.
As shown in FIG. 7, the writing time characteristic differs for each chip.

As described above, the method of writing data into the memory cells having a variation in the writing time is roughly divided into two methods.
Can be divided into two purposes. One is a problem of reliability of a memory cell, and a writing method in which excessive writing (giving a writing time exceeding a normal writing level) to a memory cell is never performed even if the total writing time is long. . The other is a writing method in which the total time required for writing is reduced because the overwriting does not affect the reliability of the memory cell even if it is performed somewhat.

In a writing method that does not absolutely overwrite a memory cell, writing is usually performed by narrowing a pulse width given during normal writing. On the other hand, a writing method that reduces the total time required for writing is used. Then, the following several writing methods are proposed.

That is, in the write processing flowchart described with reference to FIG. 4, the time required for the processing for actually applying a write pulse in the write / erase pulse generation processing 306 is called a hardware processing.
3. The processes other than the process of giving a write pulse in the write voltage switching process 305, the verify voltage switching process 307, and the verify process 308 are called software processes.
If the write pulse applied to the memory cell is set to be shorter than the time required to reach the actual write level, additional write processing increases (hard processing increases), and as a result, software processing increases and it takes longer to write. There is a problem that the total time is long.

In order to solve such a problem, in a conventional data writing method, a pulse applied at the time of writing is divided into two types and controlled. One is a pulse (hereinafter referred to as an initial pulse) applied at the first time of the writing process of the same cell, and the other is a pulse (hereinafter, referred to as an additional pulse) applied at the second and subsequent times of the writing process of the same cell.

In a conventional method, a method of correcting an initial pulse and an additional pulse in accordance with the write characteristics of a memory cell in a chip has been considered. These pulse width correction methods are currently performed by performing a write operation. The writing time is measured while actually writing data to the memory cell in which it is written, and based on the measurement result, the pulse width given at the time of writing is corrected so as to be reflected in the next memory cell. In this write pulse correction method, a memory cell for which the write time is measured is hereinafter referred to as a measurement cell, and a memory cell to be written using the corrected pulse width is hereinafter referred to as a correction execution cell.

In a specific example of this type of conventional method, for example, disclosed in Japanese Patent Application Laid-Open No. 9-147590, a writing method in which only the initial pulse is corrected to reduce the total time required for writing is considered. Various methods have been considered, and a typical example is disclosed in
The writing method disclosed in Japanese Patent No. 147590 will be described with reference to the drawings. FIG. 8 is a flowchart of a conventional data write procedure.
= 1 In the process 301, the number-of-writes counter N is set to "1", and the number of writes is initialized.

Next, the number of times of writing is determined in the number of times of writing determination process 302. If the number of times of writing is 1 in the number-of-times-of-writing determination processing 302, the initial pulse width setting processing 303
, An initial pulse width is set. When the number of times of writing is 2 or more, an additional pulse width is set in an additional pulse width setting process 304. Next, the voltage is switched to a data write voltage in a write voltage switching process 305, and a write pulse is generated in a write / erase pulse generation process 306.

Next, verify voltage switching processing 307
Is switched to the voltage for verification, and the verify processing 30
In step 8, verify is performed at the write determination level. If the verification fails, the number of times of writing 30
In step 9, the number of write operations is determined. If the number of times of writing is 1, nothing is performed, and if the number of times of writing is two or more, the initial pulse width correction processing 310 increases the number of initial pulses. After that, the number-of-writes counter is incremented by 1 in the number-of-writes count-up process 311, and the process from the number-of-writes determination process 302 is repeated again. Only when the verification process 308 is passed, the number of write times is determined in the number-of-writes determination process 312. When the number of times of writing is 1, the initial pulse is decreased, and when the number of times of writing is 2 or more, nothing is performed. After that, the write / erase processing ends.

In addition to this method, in addition to the above-described method of correcting the initial pulse, a writing method of correcting an additional pulse in accordance with the number of times of writing of the measurement cell and writing data to the correction execution cell is also considered.

[0015]

However, in such a data writing and erasing method, the initial pulse and the additional pulse are not set in consideration of the characteristics of each chip, but are set in all non-volatile memories. Since the initial values of one initial pulse and an additional pulse are determined as, for example, an average value obtained by measuring the write characteristics of all the non-volatile memory chips as a common program prepared in the memory chip, Problems arise. For example, in writing to a measurement cell, if there is a large difference between the pulse given as the initial pulse and the writing time to reach the writing level, and if the initial value of the additional pulse is short, many additional pulses will be generated. .

FIG. 9A shows a time chart of a conventional data writing procedure. In the time chart of FIG. 9A, writing is performed on the measurement cell with the initial pulse width, but the writing level has not been reached, and additional writing is performed. The time from the time given by the initial pulse to the time to reach the write level is the time given by the additional pulse.
If the additional pulse has a fixed value and a short pulse width is set, many additional pulses are generated, which is a major problem.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a method of writing and erasing data in a semiconductor memory which can effectively reduce the total time required for writing data to the semiconductor memory. With the goal.

[0018]

According to the present invention, there is provided a method for writing and erasing data in a semiconductor memory according to the present invention. The number of times of writing is counted during the data writing to the memory cell which continues to apply the pulse until the write determination voltage level is obtained by applying an additional pulse after the second time of the writing process. According to the number of times of writing, the pulse width to be given is reduced when the number of times of writing is one, and the initial pulse is reduced without changing the additional pulse. When the number of times of writing is two, the number of additional pulses is reduced and the number of initial pulses is increased. If the number of times is 2 or more, write to control to increase the initial pulse by increasing the additional pulse And an erasing method, in which, for a memory cell which counts and measures the number of times of writing for the next cell for pulse width correction, an additional pulse is increased and corrected according to the number of times. is there.

According to the present invention, the total time required for writing data to the semiconductor memory can be effectively reduced.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a process for correcting an additional pulse in addition to a basic pulse width correction process in writing to a measurement cell in addition to the conventional pulse width correction for a correction cell. In practice, two places for storing the additional pulse width are provided.
If one is to correct an additional pulse for the correction execution cell and is a correction pulse A, and the other is to correct an additional pulse for the measurement pulse and is an additional pulse B, the correction pulse A is used for the correction execution cell. When the writing of the measurement pulse is completed, the pulse correction processing is executed. Further, the additional pulse B is a pulse width used for the writing processing to the measurement cell, and the verification processing is completed. The pulse width is corrected when additional writing is required.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same reference numerals are used for the same parts as those of the conventional one. FIG. 1 is a flowchart showing a flow of processing in an embodiment of a method for writing and erasing data to a semiconductor memory according to the present invention, and FIG. 2 is a time chart of a data writing procedure in the flow of processing in FIG.

In FIG. 1, first, the number of times of writing N = 1
In process 301, the number-of-writes counter N is set to "1", and the number of writes is initialized. Next, the additional pulse width B (=
Additional pulse width A) The additional pulse corrected in the previous memory cell in the initial setting process 314 is used as an additional pulse in the current memory cell (measurement cell). Next, the write number determination process 302
The number of write operations is determined. If the number of write operations is 1, the initial pulse width is set by the initial pulse width setting process 303. If the number of write operations is 2 or more, the additional pulse width B is set by the additional pulse width setting process 304. I do. Next, the voltage is switched to a data write voltage in a write voltage switching process 305, and a write pulse is generated in a write / erase pulse generation process 306. Next, the voltage is switched to a voltage for verification in a verify voltage switching process 307, and verification is performed at a write determination level in a verify process 308. If the verification fails, the number of times of writing is determined in the number of times of writing determination processing 309. When the number of times of writing is 1, nothing is performed, and when the number of times of writing is 2 or more, the initial pulse width and the additional pulse width B are increased by the initial pulse width correction processing 310 and the additional pulse B correction processing 315. Thereafter, the number-of-writes count-up process 31
The count of the number-of-writes counter is incremented by 1, and the process from the number-of-times-of-write determination process 302 is repeated. Only when the verification process 308 is passed, the number of write times is determined in the number-of-writes determination process 312. When the number of times of writing is 1, the initial pulse width is reduced.

Next, the number of times of writing is determined in the number-of-times-of-writing determination process 316. If the number of times of writing is 2, the additional pulse width A is reduced by the additional pulse width A correction process 318. Is the additional pulse width A
The additional pulse width A is increased by the correction process 317. After that, the write / erase processing ends. Write count is 2
Regarding the number of times, a method that does not change the additional pulse width is conceivable, but if there is no mechanism to reduce the additional pulse width, the additional pulse width will be too large because the additional pulse operates only in the increasing direction. Because
In the present embodiment, a mechanism for reducing the additional pulse width when the number of times of writing is two is adopted. Next, the flow of the processing will be described with reference to the time chart of FIG.

First, in writing to the measurement cell (address N), an initial pulse is given, but since the writing level has not been reached, an additional pulse corrected in the previous memory cell is given. When the additional pulse width is given, it is determined again whether the writing level has been reached. However, since the writing level has not been reached yet, the initial pulse width and the additional pulse width are increased and corrected this time. Next, writing is performed with the additional pulse width corrected for increase. When it is determined whether or not the writing level has been reached, the writing has been reached, and thus the writing is terminated. In the correction of the pulse width given to the next cell, the initial pulse width and the additional pulse width B are corrected to be increased because the number of times of writing is three. As a result, as shown in FIG. 9B, by increasing and correcting the additional pulse width for the measurement cell as a whole, the number of times of providing the additional pulse decreases, and as a result,
Since the software processing can be reduced, the total time required for writing can be reduced.

As a correction method for the measurement cell, a method of decreasing the additional pulse width in addition to the method of increasing the additional pulse width in the present embodiment is conceivable. However, when the decrease is performed, the possibility of increasing the number of additional write operations increases. Since the software processing increases, a correction method for increasing the additional pulse width is adopted.

As described above, according to the present embodiment, by increasing and correcting the additional pulse width with respect to the measurement cell, the number of times of providing the additional pulse decreases, and as a result, the software processing can be shortened. The total time required for writing can be reduced.

[0027]

As described above, according to the present invention, by increasing and correcting the additional pulse width for the measurement cell, the number of times of applying the additional pulse is reduced, and as a result, the software time can be shortened. Has the advantageous effect of being able to reduce the total time required for.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow in an embodiment of a method for writing and erasing data in a semiconductor memory according to the present invention;

FIG. 2 is a time chart of a data writing procedure in the processing flow of FIG. 1;

FIG. 3 is a block diagram illustrating an example of a general device for writing data to a nonvolatile memory;

4 is a flowchart of a data writing procedure in the device shown in FIG.

5 is a graph showing a relationship between a writing time and a writing voltage level in the device shown in FIG.

FIG. 6 is a graph showing a write time characteristic of each memory cell of the nonvolatile memory chip;

FIG. 7 is a graph showing write time characteristics of each nonvolatile memory chip;

FIG. 8 is a flowchart of a conventional data writing procedure.

FIG. 9 is a time chart of a data writing procedure according to the related art and the present invention.

[Description of Signs] 1 Write / erase pulse width setting circuit 2 Write / erase pulse generation circuit 3 Memory cell 4 Verify circuit 301 Write number counter N = 1 processing 302 Write number determination processing 303 Initial pulse width setting processing 304 Additional pulse width setting processing 305 Write voltage switching processing 306 Write / erase pulse setting processing 307 Verify voltage switching processing 308 Verify processing 309 Writing frequency determination processing 310 Initial pulse width correction processing (increase) 311 Writing frequency count up processing 312 Writing frequency determination processing 313 Initial pulse width correction processing ( Decrease) 314 Additional pulse width B initial setting processing 315 Additional pulse width B correction processing (increase) 316 Writing frequency judgment processing 317 Additional pulse width A correction processing (increase) 318 Additional pulse width A correction processing (Decrease)

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Claims (1)

[Claims] 1. A method for writing and erasing data to and from an electrically writable and erasable nonvolatile semiconductor memory,
An initial pulse is given at the first time of the write process, and an additional pulse is given at the second and subsequent write processes, and the pulse is continuously applied until the write determination voltage level is reached. After that, the pulse width given to the next memory cell is reduced according to the number of write times, the initial pulse is reduced without changing the additional pulse when the number of write times is one, and the additional pulse is reduced when the number of write times is two. This is a writing and erasing method in which the initial pulse is increased, and if the number of writing is two or more, the additional pulse is increased to increase the initial pulse. The additional pulse is also increased and corrected according to the number of times even for the memory cells that are counting and measuring Data writing and erasing method of the semiconductor memory.