JP2000259288A - Electronics - Google Patents

Abstract

(57) [Problem] To provide an electronic device capable of eliminating a malfunction due to an overcurrent when a CPU driving core voltage is changed. SOLUTION: Each of a low target value register 41a and a high target value register 41b of a voltage controller 29 stores 4-bit data which is a target voltage value,
The target voltage value selection data is stored in the change register 45, and the predetermined time data is stored in the time register 46. The 4-bit data representing the current voltage value is added or subtracted by one bit from the 4-bit data indicating the current voltage value for each predetermined time data to the 4-bit data that becomes the target voltage value selected by the data of the VRChange register 45. Outputs voltage value data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device such as a personal computer, and more particularly to an electronic device having a feature in voltage control of a CPU.

[0002]

2. Description of the Related Art In recent years, CPUs used in electronic devices such as personal computers have become more and more sophisticated. As a result, the processing speed and power consumption of CPUs have also increased. The driving battery consumption is also increasing.

In consideration of the above, in a conventional electronic device, the operating clock frequency of the CPU is changed,
A technique of controlling the CPU power consumption by changing the PU core voltage has been adopted. To change the CPU core voltage, a switching power supply IC for setting an output voltage is provided. Switching power supply IC
When the output voltage of the switching power supply circuit is changed in the power-on state by using the power supply, protection against overcurrent is required. FIG. 1 is a graph showing a current value when a CPU core voltage is changed in a conventional electronic device. For example, the CPU core voltage is changed from 1.3 (V) to 1.5.
When the voltage increases to (V) (increase by 0.2 V), when the capacitor capacitance is 1000 μF and the voltage change time is 10 μsec, generally, the flowing current is obtained by multiplying the value obtained by dividing the voltage change amount by the elapsed time by the capacitor capacitance. Can be derived by This causes a problem that an overcurrent of 20 A flows instantaneously and the electronic device malfunctions.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide an electronic apparatus capable of eliminating a malfunction due to an overcurrent when a CPU core voltage is changed. Aim.

[0005]

In order to achieve the above object, according to the present invention, there is provided an electronic apparatus comprising: a setting means for setting a target voltage value of a driving voltage supplied to a device;
According to the target drive voltage value set in the setting means, the current C
Voltage change means for changing the PU drive voltage stepwise to a target drive voltage value.

With such a configuration, the driving voltage of the CPU is not instantaneously increased to the target driving voltage,
Since the voltage is changed stepwise to the target drive voltage, overcurrent flowing through the circuit can be prevented.

[0007]

Embodiments of the present invention will be described below.
This will be described with reference to the drawings. FIG. 2 is a block diagram illustrating a configuration of the electronic device. The electronic apparatus is, for example, a notebook-type or laptop-type portable computer driven by a battery or an AC power supply, and has a CPU bus 3 and a PCI
A bus 4 and an ISA bus 5 are provided.

In the computer main body, a CPU 1, a host / PCI bridge device 2, a main memory 6, a display controller 10, a PCI / ISA bridge device 14,
HDD 17, BIOS ROM 18, keyboard controller / embedded controller (KBC / EC) 2
1, keyboard 23, power supply controller (PSC) 2
5, a voltage controller 29, a voltage regulator (VR) 31, and the like are provided.

The CPU 1 is, for example, a microprocessor "Penti" manufactured and sold by Intel Corporation in the United States.
um ". The CPU bus 3 directly connected to the input / output pins of the CPU 1 has a 64-bit data bus. The main memory 6 includes an operating system, a device driver, and an execution target. It is a memory device for storing application programs, processing data, etc., and is composed of a plurality of DRAMs.
It is connected to the host-PCI bridge device 2 via a dedicated memory bus having a 4-bit data bus.
The data bus of the CPU bus 2 can be used as the data bus of the memory bus. In this case, the memory bus includes an address bus and various memory control signal lines.

The host / PCI bridge device 2 has a CPU
This is a bridge LSI that connects the bus 2 and the PCI bus 4, and functions as one of the bus masters of the PCI bus 4.
The host / PCI bridge device 2 has a function of bidirectionally converting a bus cycle including data and addresses between the CPU bus 2 and the PCI bus 4, and a function of controlling access to the main memory 6 via the memory bus. And so on.

The PCI bus 4 is a clock synchronous type input / output bus, and all cycles on the PCI bus 4 are performed in synchronization with the PCI bus clock. The PCI bus 4 has an address / data bus used in a time-division manner. This address / data bus is 32 bits wide.

The display controller 10 is one of the bus masters of the PCI bus 4 like the host / PCI bridge device 2 and displays the image data of the video memory (VRAM) 11 on the LCD 12.

The PCI-ISA bridge device 14 is a PC
This is a bridge LSI that connects the I bus 4 and the ISA bus 5. The HDD 17 is connected to the PCI / ISA bridge device 14.
Is connected. The ISA bus 5 has a BIOS RO
M18 and KBC / EC21 are connected. KBC /
The keyboard 23 of the keyboard controller of EC21
Is connected.

The EC of the KBC / EC 21 (hereinafter referred to as EC 21) is a bridge LSI connecting the ISA bus 5 and the I ² C bus 19, and has a plurality of register groups readable / writable by the CPU 1. By using these register groups, communication between the CPU 1 and devices on the I ² C bus 19 becomes possible. The I ² C bus 19
It is used for communication between the EC 21, the PSC 25, and the voltage controller 29.

A battery pack 27 is provided in the computer body.
Are detachably connected. The battery pack 27 includes an EEPROM (not shown). This EEPRO
M stores battery information indicating the type of secondary battery of the battery pack 27, the remaining capacity, and the like. This battery information is read by the PSC 25 and used for battery charge control and system power management.

An AC adapter for connecting a commercial power supply to the computer main body is connected to the PSC 25. Thereby, the computer main body can be driven by the commercial power supply via the AC adapter.

The PSC 25 turns on / off the system power supply.
It is a controller that controls the operation power supply such as off
The charge control of the secondary battery of the battery pack 27 is performed.

A voltage control controller 29 is connected to the EC 21 via an I ² C 19. The voltage controller 29 sends the CPU core voltage set value to the voltage regulator (VR) 31, and the VR 31 responds to the set value according to the set value.
A drive voltage is supplied to the CPU 1 via the power supply line 32. A capacitor 33 is connected in parallel with the power supply line 32. The capacity of this capacitor 33 is 1000 μ
F. The capacitor 33 functions as a noise filter.

The CPU 1 has a built-in temperature detecting element 34 for detecting the internal temperature of the CPU 1. The temperature detected by the temperature detecting element 34 is detected by the BIOS via the EC 21.
The data is read at predetermined time intervals by the BIOS stored in the ROM 18 and stored in the register 7 provided in the main memory 6 and storing the CPU temperature data. Further, a register 8 for storing data indicating the presence or absence of the AC adapter 26 is provided in the main memory 6. When the PSC 25 detects that the AC adapter 26 has been connected while the power of the computer body is on, the EC 21
Issues a top priority interrupt notification (SMI). CP
U1 instructs the BIOS by the SMI output from the EC 21 to perform predetermined processing when the AC adapter 26 is connected. The BIOS stores data indicating the presence of the AC adapter in the register 8 in the main memory 6.

Next, a method of switching the CPU core voltage of the CPU 1 will be described in detail. FIG. 3 is a block diagram showing processing of the voltage controller. As shown in FIG. 3, the voltage controller 29 has a built-in multiplexer 40. When the power of the computer body is turned on or when the computer is reset, the voltage control controller 29
The VIDSET signal 43 for setting the initial value of the PU core voltage is set to initial value setting hardware (initial value setting means) 4.
2 is output. The VIDSET signal 43 is 4-bit data and is input to the multiplexer 40. The voltage control controller 29 includes an H / L register 41 in which 4-bit data indicating a target voltage value when changing the CPU core voltage is stored. H / L
As the 4-bit target voltage value stored in the register 41, predetermined 4-bit data is input to the multiplexer 40 in accordance with a signal from the EC 21. EC21 is C
It functions as clock setting means for PU clock frequency control.

When a reset signal is input to the voltage controller 29, the multiplexer 40 outputs VIDSET (4
Bit) as input voltage data (VID (4 bits) output)
30 and output to VR40. VR40 is VID (4
Bit) Adjust the voltage according to the output 30 and change the CPU to CPU1.
Supply core voltage. When a predetermined signal is input from the EC 21 to the voltage controller 29 in a state where the computer main body is driven by the core voltage based on the initial value VIDSET (4 bits) 43, the signal is stored in the H / L register 41. The 4-bit target voltage value is VI
It is input to the VR 31 as a D (4 bit) output 30.
VR 31 responds to this VID (4 bit) output 30 by
The CPU 1 driven by the initial voltage changes the CPU core voltage of the CPU 1 to the target voltage value stored in the H / L register 41. CPU supplied to this CPU 1
The CPU 1 operates by switching the clock frequency from the initial value to the target value in proportion to the core voltage.

Next, the CPU core voltage control will be described in detail with reference to FIGS. FIG. 4 is a block diagram showing the internal processing of the voltage controller. Figure 5 shows VID and CP
FIG. 4 is a diagram illustrating a relationship with a U-core voltage. FIG. 6 is a flowchart illustrating a startup process of the electronic device. FIG. 7 is a flowchart showing the frequency switching process. FIG. 8 shows the CP
FIG. 5 is a diagram illustrating a current value flowing in response to a change in a U-core voltage.

As shown in FIG. 4, the H / L register 41 of the voltage controller 29 is provided with a low target value register 41a for setting a low target value and a high target value register 41b for setting a high target value. ing.

Here, the core voltage of the CPU 1 can be freely changed between 1.3 V and 1.5 V. V shown in FIG.
R31 stores a voltage conversion table in which the relationship between the VID (4-bit) output 30 and the CPU core voltage shown in FIG. 5 is recorded. When the VID (4 bits) output 30 = “1110” is input, the VR 31 outputs the CPU core voltage =
When 1.3 V is supplied to the CPU 1 and the VID (4 bits) output 30 = "1010" is input, the CPU core voltage =
1.5V is supplied to CPU1. When the power of the computer is turned on, the CPU 1 is set to be driven in the low mode, and the signal VIDSET 43 is set with 4-bit data “1110” in advance.

Therefore, when the voltage controller 29 receives the reset signal 44, the multiplexer 40 selects VIDSET 43 = "1110", and
VR (3 bits) with ID (4 bits) output 30 = "1110"
1 will be output. VR31 is a 4-bit signal “1”.
A voltage of 1.3V corresponding to 110 ″ is supplied to the CPU 1. Thereby, the CPU 1 is driven at a core voltage of 1.3V.

Low target value register 41a and Hig
A predetermined value is set in the h target value register 41b by the EC 21 when the power of the computer is turned on and reset. In the case of the present embodiment, the low target value register 41
4-bit data = "1110" is stored in "a".
The 4-bit data = “10” is stored in the gy target value register 41b.
10 "is stored.

The voltage controller 29 has L
ow target value register 41a and high target value register 4
VRChan in which information is stored for selecting output of 1b
A ge register 45 is provided. VRChange
The information stored in the register 45 means the current mode setting. Further, the voltage control controller 29 is provided with a time register 46. VRChan
The Ge register 45 also stores data “0” from the EC 21 as an initial value when the computer is turned on and reset.
Is stored. The VRChange register 45 stores data “0” or “1”. VRChange
When data = "0" is stored in the register 45, the current core voltage (clock frequency) of the CPU 1 is Low.
This means a mode state, and when data = "1" is stored, the current core voltage (clock frequency) of the CPU 1 indicates a HIGH mode state. In the case of the present embodiment, VIDSET 43 = "1110"
To be output to R31, data "0" indicating that the initial value drive voltage is in the low mode is stored.

In the case of the present embodiment, EC 21
The data of the CPU temperature register 7 and the AC adapter 8 stored in the main memory 6 are read, and the temperature detection element 3
A signal is output to the voltage control controller 29 each time the temperature detected by step 4 exceeds a predetermined threshold value and when the presence or absence of the AC adapter 26 is detected. By this signal, data "0" is stored in the VRChange register 45.
Alternatively, “1” is stored. Further, the EC 21 sets the L value in the voltage controller 29 as an initial value when the power of the computer main body is turned on or reset.
The 4-bit data = “111” is stored in the ow target value register 41a.
0 ”, 4-bit data =“ 1010 ”is stored in the high target value register 41 b.The EC 21 stores the initial value in the time register 46 of the voltage controller 29 in the time register 46.
For example, “20 μsec” is set.

Normally, when the main body of the computer is driven by the battery 27, the computer is driven in a low mode (CPU core voltage = 1.3 V) in order to extend the battery driving time. As described above, when the computer main body is driven by the battery and the AC adapter 26 is connected to the computer main body and the operation mode is switched from the battery operation to the commercial power supply operation, the EC 21 stores the high voltage in the VRChange register 45.
Data "1" indicating the h mode is stored. Based on this data, the multiplexer 40 outputs 4-bit data = “101” stored as a specified value in the High target value register.
"0" is selected and output to the VR 31. The VR 31 adjusts the currently output CPU core voltage = 1.3V to 1.5V in the High mode and supplies it to the CPU1.

At this time, instead of rapidly increasing the CPU core voltage from 1.3 V to 1.5 V by 0.2 V, the voltage controller 29 changes the current output VID data from “1110” (Low mode). , First subtract 1 bit, and VID = “1101” (CPU core voltage = 1.3)
5V) is output to VR31. VR31 is は of the time data set in the time register 46 (10 μm).
In sec), the voltage is boosted by 0.05 V based on the voltage conversion table and supplied to the CPU 1. Next, when the time data in the time register 46 elapses, the voltage controller 29 further subtracts one bit from the current VID data = "1101".
VID = "1100" (CPU core voltage = 1.4 V) is output to VR31. VR31 is half the time data set in the time register 46 (10 μsec)
Then, the voltage is boosted by 0.05 V based on the voltage conversion table, and CP
Supply to U1. This process is sequentially repeated until the output data of the VID (4-bit) output 30 becomes the data “1010” stored in the High target value register 41b, and the current VID is stored for each time data stored in the time register 46. (4 bits) Output 30 is subtracted bit by bit and output to VR31. By the above processing, the CP
As shown in FIG. 8, the U core voltage is stepped up by 0.05 V every time data (20 μsec) set in the time register 46, and finally the CPU core voltage = 1.3 V
To 1.5V. As the CPU core voltage changes, the driving clock frequency of the CPU 1 also changes.
Conversely, when the CPU 1 is driven at the CPU core voltage = 1.5 V (High mode) and shifts to the LOW mode drive, the EC 21 sets the VRChange register 4
5 is stored with data “0”. In response, the voltage controller 29 outputs the current VID (4 bit) output 3
0 to 4 stored in the low target value register 41a
Until the bit data is added to "1110", the VID (4-bit) output 30 added by one bit for each time set in the time register 46 is output to the VR 31. The VR 31 gradually increases the CPU core voltage in steps of 0.05 V from 1.5 V to 1.3 V based on the voltage conversion table in accordance with the VID (4-bit) output 30 output every time set in the time register 46. Step down to CPU
Supply to 1.

Next, a series of processes will be described with reference to FIGS. First, the power of the computer is turned on.
Next, initialization of each register in the voltage control controller 29 is performed. VIDSET43 from initialization setting HW42
Is input to the voltage control controller 29. The EC 21 stores “1110” (voltage 1.3 V) in the low target value register 41a and “1010” in the high target value register 41b. Next, the EC 21 stores “20 μsec” in the time register 46 and sets the VRCh.
"0" (Low mode) is set in the angle register 45 (step S1). Next, CPU core voltage conversion processing (hereinafter, frequency switching processing) (step S2) is performed, and boot processing is performed. (Step S3).

Next, the frequency switching process will be described. The frequency switching process is performed after initialization of each register of the voltage control controller 29 and every time a frequency switching factor occurs, and is also executed after the boot process. In the case of this embodiment, after the initialization of the voltage control controller 29 and when it is detected that the internal temperature of the CPU 1 has exceeded a predetermined threshold (75 ° C. to 80 ° C.)
When the presence or absence of the AC adapter 26 is detected, EC2
1 by the SMI generated by the BIOS
21 is executed when a frequency switching processing command is issued to the CPU 21. When these states are reached, the EC 21 performs a predetermined frequency switching process.

First, the BIOS reads data stored in the register 7 of the main memory 6 to determine whether or not the AC adapter 26 is connected to the computer main body (step S10).

When the computer is driven by the commercial power supply by the AC adapter 26, the BIOS reads the data stored in the register 8 of the main memory 6 and checks whether the temperature of the CPU 1 is 80 ° C. or less. It is detected whether or not it is (step S11).

When the temperature of the CPU 1 is 80 ° C. or less, B
The IOS similarly determines from the data in the register 8 whether the temperature of the CPU 1 is 75 ° C. or lower (step S1).
2).

When the temperature of the CPU 1 is equal to or higher than 75 ° C., the CPU 1 maintains the state where it is driven at the initial voltage of 1.3 V, and the frequency switching process ends without performing the frequency switching. That is, the temperature of the CPU 1 is 75 °
When the temperature is equal to or higher than C and equal to or lower than 80 ° C., even if the AC adapter 26 is connected and driven by a commercial power supply,
U1 is driven with the drive voltage (initial value (VIDSET43) = Low mode) immediately before the frequency switching process (step S2).

On the other hand, when the CPU temperature is lower than 75 ° C., B
The IOS notifies the EC 21 to store the data “1” (High mode) in the VRChange register 45. The EC 21 determines whether the data in the VRChange register 45 is "1" (step S13).

If the value of the VRChange register 45 is not "1", the EC 21 sets the VRVRChange
"1" (High mode) is stored in the register 45 (step 14).

Thereafter, in step 13, the BIOS
As a result, when the value of the VRChange register 45 is determined to be "1", and when "1" is stored in the VRChange register 45 by the EC 21 in step 14, the BIOS notifies the EC 21 of the VID switching command. (Step S17). This command causes the EC 21 to instruct the voltage control controller 29 to VRRChang.
Control is performed to respond to the data “1” in the e-register 45. The multiplexer 40 of the voltage controller 29 responds to the data “1” of the VRChange register 45 until the 4-bit data “1010” stored in the high target value register 41 b becomes V
The ID (4 bits) data 30 is subtracted by 1 bit for each time stored in the time register 46 from the current 4-bit data “1110” to “1010”.
The bit data is output to VR31. Step 1
If it is determined in step 3 that the value of the VRChange register 45 is "1", the state (VID (4 bit) data 30 = "1010") is maintained.

Next, in step S10, when it is determined that the AC adapter 26 is not connected to the computer main body, that is, when the battery is being driven =
A from Low mode or from a state where the AC adapter is driven by a commercial power supply (High mode)
If the C adapter 26 is removed and is therefore powered by a battery, it is necessary to conserve battery capacity.
PU1 needs to be driven in the Low mode. For this purpose, the BIOS stores the VRChange register 4 in EC21.
5 to store data “0” (Low mode). The EC 21 determines whether or not the data in the VRChange register 45 is “0” (Step S15).

In step S11, the CPU temperature is set to 8
If it is determined that the temperature is higher than 0 ° C., that is, it is necessary to reduce the driving clock frequency of the CPU 1 so that the CPU 1 does not cause a problem in a high-temperature circuit, and the CPU 1 is switched to the low mode driving. There is a need. Therefore, the process of step S15 described above is performed. The data “0” (L
If (low mode) is stored, it is determined that the state immediately before that is the low mode state, and the process ends.

If the value of the VRChange register 45 is not "0", the EC 21 sets the VRVRChange
“0” (Low mode) is stored in the register 45 (Step S14), and the processing of Step S17 described above is performed. This completes the frequency switching process.

With the above configuration, for example, as shown in FIG. 8, for example, a low mode (CPU core voltage =
1.3 V) to High mode (CPU core voltage = 1.
5V), switch to 0.05V every 20 μsec.
By increasing the voltage step by step, a current of only 5 amps flows every 20 μsec until reaching the CPU core voltage target value of 1.5 V. Therefore, the current flowing when the voltage is stepped up by 0.2 V at a time is 20 amps (FIG. 1).
, An overcurrent can be prevented, and circuit destruction can be prevented.

Although the present embodiment has been described with reference to the presence or absence of an AC adapter and the case where the CPU temperature exceeds a threshold as the factors for performing the frequency switching process, the present invention is not limited to these factors, and is not limited to this factor. When an expansion device with a cooling function is connected, when the user arbitrarily sets the frequency switching (even if the CPU is
May be set to drive in the High mode, the mode may be set to drive in the Low mode even when the AC adapter is driven, or the frequency switching process may be executed when used together with the cooling means in the computer main body.

[0045]

According to the invention described in detail above, the present CP
When boosting the drive voltage from the U drive core voltage to the target drive core voltage, by increasing the voltage stepwise at predetermined time intervals, overcurrent can be prevented and damage to the circuit can be prevented. It is possible to change the drive voltage of the CPU normally without any change. That is, the drive clock frequency of the CPU is normally changed in proportion to the drive voltage to be changed, so that malfunction of the electronic device can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional current value flowing in response to a change in CPU core voltage.

FIG. 2 is a block diagram showing a configuration of an electronic device according to the present invention.

FIG. 3 is a block diagram showing processing of a voltage control controller according to the present invention.

FIG. 4 is a block diagram showing internal processing of a voltage control controller according to the present invention.

FIG. 5 is a diagram showing the relationship between VID and CPU core voltage according to the present invention.

FIG. 6 is a flowchart showing processing of an electronic device according to the present invention.

FIG. 7 is a flowchart showing a frequency switching process according to the present invention.

FIG. 8 is a diagram showing a current value flowing in response to a change in a CPU core voltage according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... Host / PCI bridge device 3 ... CPU bus 4 ... PCI bus 5 ... ISA bus 6 ... Main memory 7 ... CPU temperature register 8 ... AC adapter register 10 ... Display controller 11 ... VRAM 12 ... LCD 14 ... PCI / ISA bridge 17 ... HDD 18 ... BAIOS 19 ... I 2 C bus 21 ... KBC / EC 25 ... power controller 26 ... AC adapter 27 ... battery 28 ... ^{I 2} C bus 29 ... voltage control controller 30 ... VID 31 ... voltage regulator 32 ... Output voltage 33 ... Capacitor 40 ... Multiplexer 41 ... H / L register 41a ... Low target value 41b ... High target value 42 ... Initial value setting H / W 43 ... VIDSET output 45 ... VRCHANG register 46 ... Time register

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Ryoji Ninomiya 2-9-9 Suehirocho, Ome-shi, Tokyo F-term in Toshiba Ome Plant Co., Ltd. 5B011 EA02 GG04 HH01 JA12 LL02

Claims (10)

[Claims] 1. A setting means for setting a target voltage value of a drive voltage supplied to a device; and
An electronic device comprising: voltage changing means for changing a current CPU drive voltage stepwise to the target drive voltage value. 2. The apparatus according to claim 1, further comprising: time setting means for setting a time, wherein the voltage changing means sets the current drive voltage of the device stepwise to the target drive voltage value with the time set in the time setting means as a cycle. The electronic device according to claim 1, wherein: 3. The electronic apparatus according to claim 1, wherein the device is a CPU. 4. An electronic apparatus having a CPU driven by a drive voltage, wherein: a setting means for setting a first target drive voltage value and a second target drive voltage value for driving the CPU; Selecting means for selecting either the first or second target driving voltage value according to a factor; and selecting the driving voltage according to the first or second target driving voltage value selected by the selecting means. An electronic apparatus, comprising: voltage changing means for changing the driving voltage stepwise to the first or second target driving voltage value. 5. A time setting means for setting a time, wherein the voltage changing means sets a current CPU drive voltage to the selected first or second target in a cycle of the time set in the time setting means. 5. The electronic device according to claim 4, wherein the drive voltage is changed stepwise. 6. The electronic apparatus according to claim 4, wherein the voltage value switching factor is notified when the temperature detection of the CPU exceeds a predetermined threshold. 7. The electronic apparatus is driven by at least one of a battery and an external power supply, and the voltage value switching factor is issued when switching from the battery drive to the external power supply. Item 6. The electronic device according to Item 4. 8. A device is driven with a predetermined driving voltage, a target driving voltage of the device is set, and the predetermined driving voltage is gradually increased according to the set target driving voltage until the predetermined driving voltage reaches the target driving voltage value. A voltage control method characterized in that the voltage is changed to: 9. A first method for setting an initial drive voltage value of a CPU.
Setting means; a CPU driven in accordance with the initial value driving voltage value; a second setting means for setting a first target driving voltage value and a second target driving voltage value for the CPU; Selecting means for selecting any of the target voltage values; and setting the initial drive voltage to the selected first drive voltage in accordance with the first or second target drive voltage value selected by the select means.
Or a voltage changing means for changing the driving voltage stepwise to a second target driving voltage value. 10. A CPU, initial value setting means for setting an initial drive voltage value of the CPU, voltage control means for outputting the initial drive voltage value set by the initial value setting means, and voltage control means A voltage supply unit that supplies a voltage to the CPU based on the initial drive voltage value output by the control unit; a voltage control unit that sets a target drive voltage value of the CPU; Output means for changing the initial drive voltage value stepwise to the target drive voltage value and outputting to the voltage supply means in accordance with the target drive voltage value set by the target voltage value setting means, An electronic apparatus, wherein the voltage supply means supplies a voltage to the CPU in a stepwise manner in accordance with a drive voltage value changed and outputted in a stepwise manner by the output means.