JP2000259110A - Image data integration method, image data integration circuit, and display device - Google Patents

Abstract

(57) Abstract: An image data integration method, an image data integration circuit, and a display device are provided which enable the power consumption of a display panel to be limited to a predetermined value. SOLUTION: For each of m × n image data Dij, the data is corrected using a correction coefficient corresponding to the data (groups G1 to Gm), and then the integration of m × n image data Dij is performed. I do.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP), a fluorescent display tube, and an electroluminescent panel (EL).
Also called P. The present invention relates to an image data integration method, an image data integration circuit, and a display device applied to a display panel having self-luminous pixels, such as a display panel described in (1).

[0002]

2. Description of the Related Art FIG.
It is a block diagram which shows the whole structure of the display apparatus described in the publication No. 7. 16, an image signal control circuit 1 receives an image signal S1 and generates an image signal S2 and various control signals accompanying the image signal from the image signal S1,
Reference numeral 14 denotes a pixel number integration circuit having a function of integrating the number of image data of a predetermined value level from image signals S2 given in a predetermined period (for example, one vertical scanning period or one horizontal scanning period). An APC signal generation circuit for controlling the display brightness in accordance with the integration result S3a in order to control an automatic power control function of receiving the integration result S3a of the circuit 14 and limiting the power consumption to a predetermined value. In response to the signal S2 and the APC signal S4 of the APC signal generation circuit 7, the display luminance is controlled in accordance with the APC signal S4 in accordance with the image signal S2 in accordance with the horizontal and vertical scanning periods of the screen. A display timing control circuit for controlling the display timing of the displayed image, a driving power supply 2 for generating a driving voltage necessary for displaying an image, Matrix display panel comprising a large number of cells of the optical type are arranged in a matrix, the control signal S5 of four display timing control circuit 6 and the driving power supply 2
This is a driver that receives a drive voltage from and generates various drive pulses for driving the matrix display panel 5. The display timing control circuit 6 and the APC signal generation circuit 7 constitute the control means 3.

Hereinafter, the operation will be described. In order to reduce the power consumption of the matrix display panel 5, the pixel number accumulating circuit 14 firstly outputs the image signal S2 given in a predetermined period, for example, one vertical scanning period (or one horizontal scanning period).
Among them, the number of image data in which the luminance value of the image data (image data corresponding to one pixel) included in the image signal S2 has a predetermined level is integrated. APC signal generation circuit 7
Controls the display brightness according to the integration result S3a. Specifically, it functions as frequency changing means for changing the driving frequency of the matrix display panel 5 (for example, when the matrix display panel 5 is a PDP, the frequency of the sustain pulse), and provides the display timing control circuit 6 with the display timing control circuit 6 based on the integration result S3a. By outputting the APC signal S4, the driving frequency of the matrix display panel 5 is changed.

The power consumption of the display device, that is, (the output voltage of the drive power supply 2) × (the drive current Is supplied from the drive power supply 2 to the driver 4) is the display rate (the number of all display cells) in the matrix display panel 5. (The ratio of the cells that emit light). Therefore, for example, even if the display ratio increases and the integration result S3a increases, the driving current Is decreases by limiting the driving frequency by the APC signal generation circuit 7, and the power consumption is limited to a certain value or less. Have been to be.

The APC signal generating circuit 7 weights the integration result S3a of the image signal S2 and the integration result S3a of the image signal S2 by gradation when performing gradation display, and newly adds the integration pixel number. Is associated with the drive current Is, and the drive frequency is set based on the number of integrated pixels weighted by gradation.

[0006]

By the way, when the matrix display panel 5 is a PDP for displaying a color image,
The phosphors provided in the cells are usually separately colored into three colors of red (R), green (G), and blue (B) for each cell. Since the phosphor uses different materials for each color, the thickness may be different for each color in manufacturing.
Alternatively, taking into account the emission intensity of each color, color balance, etc.,
The thickness may be intentionally made different for each color. In the case where the thickness of the phosphor is different as described above, if the thickness of the phosphor is large, the discharge space becomes relatively narrow, and the spread of the sustain discharge in the discharge space is spatially limited. As a result, the current flowing during the sustain discharge (hereinafter, referred to as the sustain discharge current) decreases. Conversely, when the thickness of the phosphor is small, the discharge space becomes relatively large, and the spread of the sustain discharge in the discharge space increases, so that the sustain discharge current increases. Therefore, when the thickness of the phosphor formed for each color is different, the current flowing in each cell (accordingly, for each pixel) corresponding to each color for obtaining a desired display state is substantially different.

FIG. 17 shows a PD in a PDP device.
FIG. 3 is an explanatory diagram showing a position (arrangement) relationship between P and a driver circuit for driving the PDP. In FIG. 17, 3
Reference numeral 0 denotes connection wiring for connecting the driver 4 and the matrix display panel 5, and other reference numerals correspond to those in FIG.

The driver 4 is connected to a sustain electrode Xi and a scan electrode Yi provided on the PDP 5 via a wiring 30. In order to cause the cell to emit light, the driver 4 applies a sustaining pulse having an inverted polarity alternately between the sustaining electrode Xi and the scanning electrode Yi provided on the PDP 5 to generate a sustaining discharge in the discharge space. Done. When the driver 4 is arranged at the center P2 in the vertical position of the PDP 5, the length of the connection wiring 30 from the driver 4 to the row near the center of the PDP 5 is short, and the connection is made with low impedance. Top P of
1 and the length of the connection wiring 30 reaching the row near the lower portion P3 is longer than the length of the connection wiring 30 reaching the row near the center, so that the impedance of the connection is further increased and the resistance of the connection wiring 30 is increased. In the case where the voltage drop (voltage drop) due to the component and the influence of ringing due to the inductance component occur more, and the above-mentioned voltage drop becomes greater than the central portion P2 of the PDP 5, the discharge current decreases. When the influence of ringing increases, the discharge current tends to increase.
In addition, the current flowing for each scanning electrode Yi (for each row) varies. Further, as described later, a P cell in which the cell structure or the cell structure corresponding to one pixel is different for each color.
In the case of DP, the difference in the flowing current becomes remarkable.

Since there are various types of variations in the cells, such as the above-mentioned variations in the structure of the cells and variations in the wiring 30 between the sustain electrodes Xi and the scan electrodes Yi and the driver 4, the current flowing through the PDP is not sufficient. There is a problem that the power consumption of the PDP cannot be actually limited to a predetermined value even if the variation occurs and the APC function operates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has an image data integrating method, an image data integrating circuit, and a display device capable of limiting the power consumption of a display panel to a predetermined value. The purpose is to obtain.

[0011]

According to a first aspect of the present invention, there is provided a method for integrating a plurality of image data corresponding to each of a plurality of cells constituting a display panel, the method comprising: The image data is corrected for each of the image data using a correction coefficient corresponding to the image data, and then the integration of the plurality of image data is performed.

In the means for solving problems according to claim 2 of the present invention, the plurality of image data are divided into a plurality of groups,
One correction coefficient corresponds to each of the plurality of groups.

[0013] In the means for solving problems according to claim 3 of the present invention, the plurality of groups correspond to each color.

[0014] The means for solving the problem according to claim 4 of the present invention is:
The image data includes a luminance value.

According to a fifth aspect of the present invention, in accordance with the fifth aspect of the present invention, the power supply to the display panel is suppressed according to the result of the integration.

According to a sixth aspect of the present invention, there is provided an image data integrating circuit for integrating a plurality of image data corresponding to each of a plurality of cells constituting a display panel, wherein the plurality of image data are integrated. Receiving the plurality of image data, correcting the image data using a correction coefficient corresponding to the image data, and then integrating the plurality of image data.

[0017] In the means for solving problems according to claim 7 of the present invention, the plurality of image data are divided into a plurality of groups,
One correction coefficient corresponds to each of the plurality of groups.

[0018] In the means for solving problems according to claim 8 of the present invention, the plurality of groups correspond to each color.

In a ninth aspect of the present invention, the image data includes a luminance value.

According to a tenth aspect of the present invention, in the image processing apparatus, the image data integration circuit includes a correction integration section for performing the correction and integration, the correction coefficient stored in advance, and the correction coefficient stored in the correction integration section. And a correction coefficient output unit that outputs the correction coefficient.

[0021] In the eleventh aspect of the present invention, the image data accumulating circuits are provided in parallel corresponding to the groups and receive corresponding ones of the image data divided into the groups. , A plurality of correction units each performing the correction.

According to a twelfth aspect of the present invention, there is provided an image data multiplying circuit according to any one of the sixth to eleventh aspects, the display panel, and the display device, which displays the image represented by the plurality of image data. An image display control unit that drives the display panel to display on a panel, and a supply power suppression unit that suppresses supply power supplied to the display panel according to a result of the integration of the image data integration circuit. Is provided.

[0023] In the means for solving problems according to claim 13 of the present invention, the supplied power suppressing section suppresses the supplied power such that the larger the result of the integration, the smaller the rate of change of the supplied power.

According to a fourteenth aspect of the present invention, in the display panel, the area of the cell is different for each color.

[0025] According to a fifteenth aspect of the present invention, there is provided a display panel, comprising: a display panel; and a plurality of image data corresponding to a plurality of cells constituting the display panel. A correction circuit that corrects the image data using a correction coefficient corresponding to the image data, an image data integration circuit that receives the plurality of image data and integrates the image data, and an image represented by the plurality of image data An image display control unit for driving the display panel to display the image on the display panel, and a supply power for suppressing a supply power to the display panel according to a result of the integration of the image data integration circuit. A suppression unit.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram illustrating a configuration of a display device according to Embodiment 1 of the present invention. The display device according to the first embodiment includes an image signal control circuit 1, a correction type integration circuit (image data integration circuit) 8, a driving circuit 100, and a matrix display panel 5. The drive circuit 100 includes an APC signal generation circuit (supply power suppression unit) 7
And an image display control unit 101. Image display control unit 10
1 includes a driving power supply 2, a driver 4, and a display timing control circuit 6.

The image signal control circuit 1 receives the video signal S1 and outputs an image signal S2. The correction type integrating circuit 8 receives the image signal S2 and outputs a result of integration S3. The APC signal generation circuit 7 receives the integration result S3 and outputs an APC signal S4. The display timing control circuit 6 receives the image signal S2 and the APC signal S4, and outputs a control signal S5. The drive power supply 2 generates and outputs power S6. The driver 4 receives the control signal S5 and the power S6, and is connected to the matrix display panel 5. The drive current supplied from the drive power supply 2 to the driver 4 is defined as Is. The drive current Is is proportional to the power consumed by the matrix display panel 5.

The matrix display panel 5 is a so-called three-electrode surface discharge type PDP. FIG. 2 shows the concept of the matrix display panel 5. The matrix display panel 5 is composed of m × n cells Cij (i is an arbitrary integer from 1 to m, j is an arbitrary integer from 1 to n) arranged in a matrix.

The structure of the matrix display panel 5 in the first embodiment is as shown in FIG. FIG. 3 shows a cross-sectional structure of the matrix display panel 5 and shows one cell Cij. Glass substrate 21 (first substrate) and glass substrate 24
The (second substrates) are arranged to face each other via the discharge space 27. On the glass substrate 24 side of the glass substrate 21, an electrode pair XYi is formed. The dielectric 22 covers the electrode pair XYi and the glass substrate 21. The protective film 23 is made of, for example, MgO, and is
Cover 2 On the glass substrate 21 side of the glass substrate 24, an address electrode Aj is formed in a direction orthogonal to the electrode pair XYi. On the glass substrate 21 side of the address electrode Aj,
A partition 26 for partitioning cells is formed in a direction orthogonal to the address electrodes Aj. The phosphor 25 covers the address electrode Aj. Note that an insulating layer may be formed between the address electrode Aj and the phosphor 25.

The electrode pair XYi is connected to the sustain electrodes Xi parallel to each other.
And the scanning electrodes Yi. Sustain electrode Xi and scan electrode Yi
Each has a laminated structure of a transparent electrode 28 and a metal electrode (bus electrode) 29 such as a low-resistance metal provided to partially overlap the transparent electrode 28 to assist the conductivity of the transparent electrode 28. It is.

Glass substrate 21, electrode pair XYi, dielectric 2
2 and the protective film 23 are collectively referred to as a front substrate FB, and include a glass substrate 24, an address electrode Aj, a phosphor 25, and a partition 2.
6 is collectively called a back substrate BB. The matrix display panel 5 has a structure in which a front substrate FB and a rear substrate BB are bonded.

The front substrate FB and the rear substrate BB bonded to each other are sealed and sealed at their peripheral portions (not shown) with frit glass or the like, whereby the discharge space 27 is sealed and the inside of the discharge space 27 is evacuated. , Xe, N
The discharge gas e is sealed in the discharge space 27.

Next, the operation of the cell Cij will be described. During a predetermined writing period, the sustain electrodes Xi (or
By generating a write discharge between scan electrode Yi) and address electrode Aj, sustain electrode Xi and scan electrode Yi are generated.
Then, wall charges (bit value “1” described later) are accumulated on the dielectric 22 (actually on the protective film 23) near the discharge gap between them.

Next, continuously over a predetermined maintenance period,
Video signal S1 between sustain electrode Xi and scan electrode Yi (FIG. 1)
A predetermined drive pulse based on is applied. By setting the polarity of the driving pulse to be different from the wall voltage generated by the wall charges, the driving pulse is maintained in the discharge gap between the transparent electrode 28 of the sustain electrode Xi and the transparent electrode 28 of the scan electrode Yi of the cell in which the wall charges are accumulated. Discharge occurs, generating ultraviolet light. This ultraviolet light is converted into visible light by the phosphor 25 and passes through the front substrate FB. As a result, an image is displayed on the front substrate FB.

The partition 26 comprises a front substrate FB and a rear substrate BB
As a spacer, a sustain discharge in a sustain period, a write discharge generated by a write pulse applied to the address electrode Aj in a predetermined write period, etc., in one line direction (direction along the electrode pair XYi). Has the role of ensuring the stability of the write discharge or the sustain discharge by preventing the spread of the discharge.

Next, the internal structure of the correction type integrating circuit 8 in FIG. 1 is as shown in FIG. 4 in the first embodiment. The correction type integration circuit 8 includes an operation / integration unit (correction integration unit) 9 and a correction coefficient output unit 10. The correction coefficient output unit 10 receives the address # and outputs a correction coefficient A. The calculation / integration unit 9 receives the image signal S2 and the correction coefficient A, and receives the address # and the integration result S
3 is output. The correction coefficient output unit 10 is a ROM and a ROM.
And a logic circuit having a function of reading the correction coefficient A therein. Note that the address # is a generic name of the addresses described later, and the correction coefficient A is a generic name of the correction coefficients described later.

The operation of the display device shown in FIG. 1 is roughly classified into an image display function for displaying the image indicated by the video signal S1 on the matrix display panel 5, and an APC function for limiting the power consumption of the matrix display panel 5 to a predetermined value. it can. Hereinafter, the operation of the display device of FIG. 1 will be described separately for the image display function and the APC function.

Image display function. First, the image display function will be described. The image signal control circuit 1 receives a video signal S1 such as a TV signal or a display signal of a personal computer. The type of the video signal S1 includes RGB, T in the case of a display signal of a personal computer.
In the case of the V signal, there are NTSC, PAL, SECAM and the like. The image signal control circuit 1 performs synchronization separation, video demodulation, YC separation, A / D conversion, inverse gamma correction, and the like on the video signal S1 according to the type of the video signal S1, and performs n × m corresponding to each cell Cij. Image data Dij, a vertical synchronizing signal, a horizontal synchronizing signal, and a dot clock (clock for reading out image data Dij such as digitalized RGB)
An image signal S2 of a predetermined signal format for driving the display panel, such as a control signal in combination with the above, is generated from the video signal S1 and output.

FIG. 5 conceptually shows the structure of the image data Dij in the image signal S2. FIG. 5 corresponds to FIG. The image data D is composed of m × n pieces of image data Dij, and the image data Dij of the i-th row and the j-th column corresponds to the cell Cij of the i-th row and the j-th column.

The image data Dij is specifically a luminance value, for example, 8 bits. If it is 8 bits, the light emission brightness of the cell Cij can be represented by 256 gradations.

The image display controller 1 of the drive circuit 100 shown in FIG.
01 drives the matrix display panel 5 so that each cell Cij of the matrix display panel 5 emits light at the luminance value indicated by the image data Dij of the image signal S2. As a result, the image indicated by the image data D of the image signal S2 is displayed on the matrix display panel 5.

The image display control unit 101 will be described in more detail. The image display control unit 101 drives the matrix display panel 5 using a known subfield method. Hereinafter, for example, one field has eight subfields SF1 to SF
And the image data Dij is composed of eight bits b1, b
,..., B8, and cell C in each subfield
The period during which ij maintains light emission (sustain period) is the ratio (weighting)
, The sustain period of SF1, the sustain period of SF2,.
, SF8 sustain period = 1: 2,..., 128 will be described.

The display timing control circuit 6 controls the driver 4 so as to operate as follows. Each subfield includes a write period and a sustain period. First, in the writing period, the driver 4 sets the bits of the image data Dij (for example,
In the subfield SF8, the bit b8) is written in the corresponding cell Cij. Next, in the sustain period, the driver 4 generates a drive pulse (period is a constant value T (sec)) having the number of pulses multiplied by the weight of the constant K from the power S6 and sends the drive pulse to all the cells Cij of the matrix display panel 5. A drive pulse is given all at once. At this time, the number of drive pulses applied per second is called a drive frequency. The cell Cij in which the "1" bit is written emits light only during the sustain period, and the cell Cij in which the "0" bit is written does not emit light. The sustain period is, for example, K × 128 × T (sec) in the case of the subfield SF8. By performing the subfields SF1 to SF8 in this order, the cell Cij emits light with 256 levels of brightness. The above is the image display function.

APC function. Next, the APC function will be described. 1 receives the image signal S2, and divides the image data D (FIG. 5) of the image signal S2 into each row in FIG. The group Gi of the i-th row includes n pieces of image data Di.
1 to Din.

FIG. 7 shows the correction coefficients stored in the ROM of the correction coefficient output section 10 in FIG. FIG. 7 corresponds to FIG. The correction coefficient output unit 10 previously stores m correction coefficients A1 to Am in a ROM. The correction coefficients A1 to Am correspond to the addresses # 1 to #m, respectively, and the address #i
Corresponds to the group Gi on the i-th row in FIG.

The operation / integration unit 9 outputs the address # 1 to the correction coefficient output unit 10. In response, the correction coefficient output unit 10 outputs the correction coefficient A1 to the calculation / integration unit 9. The calculation / integration unit 9 calculates the n image data D11 in the group G1.
.. D1n and the correction coefficient A1. The reading and multiplication are similarly repeated for the other correction coefficients Ai and groups Gi. Thus, the operation / integration unit 9
Is the correction coefficient Ai corresponding to the group Gi and the group G
The image data D is corrected by performing multiplication with the n image data Di1 to Din in i.

Next, the arithmetic / integrator 9 adds (m × n) corrected image data D (integration). That is, at this point, the calculation / integration unit 9 determines that Σ (Ai × (Di1 + Di2 +...)
... Din)). Then, the calculation / integration unit 9 outputs the integration result S3 of Σ (Ai × (Di1 + Di2 +... Din)).

Integration result S3 (= Σ (Ai × (Di1 + Di2
+ ... Din))) is equivalent to representing the brightness of the entire image displayed on the matrix display panel 5. The brightness of the entire image displayed on the matrix display panel 5 is proportional to the power consumption of the matrix display panel 5. Therefore, the size of the integration result S3 is determined by the matrix display panel 5
Can also be said to represent the power consumption of As the integration result S3 is larger, the whole image becomes brighter, and the power consumption of the matrix display panel 5 increases.

The APC signal generation circuit 7 receives the integration result S3, compares the integration result S3 with a preset reference value a, and determines whether or not the entire image displayed on the matrix display panel 5 is bright. That is, it is determined whether or not the power consumption of the matrix display panel 5 exceeds the reference value a. The APC signal generation circuit 7 calculates the integration result S3
Is greater than or equal to the reference value a, the APC signal generation circuit 7 outputs an APC signal S4 for instructing the image display function to suppress the driving frequency described above to the display timing control circuit 6. The display timing control circuit 6 responds to the APC signal S4
By suppressing the drive frequency, the power consumption of the matrix display panel 5 (therefore, the drive current Is (supply power) supplied from the drive power supply 2 to the driver 4) is suppressed.

FIG. 8 is a graph showing the relationship between the integration result S3 and the driving frequency. As shown in FIG. 8, the integration result S3
Is less than the reference value a, the driving frequency is the predetermined number of pulses b
(= The number of pulses multiplied by the weight of the constant K. For example, if the subfield SF8 is K × 128), as shown in FIG. 9, when the integration result S3 is less than the reference value a, the consumption of the matrix display panel 5 is reduced. The power increases in proportion to the integration result S3. However, when the integration result S3 is equal to or larger than the reference value a, the drive frequency decreases as the integration result S3 increases. Thus, when the integration result S3 is equal to or larger than the reference value a, the power supplied from the driving power supply 2 to the driver 4 can be suppressed to the predetermined value c. The above is the APC function.

One group corresponds to one image data for each of the plurality of image data even if one correction coefficient does not correspond to each of the plurality of groups as shown in FIG. I just need. For example, as shown in FIG. 10, one correction coefficient may correspond to one image data. That is, one group may include only one image data. In this case, there are m × n groups Gij corresponding to one image data Dij on a one-to-one basis. In addition, as shown in FIG. 11, the correction coefficient output unit 10 previously stores m × n correction coefficients A11 to Amn in the ROM corresponding to FIG. Correction coefficient A
11 to Amn correspond to addresses # 11 to #mn, respectively, and the correction coefficient Aij of the address #ij corresponds to the group Gij in the i-th row and the j-th column in FIG. In the case of FIGS. 10 and 11,
The calculation / integration unit 9 calculates a correction coefficient A corresponding to the group Gij.
The image data D is corrected by multiplying ij by one image data Dij in the group Gij. Then, the calculation / integration unit 9 calculates m × n corrected image data D
Together. Therefore, the integration result S3 is Σ (Aij × D
ij).

The group for dividing the image data D is as follows:
6 and 10 and may correspond to each color, for example. A desirable mode for the case where the group corresponds to each color will be described in a second embodiment described later.

As described above, the APC signal generation circuit 7
When the integration result S3 is within the range of the reference value a or more, the power supplied from the driving power supply 2 to the driver 4 is suppressed to the predetermined value c.

Moreover, even if there is a variation in the power consumption for each group of the cells Cij of the matrix display panel 5, the correction type integrating circuit 8 determines the image data for determining the power consumption in consideration of the variation. D can be corrected in group units. Therefore, the APC signal generation circuit 7 can accurately determine the power consumption of the matrix display panel 5 from the integration result S3 for determining the power consumption. Therefore, the actual power consumption (supply power) of the matrix display panel 5 can be accurately suppressed to the predetermined value c.

In particular, in the case of FIG. 17, since there is variation for each row, it is effective to associate one row of image data with one group as shown in FIG.

In the above description, the correction type integrating circuit 8
The APC signal generation circuit 7 uses m × n pieces of image data Dij for one field (one vertical synchronization period) to determine the brightness of the entire image displayed on the matrix display panel 5. Not limited to this, for example, n pieces of image data for one row (one horizontal scanning period) may be used, or more than m × n pieces of image data exceeding one field may be used.

In the operation described above, the brightness of the entire image displayed on the matrix display panel 5 is determined for each field (one vertical synchronization period), and the brightness of the entire image displayed on the matrix display panel 5 is determined. (Power consumption). Therefore, depending on the video signal S1, for example, the brightness of the entire image is suppressed in units of one field,
There is a case where non-suppression is repeated, and the image flickers (a sudden change in brightness of the entire image). Thus, the APC signal generation circuit 7 is configured to suppress the brightness of the entire image when it is determined that the brightness of the entire image is within the range of the reference value a or more for one or more vertical synchronization periods. As a result, it is possible to suppress the fluctuation of the image.

The APC signal generation circuit 7 calculates the integration result S
3 was compared with one reference value a to distinguish the brightness of the entire image into two states of whether the image was bright or not.
The PC signal generation circuit 7 may distinguish the brightness of the entire image into three or more states by comparing the integration result S3 with a plurality of reference values. For example, the APC signal generation circuit 7 distinguishes the brightness of the entire image into three states by comparing the integration result S3 with two reference values a1 and a2, and changes the driving frequency according to each state. Thereby, as shown in FIG. 12, three stages (less than a1, a1
The actual power consumption (supply power) of the matrix display panel 5 can be suppressed according to the above (less than a2 and more than a2).

In the case of FIG. 9, the rate of change of the supplied power (the brightness of the entire image) with respect to the integration result S3 is the reference value a.
, The image flickers sharply. Therefore, for example, as shown in FIG. 12, the ratio of the change of the supply power to the integration result S3 is less than a1,
The values are set so as to be smaller than a2 and smaller than a2. As described above, the brightness of the image displayed on the matrix display panel 5 does not change abruptly by suppressing the power supply so that the rate of change in the power supply decreases as the integration result S3 increases. Therefore, it is possible to suppress the image flicker from becoming noticeable.

Further, for example, m × n correction coefficients A shown in FIG.
ij can be obtained as follows. The variation in the current flowing into each of the cells Cij is basically determined by the structure of the display panel, the material of the phosphor to be used, and, for example, a process for forming the phosphor (a method of manufacturing a phosphor layer) and the like. It can be predicted experimentally. Therefore, a plurality of matrix display panels 5 are prepared as samples. Then, each brightness value of the image data D is a fixed value (however, AP
1 is applied to the display device of FIG. 1, and as a result, the current value flowing through each of the image data D is measured and recorded on the matrix display panel 5 of a plurality of samples. . From the measured values, the average value d of the current flowing into each of the cells Cij is calculated. Then, the current value flowing into the ideal cell Cij having no variation is assumed to be e, and the correction coefficient Aij may be obtained from the ratio of the average value d of the current value actually flowing into the cell Cij to the ideal value e. Note that the actual measurement of the current value need not be performed for each pixel. For example, the measurement may be performed for each color of red, green, and blue, or the measurement may be performed for each group by dividing the m × n cells Cij of the matrix display panel 5 into a plurality of groups. With the correction coefficient Aij statistically obtained in this way, it is possible to accurately predict the drive current Is actually flowing into the matrix display panel 5 from the image data D (the integration result S3) corrected by the correction coefficient Aij. Therefore, since the integration result S3 and the driving current Is actually flowing into the matrix display panel 5 can be accurately correlated, the actual power consumption of the matrix display panel 5 can be accurately suppressed to the predetermined value c.

Embodiment 2 The first embodiment is a case where the present invention is applied to a matrix display panel 5 having a variation for each row or a matrix display panel 5 having a variation for each cell Cij. In the second embodiment, a matrix having a variation for each color is provided. This is a case where the present invention is applied to the display panel 5.

FIG. 13 shows a matrix display panel 5 applied in the second embodiment, which has a variation for each color. The PDP shown in FIG. 13 is disclosed in Japanese Patent Application No. 10-4057 by the present applicant.
6, which has the same structure as the PDP shown in No. 6.
By varying the cell width (substantially the area of the cell) for each color, the luminance balance for each color including the color temperature in the entire image is optimized.

The structure shown in FIG. 13 will be described. FIG. 13 shows three cells of red (R), green (G), and blue (B). The phosphor 25 includes a red phosphor 25.
R, green phosphor 25G, and blue phosphor 25B. Phosphor 25R, phosphor 25G and phosphor 25B
Are provided in red, green, and blue cells, respectively, and generate red, blue, and green visible lights, respectively, upon receiving ultraviolet rays generated by the discharge. Also, address electrodes Aj, Aj + 1,
Aj + 2 is a red phosphor 25 on a glass substrate 24, respectively.
R, blue phosphor 25B, and green phosphor 25G are provided. Usually, a region formed of three cells of red, green and blue in the glass substrate 21 and the glass substrate 24 is rectangular. 13 is conceptually the same as FIG.

The PDP as shown in FIG. 13 is characterized by the cell width. Of the red phosphor 25R, the blue phosphor 25B, and the green phosphor 25G, the blue phosphor 25B
The width of the cell in which is formed is larger than the width of the cell in which the other red phosphor 25R and green phosphor 25G are formed. For example, red cell width: blue cell width: green cell width = 1: 2: 1.

When such a structure is adopted, as the cell width increases, the length of the discharge gap in one line direction increases in proportion to the cell width, and the discharge space 27 also expands. The current flowing through the cell increases substantially in proportion to the width of the cell.

As described above, the matrix display panel 5 as shown in FIG. 13 has variations for each color. However, the concept of FIG. 10 can be applied to the matrix display panel 5 having variations in colors. However, in FIG. 10, since it is necessary to read out the correction coefficient and perform the operation every m × n, the correction type integrating circuit 8 must perform a huge amount of processing. Therefore, when the matrix display panel 5 has variation for each color, it is desirable to use the correction type integrating circuit 8 shown in FIG. The other parts of the display device according to the second embodiment are the same as those in FIG.

The correction type integrating circuit 8 shown in FIG.
R, 9G, 9B and an integrating unit 13 are included. The correction unit 9R
It includes an R integrating unit 11R and an R correcting unit 12R. The calculation / integration unit 9G includes a G integration unit 11G and a G correction unit 12G.
The calculation / integration unit 9B includes a B integration unit 11B and a B correction unit 12
B.

The operation of the correction type integrating circuit 8 shown in FIG. 14 will be described. The image data D included in the image signal S2 is divided into a red group GR, a green group GG, and a blue group GB. As in the first embodiment, the image data D is composed of m × n image data Dij (luminance values), and each of the image data Dij corresponds to each of m × n cells Cij (FIG. 2). . In one field, group G
The number of image data included in each of R, GG, and GB is
m × n / 3. The R integrator 11R receives the group GR, sums m × n / 3 image data in the group GR, and outputs the total SR. The G integrating unit 11G receives the group GG, sums m × n / 3 pieces of image data in the group GG, and outputs the total SG. B integrating unit 11B
Receives the group GB, sums m × n / 3 pieces of image data in the group GB, and outputs the total SB.

A red correction coefficient AR, a green correction coefficient AG, and a blue correction coefficient AB are preset in the R correction unit 12R, the G correction unit 12G, and the B correction unit 12B, respectively. The R correction unit 12R receives the total SR, performs multiplication (correction) of the total SR and the correction coefficient AR, and calculates the calculation result S
Ra is output. The G correction unit 12G receives the total SG, performs multiplication (correction) of the total SG and the correction coefficient AG, and outputs the calculation result SGa. The B correction unit 12B calculates the total SB
Then, the multiplication (correction) of the total SB and the correction coefficient AB is performed, and the calculation result SBa is output.

The integrator 13 calculates the calculation results SRa, SGa, S
Ba is received, these are integrated, and the integration result S3 is output.

In the second embodiment, the correction coefficients AR, AG and AB can be obtained as follows. In the case of the structure of FIG. 13, the above-described variations in the drive current to be applied to each pixel, differences in the thickness of each color of the phosphor, differences in the length of the connection wires connected to the electrodes of the PDP, etc. Since the influence of the cell width on the drive current is superior to the influence of the discharge current, etc., the correction is performed using the correction coefficient of each color determined based on the substantial cell width or the ratio of the cell width in each color. By obtaining the integrated result, it is possible to accurately obtain the correlation with the drive current (and power) even when the current value changes extremely for each cell.

For example, in the case of the structure shown in FIG. 13, as an example of the correction coefficient corresponding to each cell width, when the ratio of red cell width: blue cell width: green cell width is 1: 2: 1, The correction coefficient AR: correction coefficient AB: correction coefficient AG = 1: 2: 1 may be set. Note that, as shown here, the influence on the drive current depends on other conditions (variation in drive current to be given to each pixel, difference in thickness for each color of phosphor, connection wiring connected to the PDP electrode). In this case, the correction coefficient is basically given according to the ratio of each cell width as described above. When a condition other than the width greatly affects the drive current, the correction coefficient may be determined based on the condition, and it is needless to say that the present invention is not necessarily limited to the above case.

As described above, the correction type integrating circuit 8 shown in FIG.
Is simply the total SR × correction coefficient AR, total SG for each color.
X correction coefficient AG, total SB x correction coefficient AB, and multiply these operation results SRa, SGa and SBa. Therefore, compared with the case of FIG. 10, the correction type integrating circuit 8 of FIG. 14 does not need to perform an enormous amount of processing. Also, R
Each of the correction unit 12R, the G correction unit 12G, and the B correction unit 12B only needs to store one correction coefficient, and the configuration of the correction type integration circuit 8 can be made simpler and at low cost. Further, the above-described calculation for each color (total SR × correction coefficient A
R, total SG × correction coefficient AG, total SB × correction coefficient AB)
Can be performed simultaneously, so that the turnaround time from the input of the image signal S2 to the output of the integration result S3 can be shortened. This is effective when the number of image data is enormous.

Modified example. In the configuration of FIG. 1, the actual brightness of the entire image displayed on the matrix display panel 5 (the actual power consumption of the matrix display panel 5) can be accurately suppressed using the correction coefficient Aij. By correcting only the brightness of a part of the image using the correction coefficient Aij, it is also possible to suppress variations in the cell structure and luminance unevenness due to the length of the wiring. This is shown in FIG.
As shown in FIG. 5, the correction circuit 8a corrects the image signal S2 for an image, and the image signal S corrected by the correction circuit 8a.
2 is received by the display timing control circuit 6. The correction type integrating circuit 8 is the same as that of FIG. Other configurations in FIG. 15 are the same as those in FIG.

The correction circuit 8a is similar to the correction type integration circuit 8,
The image data D of the image signal S2 among the pixel signals S2 is received, and the data of each of the image data D is corrected using a correction coefficient corresponding to the data. However, the correction circuit 8a differs from the correction type integration circuit 8 in that Σ (Dij × A
ij), the correction is performed by dividing each image data Dij by the correction coefficient Aij (Dij / Aij). Therefore, the only difference between the image signal S2a output from the correction circuit 8a and the image signal S2 is that the luminance value is different. On the other hand, the correction type integrating circuit 8 includes the image signal S2 of the image signal S2 given in a predetermined period such as one vertical scanning period (or one horizontal scanning period) as in the first and second embodiments. Image data (image data corresponding to one pixel) to be weighted and integrated.

According to the display device shown in FIG. 15, the correction circuit 8a displays an image in consideration of the variation even if the brightness varies in the pixel group unit of the matrix display panel 5. Image data can be corrected in groups or cells. Therefore, an image according to the image data corrected for image display is displayed on the matrix display panel 5. Therefore, the actual image displayed on the display panel can be accurately corrected, and a very natural image can be obtained. Moreover, the correction circuit 8a outputs the image signal S2
Is corrected, the power supplied to the cells can be corrected for each cell, and variations in power consumption for each cell can be eliminated. Thereby, the APC signal generation circuit 7
Can accurately reduce the actual power consumption of the matrix display panel 5 to a predetermined value. The correction coefficient Aij used in the correction circuit 8a and the correction coefficient used in the correction type integration circuit 8 can be shared, and it is not necessary to add a memory for storing the correction coefficient Aij.

The display device does not need to include the driving power supply 2 and may connect the driving power supply 2 from outside.

The display device shown in FIGS. 1, 4, 14 and 15 may be embodied in any form. For example, the blocks shown in these figures are independent devices (circuits)
It may be constituted as. Alternatively, in FIG. 1, the APC signal generation circuit 7 and the display timing control circuit 6 may be configured as one device 3, and in FIG.
R, G integrating section 11G and B integrating section 11B are combined into one device 1
1, or the R correction unit 12R, the G correction unit 12G, and the B correction unit 12B may be configured as one device 12. Alternatively, a plurality of blocks may be formed on the same circuit board and configured as one device. Alternatively, for example, the functions of the correction type integrating circuit 8 and the correction circuit 8a may be realized by a computer program.

As an example of the case where a plurality of image data correspond to each of a plurality of cells, Embodiment 1
Although the case where one image data corresponds to one cell was considered, in addition to this, the case where one image data corresponds to a plurality of cells (for example, the second embodiment of Japanese Patent Application No. 10-40576 described above). In the case where two blue cells emit light simultaneously in response to one blue image data as shown in FIG.

As shown in FIG. 14, the idea of providing a plurality of correction units in parallel corresponding to a plurality of groups is as follows.
The present invention may be applied to a case other than a case where a group corresponds to each color.

A correction type integrating circuit 8 using a correction coefficient
May be other than simple multiplication.

Further, a display panel composed of self-luminous pixels applied to the present invention is a self-luminous type such as a display panel such as a fluorescent display tube or an electroluminescent panel in addition to a PDP. The present invention may be applied to a display panel having pixels.

[0083]

According to the first aspect of the present invention, since the correction is performed for each image data and then the integration is performed, the entire image displayed on the display panel can be corrected with high accuracy.

According to the second aspect of the present invention, image data can be corrected for each group.

According to the third aspect of the present invention, the present invention is particularly effective for a display panel in which the colors vary. Further, since the number of correction coefficients need only be the number of colors, the configuration is simplified.

According to the fourth aspect of the invention, the brightness of the entire image displayed on the display panel can be corrected with high accuracy.

According to the fifth aspect of the present invention,
Even if there is a variation in the cells of the display panel, the variation can be corrected on the image data, so that the actual power consumption of the display panel can be accurately suppressed.

According to the sixth aspect of the present invention, since the correction is performed for each image data and then the integration is performed, it is possible to configure an image data integration circuit that can accurately correct the entire image displayed on the display panel.

According to the seventh aspect of the present invention, it is possible to configure an image data integrating circuit capable of correcting image data in groups.

According to the eighth aspect of the present invention, it is possible to configure an image data integrating circuit which is particularly effective for a display panel having a variation for each color. Further, since the number of correction coefficients need only be the number of colors, the configuration of the image data integrating circuit is simplified.

According to the ninth aspect, the brightness of the entire image displayed on the display panel can be accurately corrected.

According to the tenth aspect of the present invention, the correction coefficient output section can be composed of, for example, a ROM, and the configuration of the image data integrating circuit is simplified.

According to the eleventh aspect, since the correction can be performed in parallel for each group, the turnaround time of the image data integrating circuit can be shortened. This is effective when the number of pixel image data is enormous.

According to the twelfth aspect of the present invention, after correction is performed for each image data, integration is performed, and by using the result of the integration, even if cells of the display panel have variations, Since the variation can be corrected on the image data, the supplied power can be appropriately suppressed, so that the actual power consumption of the display panel can be accurately suppressed.

According to the thirteenth aspect, since the brightness of the image displayed on the display panel does not change rapidly, the flickering of the image can be suppressed.

According to the fourteenth aspect of the invention, it is possible to effectively suppress the power consumption of a display panel having a different cell area for each color.

According to the fifteenth aspect, after performing correction for each image data and using the result of this correction, even if the cells of the display panel vary, the image can be accurately output. Can be corrected. Moreover,
Since the image is displayed by performing the correction for each image data, the supplied power suppressing unit can accurately suppress the supplied power, and can accurately suppress the actual power consumption of the display panel.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a display device according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram of a self-luminous matrix display panel.

FIG. 3 is a partial cross-sectional view of a matrix display panel.

FIG. 4 is a block diagram showing a correction type integrating circuit according to the first embodiment of the present invention.

FIG. 5 is a data structure diagram of image data included in an image signal.

FIG. 6 is a diagram for explaining an operation of the correction type integrating circuit according to the first embodiment of the present invention;

FIG. 7 is a data structure diagram of a correction coefficient stored in a correction coefficient output unit according to the first embodiment of the present invention.

FIG. 8 is a graph showing a relationship between an integration result and a driving frequency according to the first embodiment of the present invention.

FIG. 9 is a graph showing a relationship between an integration result and supply power according to the first embodiment of the present invention.

FIG. 10 is a diagram for explaining an operation of the correction type integrating circuit according to the first embodiment of the present invention;

FIG. 11 is a data structure diagram of correction coefficients stored in a correction coefficient output unit according to the first embodiment of the present invention.

FIG. 12 is a graph showing a relationship between an integration result and supply power according to the first embodiment of the present invention.

FIG. 13 is a partial perspective view of a matrix display panel according to Embodiment 2 of the present invention.

FIG. 14 is a block diagram showing a correction type integrating circuit according to a second embodiment of the present invention.

FIG. 15 is a block diagram showing a display device according to a modification of the present invention.

FIG. 16 is a block diagram showing a conventional display device.

FIG. 17 is a conceptual diagram showing a connection between a matrix display panel and a driver for driving the matrix display panel.

[Explanation of symbols]

5 matrix display panel, 7 supply power suppression section, 8
Correction type integration circuit (image data integration circuit), D image data, Gi, Gij, GR, GG, GB group, Ai, A
ij, AR, AG, AB correction coefficient, R red, G green,
B yellow, 9 operation / integration unit (correction integration unit), 9R, 9
G, 9B correction unit, 10 correction coefficient output unit, 13 integration unit, 100 drive circuit, 101 image display control unit.

Claims (15)

[Claims] 1. A method of integrating a plurality of image data corresponding to each of a plurality of cells constituting a display panel, the method comprising: using a correction coefficient corresponding to the image data for each of the plurality of image data. An image data integration method, wherein the integration of the plurality of image data is performed after correcting the image data. 2. The method according to claim 1, wherein the plurality of image data is divided into a plurality of groups, and one of the plurality of groups corresponds to one of the correction coefficients. 3. The image data integration method according to claim 2, wherein the plurality of groups correspond to each color. 4. The image data according to claim 1, wherein the image data includes a luminance value.
4. The image data integration method according to any one of the above items 3 to 3. 5. The image data integration method according to claim 1, further comprising: reducing power supplied to the display panel according to a result of the integration. 6. An image data accumulating circuit for accumulating a plurality of image data corresponding to each of a plurality of cells constituting a display panel, the circuit receiving the plurality of image data, and An image data integrating circuit, wherein the image data is corrected using a correction coefficient corresponding to the image data, and then the plurality of image data are integrated. 7. The image data accumulating circuit according to claim 6, wherein said plurality of image data are divided into a plurality of groups, and one of said plurality of groups corresponds to one of said correction coefficients. 8. The image data integrating circuit according to claim 7, wherein the plurality of groups correspond to each color. 9. The image data according to claim 6, wherein the image data includes a luminance value.
9. The image data integration circuit according to any one of items 1 to 8. 10. The image data integration circuit includes: a correction integration unit that performs the correction and integration; and a correction coefficient output unit that stores the correction coefficient in advance and outputs the correction coefficient to the correction integration unit. The image data integrating circuit according to claim 6. 11. The image data multiplying circuit is provided in parallel corresponding to the group, a plurality of correction units each receiving a corresponding one of the image data divided into the group and performing the correction. The image data integrating circuit according to claim 7, comprising: 12. An image data accumulating circuit according to claim 6, wherein the display panel is driven to drive the display panel to display an image represented by the plurality of image data on the display panel. A display device comprising: an image display control unit that performs power supply; and a supply power suppression unit that suppresses supply power supplied to the display panel according to a result of the integration performed by the image data integration circuit. 13. The display device according to claim 12, wherein the supply power suppression unit suppresses the supply power such that the larger the result of the integration, the smaller the rate of change in the supply power. 14. The display device according to claim 12, wherein the display panel has a different cell area for each color. 15. A display panel, receiving a plurality of image data corresponding to each of a plurality of cells constituting the display panel, and using a correction coefficient corresponding to the image data for each of the plurality of image data. A correction circuit for correcting image data, an image data integration circuit for receiving the plurality of image data and integrating the image data, and the display for displaying an image indicated by the plurality of image data on the display panel A display device comprising: an image display control unit that drives a panel; and a supply power suppression unit that suppresses supply power supplied to the display panel according to a result of the integration of the image data integration circuit.