JP2000249728A - Peak hold circuit or bottom hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve rise / fall time with a relatively simple circuit and a small number of elements, to accurately control a droop rate (reduction rate), and to maintain accuracy. It is an object of the present invention to realize a peak hold circuit. SOLUTION: In a feedback type peak hold circuit for providing feedback by providing a capacitance means C1 and an emitter follower Q5 at an output stage of a differential amplifier circuit, npn transistors Q1 and Q5 are provided.
Clamp circuits P4 and Q4 for clamping the collector of the feedback transistor Q2 of the differential amplifier circuit composed of the Pn2 and the pnp transistors P1 and P2 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak hold circuit or a bottom hold circuit, and more particularly to a peak hold circuit or a bottom hold circuit in which a response speed, a reduction rate, and accuracy are considered.

[0002]

2. Description of the Related Art FIGS. 3 to 7 show circuit examples (a) and operation waveforms (b) of a conventional peak hold circuit or bottom hold circuit. In the operation waveform (b), the solid line is the input waveform, and the dotted line is the held output waveform.

[0003] Of FIGS. 3 to 7, FIGS. 3 to 5 correspond to a system called an emitter follower system. Of these, in the method of FIG. 3, a capacitance is used for the load of the transistor emitter follower, and a current source or a resistor is added in parallel with the load capacitance to control the droop rate (reduction rate) of the bias and the holding voltage.

The circuit shown in FIG. 3 can be composed of a single transistor. However, the output voltage is shifted by a base-emitter voltage (Vbe).
A configuration in which a pn transistor and a pnp transistor are combined is a peak hold circuit in FIG. 4 and a bottom hold circuit in FIG.

The circuits shown in FIGS. 3 to 5 have a high response speed because of their simple circuit configuration. However, in the circuit of FIG. 3, the output voltage shifts by Vbe, and in the circuits of FIGS. 4 and 5, the Vbe of the transistor fluctuates, and the effect appears on the output, so that the accuracy is not good. Also, in the circuits of FIGS.
Although the difference of Vbe can be canceled by combining the n transistor and the pnp transistor, there is a possibility that the mismatch of Vbe may cause an error.

FIGS. 6 and 7 show a feedback type peak hold circuit and a bottom hold circuit with respect to the emitter follower method shown in FIGS. In this method, the output stage of the differential amplifier is set to an emitter follower type and feedback is applied. By applying feedback in this way, accuracy can be improved. However, since the input side and the feedback side become unbalanced during the hold, the circuit is saturated as it is, and the response to the next transient signal deteriorates.

Further, in the conventional system shown in FIGS. 3 to 7, no matter which circuit is used, the droop rate (reduction rate) is affected by the input current (base current) of a buffer circuit or the like connected to its output. There is a problem of variation. For example, FIG.
In the circuit of FIG. 8, as shown in FIG. 8, if the sum of the base current Ib1 of the transistor on the feedback side and the input current Ib2 of the buffer circuit is not 0, there arises a problem that the value of the convergence destination of the hold voltage is different and an error occurs.

[0008]

As described above, in the conventional peak hold circuit or bottom hold circuit, the output voltage is shifted by the base-emitter voltage, or the base-emitter voltage mismatch causes an error. In addition, the input side and the feedback side become unbalanced during the hold, resulting in poor response to the next transient signal, and the accuracy of the droop rate (reduction rate) cannot be maintained. The present invention solves this problem by using a relatively simple circuit and a small number of elements to improve the rise / fall time and accurately control the droop rate (decrease rate).
Another object is to realize a peak hold circuit and a bottom hold circuit that can maintain accuracy.

[0009]

In order to achieve the above object, the present invention provides a feedback type peak hold circuit or bottom hold circuit for providing feedback by providing a capacitor means and an emitter follower means at an output stage of a differential amplifier circuit. And a clamping means for clamping the collector of the feedback transistor of the differential amplifier circuit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a peak hold circuit and a bottom hold circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the present invention, taking a peak hold circuit as an example. In FIG. 1, (a) is a circuit diagram,
(B) shows the operation waveform. FIG. 2 shows a circuit diagram (a) of a bottom hold circuit according to another embodiment of the present invention and an operation waveform (b) thereof. 1 and 2, Q1
Q1 to Q7 are npn transistors, P1 to P7 are pnp transistors, I1 to I4 are current sources, C1 is a capacitor, S
Is an input signal source.

In FIG. 1A, a portion composed of npn transistors Q1, Q2, Q5, pnp transistors P1, P2, current sources I1, I3 and a capacitor C1 operates in the same manner as the feedback type peak hold circuit of FIG. do. Also, the collector voltage of the npn transistor Q2 is pn for the npn transistor Q3 and the pnp transistor P4.
This is a circuit for clamping so as not to be lower than the base voltage of the p transistor P4.

FIG. 1 (b) shows the result (dotted line) when the input signal (solid line) such as a binary signal AC modulation wave is peak-held by the circuit of FIG. 1 (a). In FIG. 1B, T1 indicates a follow-up period for the input voltage, and T2 indicates a peak value holding period. As described above, by clamping the collector of the npn transistor Q2, npn is obtained during the period T2 in FIG.
It is possible to prevent the transistor Q2 from being saturated. If the npn transistor Q2 is not saturated, the response from the peak value holding period T2 to the following period T1 can be performed quickly. Since the clamp voltage at this time follows the base voltage of the pnp transistor P4, there is no possibility that the dynamic range is impaired.

By the way, in the circuit of FIG. 1A, in the follow-up period T1, the collector potential of the npn transistor Q2 is higher than its base potential by 1 Vbe (base-emitter voltage), so that the npn transistor Q3 is turned off. is there. On the other hand, the pnp transistor P3 supplies a current to the pnp transistor P4. If the base current of the npn transistor Q3 is sufficiently small, the same current flows through the pnp transistor P3 and the pnp transistor P4. Further, the base current of the pnp transistor P3 and n
The base current of pn transistor Q4 is equal, and the base current of npn transistor Q4 is
2, the result is I2 / {1 + hFE (Q4)}. Here, hFE (Q4) is the h of the npn transistor Q4.
Indicates FE (current amplification factor).

In the period T2 in which the peak value is held, n
The base potentials of the pn transistors Q1 and Q2 become unbalanced, the npn transistor Q1 is turned off, and all current flows to the npn transistor Q2. If the input stage of the buffer amplifier of the next stage is of the npn type, a current of I4 / 2 flows through the npn transistor Q6. In the period T2 in which the peak value is held, the npn transistor Q5 is off, so the current Ic flowing through the capacitor C1 is:

Ic = I3 + Ib (P4) −Ib (Q2) −Ib (Q6) (1) Here, Ib (Q2) indicates a base current of the npn transistor Q2, and the same applies to other cases. Each Ib
Represents only the magnitude, and the direction of the current is represented by + and-before the value. Where the pnp transistor P
3 and the pnp transistor P4 have the same current, so that if the current amplification factors are equal, Ib (P
4) = Ib (P3), and the base current of the pnp transistor P3 and the base current of the npn transistor Q4 are equal, so that Ib (P4) = Ib (P3) = Ib
(Q4). Further, assuming that the value of I2 is I1 + I4 / 2, the equation (1) becomes

Ic = I3 + Ib (P4) −Ib (Q2) −Ib (Q6) = I3 + Ib (Q4) −Ib (Q2) −Ib (Q6) = I3 + (I1 + I4 / 2) / {1 + hFE (Q4)} − I1 / {1 + hFE (Q2)}-I4 / 2 {1 + hFE (Q6)} (2)

Here, assuming that the current amplification factors of the respective transistors are equal, hFE (Q4) = hFE (Q2) = hFE (Q6).

Ic = I3 (3)

This is because the discharge of the capacitor is equal to the reference current I3
And the error factor due to the base current has disappeared. However, the condition is that there is no relative variation in the current amplification factor hFE of each transistor.

While the above description has been made with reference to the peak hold circuit of FIG. 1, the same concept can be applied to the bottom hold circuit shown in FIG. 2 only by changing the transistor from npn to pnp.

Although the circuits shown in FIGS. 1 and 2 have been described using only transistors in order to explain the operation of the circuits, the circuits shown in FIGS.
Similar results can be obtained even if a resistor is inserted in the circuit or the type of the current mirror or the current source is different.

As described above, according to the present embodiment: 1) Since the saturation of the differential amplifier is prevented by clamping the collector of the transistor on the feedback side, high speed operation can be realized. 2) By clamping so that the clamp voltage is equal to the base voltage of the feedback transistor of the differential amplifier circuit,
The dynamic range can be maintained. 3) By canceling the base current, the accuracy of the droop rate (reduction rate) can be maintained. 4) In addition, since there is no error in the base current, the capacitance can be reduced, and the capacitance can be easily built in the IC. 5) Because of the feedback type configuration, high accuracy can be maintained. 6) It can be configured with a relatively small number of elements. There are advantages such as.

[0024]

As described above, according to the first aspect of the present invention, a feedback type peak hold circuit or bottom hold circuit for providing feedback by providing a capacitor means and an emitter follower means at an output stage of a differential amplifier circuit. And a clamping means for clamping the collector of the feedback transistor of the differential amplifier circuit. As a result, saturation of the differential amplifier can be prevented, and the response of the differential amplifier circuit can be made quick to realize high-speed operation.

According to a second aspect of the present invention, the clamping means clamps the clamp voltage so that the clamp voltage becomes equal to the base voltage of the feedback transistor of the differential amplifier circuit. Thereby, the dynamic range can be maintained without the dynamic range being deteriorated even when the clamp is performed.

According to a third aspect of the present invention, the clamping means is constituted by a transistor, and the base of the transistor constituting the clamping means is the base of the feedback-side transistor of the differential amplifier circuit and the input transistor of the next-stage buffer circuit. , And the base currents of the connected transistors are configured to cancel each other. As a result, the droop rate (decrease rate) can be set arbitrarily and its accuracy can be maintained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a peak hold circuit of the present invention and an operation waveform diagram thereof.

FIG. 2 is a circuit diagram of one embodiment of a bottom hold circuit of the present invention and an operation waveform diagram thereof.

FIG. 3 is a circuit diagram of a conventional peak hold circuit and an operation waveform diagram thereof.

FIG. 4 is a circuit diagram of a conventional peak hold circuit and its operation waveform diagram.

FIG. 5 is a circuit diagram of a conventional bottom hold circuit and an operation waveform diagram thereof.

FIG. 6 is a circuit diagram of a conventional peak hold circuit and an operation waveform diagram thereof.

FIG. 7 is a circuit diagram of a conventional bottom hold circuit and an operation waveform diagram thereof.

FIG. 8 is an explanatory diagram showing a reduction rate and a base current error in a conventional peak hold circuit.

[Explanation of symbols]

C1 ... Capacitor, I1 to I4 ... Current source, P1 to P7 ...
pnp transistor, Q1 to Q7 ... npn transistor, S ... input signal source

Claims (3)

[Claims] In a feedback type peak hold circuit or bottom hold circuit for providing feedback by providing a capacitor means and an emitter follower means at an output stage of a differential amplifier circuit, a collector of a feedback transistor of the differential amplifier circuit is clamped. A peak hold circuit or a bottom hold circuit, comprising a clamp means. 2. The peak hold circuit or the bottom hold circuit according to claim 1, wherein a clamp voltage of said clamp means is made equal to a base voltage of a feedback transistor of said differential amplifier circuit. 3. The clamp means is constituted by a transistor, and a base of the transistor constituting the clamp means is connected to a base of a feedback-side transistor of the differential amplifier circuit and a base of an input transistor of a next-stage buffer circuit, respectively. 2. The peak hold circuit or bottom hold circuit according to claim 1, wherein the base currents of the connected transistors are mutually canceled.