JP2000244924A - Data compression / decompression device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To speed up encoding / decoding operation. SOLUTION: A plurality of processor cores 102 process a plurality of tile data in parallel. Each processor core 1
02 is a reversible wavelet transform SS, DS, SD,
Tile memory 112, 113, 1 for each component of DD
14, 115 and code memories 122, 123, 124 for DS, SD, DD components, three sets of independently operating context models 116, 117, 118 and FSM
DS, SD, D with coder 119, 120, 121
The encoding and decoding of each component of D are performed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for compressing and expanding image data and the like, and more particularly, to a device for compressing and expanding data using two-dimensional reversible wavelet transform.

[0002]

2. Description of the Related Art As a compression / decompression technique for image data or the like, a method based on a combination of a two-dimensional reversible wavelet transform, a context model process and an entropy coding / decoding process as described in Japanese Patent Application Laid-Open No. 9-112168. It has been known. FIG. 6 shows the basic configuration of a color image data compression / decompression device using this method.
In FIG. 6, reference numeral 1000 denotes a color space conversion unit which performs conversion from, for example, an RGB color system or a YMC color system to a YUV color system or vice versa. 1001 is a two-dimensional reversible wavelet transform unit, 1002 is a context model unit, 1003 is an FSM coder, and 1004 is a tag processing unit, which performs compression and decompression processing of image data.

The images to be processed include primary color R (red), G (green), B (blue), and A (primary color) used for video signals and the like.
A color image composed of (alpha) components and a color image composed of Y (yellow), M (magenta), C (cyan), and K (black) components of a complementary color system used for a printer or the like. As shown in FIG. 7, a color image is generally divided into tiles of component images (here, primary color systems), and tiles (for example, R00, R0).
1,. . . . ) Is processed as a unit.

At the time of encoding, data of each tile of each component is input to a color space conversion unit 1000, where the data is subjected to color space conversion, and a two-dimensional reversible wavelet transform unit 1001 performs two-dimensional reversible wavelet transform (forward transform). ) Is applied to perform spatial division into frequency bands, and then bits to be encoded (called target bits) are determined in an order based on the alignment information (information indicating the order of encoding) specified by the user. , A context model unit 1002 generates a context (context) from surrounding bits of the target bit (the template is shown in FIG. 8). The FSM coder 1003 is an entropy encoder / decoder based on a finite state machine, performs encoding by probability estimation from its context and target bits, and generates a code stream for the tile of the component. Similar processing is performed for each tile of the four components of the image data. A tag processing unit 1004 adds and interprets tag information. At the time of encoding, the FSM coder 1
The code stream of each tile of each component generated in 003 is combined into one code stream, and a process of adding a tag to the code stream is performed. FIG. 9 shows a format of a code stream output from the tag processing unit 1004.

[0005] At the time of decoding, image data is generated from the code stream of each tile of each component, contrary to the encoding. In this case, the tag processing unit 1004 interprets the tag information added to the code stream input from the outside, decomposes the code stream into a code stream of each tile of each component, and a code stream of each tile of each component. The decoding process is performed every time. Bits to be decoded in the order based on the tag information in the code stream (target bits)
And the context model part 1
At 002, a context is generated from the sequence of peripheral bits (already decoded) at the target bit position. In the FSM coder 1003, decoding is performed by probability estimation from the context and the code stream to generate a target bit, and the target bit is written in the target bit position. Since the data decoded in this way is spatially divided for each frequency band, the two-dimensional reversible wavelet transform unit 1001 performs two-dimensional reversible wavelet inverse transform to obtain each component of the image data. The tile is restored. The restored data is converted into the original color system data by the color space conversion unit 1000.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to increase the speed of a data compression / expansion apparatus of the above-mentioned type.

[0007]

A feature of the first aspect of the present invention is that a plurality of sets of means for context model processing and entropy coding / decoding processing are used to perform three types of two-dimensional reversible wavelet transform of image data and the like. Of the high frequency components or decoding of the encoded data of the three types of high frequency components in parallel.

[0008] A feature of the invention of claim 2 is that a plurality of tile cores such as image data are compressed and decompressed in parallel by a plurality of processor cores operating independently, and context model processing and entropy coding are performed in each processor core. Using a plurality of means for decoding processing, encoding of three types of high frequency components by two-dimensional reversible wavelet transform of tile data or decoding of encoded data of three types of high frequency components is performed in parallel. There is a configuration to perform.

According to a third aspect of the present invention, in the configuration of the second aspect, each processor core is provided with a two-dimensional reversible wavelet transform unit for tile data such as image data.
A tile memory for storing low-frequency components and three types of high-frequency components by two-dimensional reversible wavelet transform of tile data, and a code memory for storing encoded data of three types of high-frequency components, respectively. And three sets of independently operating context model processing means and entropy coding / decoding means for coding three types of high frequency components or decoding coded data of three types of high frequency components Are all mounted on the same IC chip.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 100 denotes an image data compression / decompression device according to the present invention, and reference numeral 200 denotes a personal computer including a CPU 201, a main memory 202 and the like. The image data compression / decompression device 100 is mounted on an extension board of the personal computer 200 and is connected to the personal computer 200 via a bus 203 such as a PC bus.

The image data compression / expansion apparatus 100 includes four processor cores 102 (102_1 to 102_1) operating in parallel.
2_4), a color space conversion unit 103 for color space conversion of image data, a main tag processing unit 104 for adding and interpreting main tag information of a code stream, a color space conversion unit 103 and a main tag processing unit 104 I / O selector 10 for switching data input / output between bus and bus 203
5 and a controller 106 for controlling the operations of the above-described units and the entire apparatus.

FIG. 2 shows each processor core 102 in FIG.
It is a block diagram of. As shown in FIG. 2, each processor core 102 includes a two-dimensional reversible wavelet transform unit 110,
Tile memories 112, 113, 114, 115, context model units 116, 117, 118, FSM coders 119, 120, 121, code memories 122, 12
3, 124, and a tile tag processing unit 125 for adding or analyzing tile tag information of the code stream.

Two-dimensional reversible wavelet transform unit 110
Performs the reversible wavelet forward transform for each adjacent four pixels on the data of a certain tile having a certain component input from outside, that is, the original image SS0 in FIG. 3A at the time of encoding, as shown in FIG. The low frequency component SS1 and the high frequency components DS1, SD1, and DD1 of the first layer are separated. When performing encoding of two or more hierarchies, the reversible wavelet forward transform is performed on the low-frequency component SS1, and as shown in FIG.
And high frequency components DS2, SD2, DD2.
Similarly, the reversible wavelet forward transform is performed on the low frequency component SS2, and as shown in FIG. 3D, the low frequency component SS3 and the high frequency components DS3, SD3, DD
Separate into 3. High frequency components DSi, SD of the i-th hierarchy
i and DDi are the original image data, that is, the high frequency components of the low frequency component SSi-1, and the area thereof is one fourth of the original image data. Similarly, the low frequency component SS
i is the original image data, that is, the low-frequency component of SSi-1;
Its area is one fourth of the original image data. In the case of i-th layer coding, 3 × i high frequency components DSi, SD
i, DDi,. . . , DS1, SD1, DD1 are to be coded, and the low frequency components SSi are not coded,
Sent as is. In order to perform the reversible wavelet transform, when the original image SS0 has a depth of b bits / pixel, the data depth of the low frequency component (SS) remains b bits, but the high frequency component (DS , SD) is (b + 2)
Bit depth is required, and high frequency components (D
D) requires a depth of (b + 4) bits.

In FIG. 2, tile memories 112 and 11
3, 114 and 115 are 4 of one tile image, respectively.
It is used to store various frequency band components.
The tile memory 112 is for low frequency components (SS), the tile memory 113 is for high frequency components (DS), the tile memory 114 is for high frequency components (SD), and the tile memory 115 is high frequency components (DD). It is for. The code memories 122, 123, and 124 are memories for storing encoded data of high frequency components (DS, SD, and DD), respectively.

The tile memory 113, the context model unit 116, the FSM coder 119, and the code memory 122
, Tile memory 114, context model unit 11
7, a set of the FSM coder 120 and the code memory 123;
Tile memory 115, context model unit 118, F
The set of the SM coder 121 and the code memory 124 operate independently of each other, and execute encoding of the high frequency components of DS, SD, and DD or decoding of the encoded data in parallel. That is, in each processor core 102, three types of high frequency components (DS, SD, DD)
Are parallelized.

Next, the operation of the image data compression / expansion apparatus 100 will be described on the assumption that each component of a color image is divided into tiles as shown in FIG.

First, the case of encoding (compression) will be described. The color image data is stored in the main memory 202 of the personal computer 200 and is taken into the image data compression / decompression device 100 via a bus 203 such as a PCI bus. As described above, since the image data compression / expansion device 100 has the four independently operating processor cores 102, the four tile images can be encoded by parallel processing.

According to one embodiment of the present invention, as shown in FIG. 4, tiles of different components are allocated to the four processor cores 102, and the tiles of the four components are processed in parallel. In this case, the component R,
The data of G, B, and A are each the first tile R0.
The image data is sequentially taken into the image data compression / decompression device 100 from 0, G00, B00, and A00. The tile image of each component is distributed to the corresponding processor core 102 by the I / O selector 105. The four processor cores 102 operate independently, and fetch and process the tile images (to which the color space conversion unit 1003 performs color space conversion as necessary) to which the tile images are assigned.

In each processor core 102, a two-dimensional reversible wavelet forward transform is performed on the tile image by the reversible wavelet transform unit 110, and the low frequency components (SS) are stored in the tile memory 112 and the high frequency components (DS). ) Is stored in the tile memory 113, and the high frequency component (SD) is stored in the tile memory 114.
D) is written to the tile memory 115, respectively.
The high frequency components (DS, SD, and DD) are respectively transmitted to three sets of context model units 116 and 11 that operate independently.
7, 118 and the FSM coder 119, 120, 121 in parallel processing. The encoding operation of each high frequency component is as described above. For example, for the high frequency component DS, the context model unit 116 determines target bits according to the alignment information specified by the user, sends the target bits on the tile memory 113 to the FSM coder 119, and sets the peripheral bits of the target bits. Is generated using a template (see FIG. 8) prepared in advance, and this context is sent to the FSM coder 119. The FSM coder 119 performs coding by probability estimation from the given context and target bits, and outputs a code. The code output from the FSM coder 119 is stored in the code memory 122. The other high frequency components (SD, DD) are similarly encoded, and the codes are stored in the code memories 123, 124, respectively. Then, the low frequency components (SS) on the tile memory 112 and the code memories 122, 123, 1
The code stream of the high frequency components (DS, SD, DD) on 24 is assembled into one code stream to which tile tag information is added by the tile tag processing unit 125 and output to the outside.

Thus, the four processor cores 1
02, the encoding process for one tile of each of the R, G, B, and A components is executed in parallel. This is completed, and a code stream with tile tag information is output from each processor core 102. These four code streams are assembled into one code stream under the control of the main tag processing unit 104, and are added to the beginning and end. I / O selector 10 with main tag information added
5 to the main memory 202 of the personal computer 200 via the bus 203.

As described above, the processing of the four components is executed in parallel by the four processor cores 102. Further, for each component, the high frequency components (DS, SD, D
Since the processing for D) is executed in parallel, an extremely high-speed encoding operation is possible.

According to another embodiment of the present invention, FIG.
As shown in (4), four tiles of the same compote are allocated to four processor cores 102, and four tiles of one component are processed in parallel. In this case, for example, the data of the component R is tiles R00, R0
1, R02, R03,. . . Are sequentially taken into the image data compression / decompression device 100 and distributed to each processor core 102 by the I / O selector 105. Each processor core 102 takes in and processes the assigned tile image (which is subjected to color space conversion by the color space conversion unit 1003 as necessary). In each processor core 102, as described above, the high frequency components (DS, SD, D
The encoding of D) is performed in parallel, and a code stream with tile tag information is output. Four processor cores 10
2 is assembled into one code stream to which main tag information is added under the control of the main tag processing unit 104, and is returned to the main memory 202 of the personal computer 200.

Also in this case, four tiles are coded by parallel processing for each component, and high frequency components (DS, SD,
Since the processing for DD) is performed in parallel, an extremely high-speed encoding operation is possible.

Next, decoding (decompression) will be described.
The code stream to be processed is stored in the main memory 202 of the personal computer 200, and is stored in a bus 203 such as a PCI bus.
Is taken into the image data compression / decompression device 100 via This code stream is, for example, a code stream in which one tile of four components is encoded in the order shown in FIG. 4 or four tiles of one component are encoded in the order shown in FIG. Code stream.

In the image data compression / decompression device 100,
The main tag information of the code stream is I / O selector 1
05 and is interpreted by the main tag processing unit 104. The main tag processing unit 104 controls the I / O selector 105 according to the content of the main tag information, so that the code stream is decomposed in tile units and distributed to each processor core 102.

In each processor core 102, the tile tag information of the code stream is interpreted by the tile tag processing unit 125 to write the low frequency component (SS) data in the code stream to the tile memory 112, and the high frequency component The encoded data of (DS, SD, DD) is written into the tacho memories 122, 123, and 124, respectively. Then, these high frequency components (D
(S, SD, DD) encoded data is decoded by three sets of independently operated context models 116, 117, 1
18 and the FSM coders 119, 120, 121 in parallel. Regarding the decoding order, the target bit position is determined according to the alignment information included in the tile tag information. In each of the context model units 116, 117, and 118, peripheral bits of the target bit (already decoded and stored in the tile memories 113 and 11)
4, 115 or a sequence of known bits), a context is generated using a template prepared in advance, and the context is generated by the FSM coder 11.
9, 120, 121 and the FSM coder 11
The target bits generated in 9, 120 and 121 are written to target positions in the tile memories 113, 114 and 115. In the FSM coder 119, 120, 121, the given context and the code memory 122, 1
Target bits are generated by the probability estimation from the encoded data in the
6, 117, 118. In this way, the high frequency components (DS, SD, DD) are restored to the tile memories 113, 114, 115 by parallel processing. And
The two-dimensional reversible wavelet inverse transform is performed by the reversible wavelet transform unit 110 on the high frequency component data and the low frequency component (SS) data on the tile memory 11. In the case of a code stream coded up to the i-th layer, the reversible wavelet inverse is applied to the decoded high-frequency components (DSi, SDi, DDi) of the ith layer and the uncoded low-frequency components (SSi). By performing the conversion, a low frequency component (SSi-1) of the (i-1) th layer is generated. The low frequency component (SSi-1) and the high frequency component (DSi-1, SDi)
-1, DDi-1), the inverse reversible wavelet transform is performed, and the low-frequency component (SSi) of the (i-2) th layer is
-2) is generated. Thereafter, by repeating the same inverse transformation, the low frequency component (SS1) and the high frequency component (DS1, SD1,
DD1) is the tile memory 112, 113, 114, 11
5 by performing an inverse reversible wavelet transform on these data.
The original image (SS0) of one tile shown in (a) is restored and output to the outside.

The decoding operation as described above is executed in parallel by the four processor cores 102, and the obtained original image data of each tile is subjected to inverse color space conversion by the color space conversion unit 103 as necessary. Then, the main memory 20 of the personal computer 200 is transmitted via the I / O selector and the bus 203.
Returned to 2.

As described above, the four processor cores 102
4 of the same component or different components
Since the decoding of one tile is performed in parallel, and the decoding of the high frequency components (DS, SD, DD) is also performed in parallel in each processor core 102 for each tile, very high-speed decoding is performed. Operation is possible.

According to a preferred embodiment of the present invention, each of the above-described processor cores 102 is mounted on the same IC chip except for at least a portion other than the tile tag processing section 125. According to such an implementation, the reversible wavelet transform unit 110 and the tile memories 112, 113, 114,
Since the data transfer width with the data 115 can be easily increased as compared with the case where they are mounted on separate IC chips, the number of transfer cycles can be reduced and the wavelet transform time can be shortened. Context model part 1
16, 117, 118 and tile memories 113, 114,
115 and the FSM coder 11
8, 120, 121 and code memories 122, 123, 1
24 can easily increase the data transfer width, so that three types of high frequency components (DS, SD, DD)
In this case, the effect of improving the speed due to the parallelization of the encoding or the decoding can be maximized.

Although the image data compression / decompression device according to the present invention described above has a configuration in which four processor cores are operated in parallel, the number of processor cores can be increased or decreased. For example, a processor core (or
A configuration with only one processing unit) is also possible.
This is also included in the present invention. In this case, it is not possible to expect high speed by parallel processing of a plurality of tiles by a plurality of processor cores, but the advantage of high speed by parallel processing of high frequency components (DS, SD, DD) is obtained.

Although the image data compression / decompression device has been described, the present invention can be similarly applied to a data compression / decompression device for two-dimensional data other than images.

[0033]

As described above, according to the first aspect of the present invention, the encoding and decoding of the high frequency components (DS, SD, DD) are performed in parallel with each other in comparison with the case without parallelization. Can be approximately three times faster. According to the second aspect of the present invention, in addition to parallel encoding and decoding of high frequency components in each processor core, parallel processing of a plurality of processor cores enables higher-speed processing. According to the invention of claim 3, the data transfer width between the tile memory and the reversible wavelet transform means in each processor core, the data transfer width between the tile memory and the context model processing means, the code memory and the entropy coding Since it is possible to easily increase the data transfer width with the decoding means, it is possible to obtain effects such as being advantageous for speeding up the internal processing of the processor core.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of each processor core of the image data compression / decompression device.

FIG. 3 is a diagram for describing space division of a two-dimensional reversible wavelet transform.

FIG. 4 is a diagram illustrating an example of a method of assigning tiles to four processor cores.

FIG. 5 is a diagram illustrating another example of a method of assigning tiles to four processor cores.

FIG. 6 is a block diagram showing a basic configuration of a compression / decompression processing method according to the present invention.

FIG. 7 is a diagram illustrating a color image including four components and tile division thereof.

FIG. 8 is a diagram showing an example of a template for determining a context.

FIG. 9 is a diagram showing a format of a code stream.

[Explanation of symbols]

100 image data compression / decompression device 102 (102_1, ..., 102_4) processor core 103 color space conversion unit 104 main tag processing unit 105 I / O selector 106 controller 110 reversible wavelet conversion unit 112, 113, 114, 115 tile memory 116 , 117, 118 Context model section 119, 120, 121 FSM coder 122, 123, 124 Code memory 125 Tile tag processing section 200 Personal computer 201 CPU 202 Main memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C057 AA06 CA01 CE10 EA01 EA02 EA07 EL01 EM07 EM11 GG01 GL02 5C059 KK13 KK50 MA24 MA32 PP15 PP16 UA02 UA05 UA33 5C078 AA09 BA21 BA23 BA32 BA53 CA31 DA00 BA01 A BD04 9A001 BB01 CC01 EE02 EE04 GZ01 GZ03

Claims (3)

[Claims] 1. A data compression / decompression apparatus for compressing / decompressing image data or the like by a combination of two-dimensional lossless wavelet transform, context model processing and entropy coding / decoding processing, for context model processing and entropy coding / decoding processing. Encoding of three types of high-frequency components by two-dimensional reversible wavelet transform of image data or the like, or decoding of encoded data of three types of high-frequency components, using a plurality of sets of means. Data compression and decompression device. 2. A data compression / decompression apparatus for compressing / decompressing image data or the like by a combination of a two-dimensional reversible wavelet transform, a context model process and an entropy coding / decoding process. Compression and decompression of a plurality of tile data in parallel, and in each processor core, using a plurality of sets of means for context model processing and entropy coding / decoding processing, three types of two-dimensional reversible wavelet transform of tile data A data compression / decompression apparatus for performing encoding of high frequency components or decoding of encoded data of three types of high frequency components in parallel. 3. Each processor core stores a two-dimensional reversible wavelet transform unit for tile data such as image data, and a low frequency component and three types of high frequency components by two-dimensional reversible wavelet transform of tile data. Memory for storing encoded data of three types of high frequency components, encoding of three types of high frequency components, or encoding of three types of high frequency components. 3. The data compression system according to claim 2, wherein three sets of independently operating context model processing means and entropy coding / decoding means for decoding are mounted on the same IC chip. Stretching device.