JP2000244907A - Low cost video decoder for digital video data decoding and format conversion - Google Patents

Abstract

[PROBLEMS] To provide a low-cost solution for implementing a decoder for decoding and format conversion of digital video data. A decoder has the ability to generate images at reduced resolution for various applications. The decoder comprises means for bit stream processing, motion compensation processing, addition and buffering of decoded data. The present invention uses U × V
M × N preselected from a block of DCT coefficients, followed by upsampling, interpolation, and downsampling of data in the motion compensation process
To perform an IDCT operation on a block of data, a method using a small M × N IDCT kernel is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a low-cost video decoder for decoding and format conversion of digital video data. The invention has application in the field of video decoders and format conversion of digital video data for applications requiring lower resolution and cost. Such uses include displaying images in images, low resolution displays for small monitors, and displaying high definition television on standard television SDTV and HDTV signals.

[0002]

BACKGROUND OF THE INVENTION Many compression and decompression techniques are available for efficient storage and supply of video data. International Organization for Standardization (ISO) is involved in the compression and decompression of video data.
Documented standards. For the MPEG standard, see MPEG
-1 (International Organization for Standardization, "CD11172-Coding of moving pictures and related audio for digital storage media up to about 1.5 Mbps", IS of 1994
O-IEC / JTC1 / SC2 / WG11) and MPEG-2 ("IS13818" by the International Organization for Standardization)
-199 General encoding of moving pictures and associated audio
There are several versions such as 4 years ISO-IEC / JTC1 / SC2 / WG11). In the present application, the decoder is capable of decoding an MPEG standard bit stream.

[0003] The MPEG standard specifies a number of properties and levels to provide different requirements for different applications. The key characteristic video format at the key level has a maximum image size of 720 × 576 pixels for standard television (SDTV). For applications requiring very high resolution display, such as the proposed US High Definition Television HDTV standard, which is part of the high level key characteristics, 1920
A maximum image size of × 1080 pixels is allowed.

[0004] Due to the high data rates of high resolution applications, the decoding circuitry of video decoders has become increasingly complex,
Also, the memory required for storing the decoded data increases. Therefore, HDTV video decoders are too expensive for the average consumer. In order to reach a wider television audience, it is desirable to reduce the cost of HDTV video decoders and to allow HDTV broadcasts to be received by conventional SDTV. Reduce costs,
One way to achieve a wide TV viewing range is to format the video signal so that it can be received by different types of receivers.
Format conversion of a video signal involves decimation (d) of the decoded image before outputting it for display.
Usually performed after the decoding process by ecimate or interpolate.

However, since this format conversion method does not reduce the amount of data required for processing and storage during decoding,
This method does not reduce the cost and complexity of the decoding circuit.

FIG. 1 shows a conventional example of a low-resolution decoder for format conversion (Report on circuits and systems for IEEE video technology, August 1994, Vol. 4, 39).
Page 2-406, authors Robert Mokry and D
(see "Minimum Error Drift of Frequency Scalability for Motion-Compensated DCT Coding", Imitris Anastassiou). The low resolution decoder uses four full resolution IDCT circuits for upsampling. After full-resolution motion compensation, to convert the predicted data block to the frequency domain before adding the predicted data block to the DCT error block, a full-resolution D
A CT circuit is used.

[0007] The data rate of digital video data for high resolution applications, such as high definition television HDTV signals, is much faster than standard television SDTV signals. Therefore, HD
The decoding circuit of a TV video decoder is more complicated than an SDTV video decoder. For example, the HDTV video decoder I
DCT circuits will require faster clocks or multiple parallel execution units to handle high data rates.

[0008] The high complexity of a video decoder also affects its cost. In fact, a large proportion of the costs associated with HDTV video decoders depend on the memory used for image storage during decoding. Since large amounts of data are required to display HDTV images, memory requirements, and thus costs, are significantly increased. The complexity and cost of video decoders is unacceptable for low cost applications requiring only low resolution displays. In some applications, low-resolution image displays, such as video devices that have only image-in-image functionality and a small display screen, can be tolerated.

[0009] The introduction of HDTV receivers is only gradually being accepted by the large consumer population that owns conventional television receivers. If the cost of HDTV receivers is beyond the reach of the average consumer, HDTV programs will not be enjoyed by large numbers of people. Therefore, one solution is to provide a low-cost video decoder with HDTV signal decoding and format conversion capabilities for display on existing conventional television receivers.

The format conversion method using the full resolution IDCT and DCT circuits of the motion compensation process as described in the prior art minimizes the drift of the low resolution video decoder. However, IDCT and D
CT circuits add extra cost to the video decoder and require additional computational means.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to address the complexity and cost issues of video decoders, the complexity of format conversion for low-resolution applications,
It is to solve the problem of compatibility between TV and SDTV formats.

[0012]

Means for solving the above problems will be described below. The present invention provides a U × V DCT
To perform an IDCT operation on a block of M × N data that is preselected from a block of coefficients and then followed by upsampling, interpolation, and downsampling of the data in the motion compensation process, a small M × N
A method using an N IDCT kernel is used. The decoding circuitry of a video decoder can be simplified by using a smaller IDCT kernel. The amount of data generated by the IDCT operation decreases as the IDCT kernel becomes smaller, and as a result, the amount of data that must be stored in the memory is also reduced. Further, in the format conversion of video data for different uses, the IDCT
The kernel is reduced. A simple two-tap filter can be used for upsampling, and an unfiltered downsampler can be used for the motion compensation process.

The present invention comprises means for performing bit stream processing, buffering, motion compensation processing, addition, and video format processing. Further, the bit stream processing means comprises means for variable length decoding VLD, inverse quantization IQ, and inverse discrete transform (IDCT) for the purpose of decoding the input bit stream.

Further, the motion compensation processing means includes a motion vector processor for processing a motion vector decoded from the input bit stream, and decoded data retrieved from the buffer means using the scaled motion vector. An upsampler for upsampling, a half-pixel interpolation circuit for interpolating upsampling data, a motion compensation unit for generating motion compensation data, and a downsampler for downsampling motion compensation data. Is done.

Further, the video format processing means comprises a horizontal post-processing means and a vertical post-processing means for post-processing decoded data in the buffer means in order to output a video in a correct aspect ratio and display format. You.

The present invention decodes digital video data of an input bit stream and performs video format conversion to generate images of different resolutions for various applications. The bit stream processing means is used for decoding the input bit stream.
The motion compensation processing means is used to predict a current frame image using information from a previous frame stored in the buffer means as decoded data.
The adding means is used to combine data outputs from the bit stream processing means and the motion compensation processing means to reconstruct a current frame image for display. The output of the adding means is stored as decoded data using the buffer means for predicting the next frame image.

[0017] The variable length decoding means decodes run-length encoded video and motion vector data of the digital video data. Next, the run length decoded video is transmitted to the inverse quantization means of the block of U × V data, and the run length decoded motion vector is transmitted to the motion vector processor. The run-length decoded video data is inversely quantized and output to the inverse discrete cosine transform means, IDCT, as a block including a U × V discrete cosine transform and DCT coefficients. The inverse discrete transform means includes an M × N IDCT kernel for performing an IDCT operation on M × N coefficients selected from the upper left M × N area of each DCT block including U × V coefficients. Next, the result comprising the block of M × N IDCT output data is output to the adding means.

The motion vector processor processes the run length decoded motion vector data and outputs a half pixel motion vector and a scaled motion vector. Since the use of the run-length decoded motion vector data was originally intended for retrieving a block of U × V data from the buffer means, U × V
Scaling is needed to search for fewer blocks than data. Since the block size is reduced to M × N after the IDCT operation, the run-length decoded motion vector data is scaled by a ratio of U: M for the horizontal component and V: N for the vertical component.

The scaled motion vector is
Used by the upsampler to retrieve a block of M × N decoded data from the buffer means for upsampling. In order for the motion compensation unit to perform half-pixel precision motion compensation, the blocks of M × N decoded data are horizontally M: U and vertically N: V into blocks consisting of U × V data. , Upsampled by the upsampler and interpolated by the interpolator into blocks of half-pixel resolution data. Next, the motion compensation unit searches the half-pixel resolution data using the half-pixel motion vector, and searches for a block required for the U × V half-pixel motion compensation data.

The block containing U × V motion compensation data is transmitted to a downsampler downsampler to generate a block of M × N downsampled data. The downsampling operation is necessary to invert the upsampling operation so that the number of data inputs to the adding means includes a block of M × N data. The adding means performs addition of a block including M × N IDCT output data and down-sampled data to generate a block of M × N decoded data to be stored in the buffer means. Next, the video format processing means retrieves the decoded data from the buffer means in a raster format for post-processing and outputting video in the correct aspect ratio and display format.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an embodiment according to the present invention. The present invention provides a bit stream processing means 207,
It comprises a buffer means 222, a motion compensation processing means 221, an adding means 208, and a video format processing means 229.

The bit stream processing means 207 further includes a variable length decoding means (VLD) 201, an inverse quantization means (IQ) 203, and an inverse discrete transform means (IDCT) 205.
And Further, the motion compensation processing means 221 outputs the motion vector 2 decoded from the input bit stream 200.
10 and to generate a scaled motion vector 212 and a half-pixel motion vector 209, the motion vector processor 211 and the decoding retrieved from the buffer means 222 using the scaled motion vector 212. Upsampler 213 for upsampling the digitized data 223, a half pixel interpolation circuit 215 for interpolating the upsampled data 214, and a motion compensation unit for generating half pixel motion compensation data 218 using the half pixel motion vector 209 217 and a downsampler 219 for downsampling the motion compensation data 218. Furthermore, the video format processing means 229
It comprises horizontal post-processing means 225 and vertical post-processing means 227 for formatting the decoded data 224,
Generate video data 228 having the correct aspect ratio and display format.

The operation of the embodiment shown in FIG. 2 will be described below.

The variable length decoding means 201 decodes the run length encoded video and the motion vector data of the input bit stream 200. Next, the run-length decoded video 202 is used as the inverse quantization means 2 for the block of U × V data.
03 and the run-length decoded motion vector 210 is transmitted to a motion vector processor 211.
The run-length decoded video data 202 is inversely quantized, U × V discrete cosine transformed, DCT coefficients 204
Is output to the inverse discrete transform means 205 as a block including. The inverse discrete cosine transform means 205 uses a U × V DCT
An M × N IDCT kernel is used to perform an IDCT operation on M × N data selected from the upper left M × N area of each block including the coefficient 204. next,
The result including the block of the M × N IDCT output data 206 is output to the adding means 208.

A motion vector processor 211 processes the run-length decoded motion vector data 210 and outputs a half-pixel motion vector 209 and a scaled motion vector 212. Since the use of the run-length decoded motion vector data 210 was originally intended for searching for blocks of U × V data from the buffer means 222, in order to search for fewer blocks than U × V data, Scaling is required. Since the block size is reduced to M × N after the IDCT operation, the run-length decoded motion vector data 210 is scaled with a U: M ratio for the horizontal component and a V: N ratio for the vertical component.

The scaled motion vector 212
Is used by the upsampler 213 to search for blocks of M × N decoded data 223 from the upsampling buffer means 222. In order for the motion compensation unit 217 to perform half-pixel precision motion compensation, a block of M × N decoded data 223 is
M: U horizontally in a block composed of data 214
And vertically to N: V by an upsampler 213 and interpolated by an interpolator 215 into a block of half-pixel resolution data 216. Next, the motion compensation unit 217 uses the half-pixel motion vector 209 to generate half-pixel resolution data 216.
And U × V half-pixel motion compensation data 218
To find the block you need.

Block 21 containing U × V motion compensation data
8 is transmitted to a downsampler downsampler 219 to generate a block of M × N downsampled data 220. The downsampling operation is necessary to invert the upsampling operation so that the number of data inputs to the adding means 208 includes a block of M × N data. The adding means 208 is used to store the M × N decoded data 2 to be stored in the buffer means 222.
To generate thirty blocks, an addition of the blocks containing the M × N IDCT output data 206 and the down-sampled data 220 is performed.

The video format processing means 229 searches the decoded data 224 from the raster format buffer means 222 for processing and display on the monitor.
The video format processing means includes:
The effect of the embodiment of FIG. 2 consisting of horizontal post-processing means 225 and vertical post-processing means 227 for up (and / or down) sampling of 4 and outputting video in the correct aspect ratio and display format is described below. explain.

The M × N IDCT kernel is not as complex as the U × V IDCT kernel of the MPEG decoder, [M <
U and N ≦ V] or [M ≦ U and N <V]. Thus, the M × N IDCT engine is smaller, less expensive, and faster. Also, since the buffer means only needs to store blocks of M × N data instead of blocks of U × V data, the blocks of data that need to be stored in the buffer means are smaller with the M × N IDCT kernel. Therefore, a smaller and less expensive buffer means can be used.

The present invention also allows for different M × N IDCT structures. To increase the display resolution,
Larger MxN structures can be used for IDCT operations. For example, a 2x2 IDCT may be sufficient for intra-image applications, while a 4x8 IDCT provides much higher resolution for full screen SDTV displays.

A specific M × NI for HDTV decoder
To illustrate the DCT structure, another embodiment of the invention is shown in FIG.
Shown in This embodiment uses 3 × 4 for M × N and 8 × 8 for U × V. The operation of the embodiment of FIG. 3 will be described below.

The variable-length decoding means 301 decodes the run-length coded video and the motion vector data of the HDTV bit stream 300. Next, the run-length decoded video 302 is transmitted to the inverse quantization means 303 of the block of 8 × 8 data, and the run-length decoded motion vector 310 is transmitted to the motion vector processor 311. The run-length decoded video data 302 is inversely quantized and output to an inverse discrete transform unit 305 as a block including an 8 × 8 discrete cosine transform and DCT coefficients 304. The inverse discrete transform unit 305 includes an 8 × 8 DCT coefficient 304
Is composed of a 3 × 4 IDCT kernel for performing an IDCT operation on 3 × 4 data selected from the upper left area of each block including. Next, the result including the block of the 3 × 4 IDCT output data 306 is output to the adding means 308.

The motion vector processor 311 processes the run-length decoded motion vector data 310 and outputs a half-pixel motion vector 309 and a scaled motion vector 312. Since the original motion vector is calculated by the video encoder according to the block of 8 × 8 video data, scaling on the video decoder side is required to retrieve the block of 3 × 4 data 323 from the buffer means 322. . Block size is IDCT
Since it is reduced to 3 × 4 after the operation, the run-length decoded motion vector data 310 is 8: 3 for the x component.
And for the y component at a 2: 1 ratio.

The scaled motion vector 312
Is used by the upsampler 313 to retrieve a block of the 3 × 4 decoded data 323 from the buffer means 322 for upsampling. In order for the motion compensation unit 317 to perform half-pixel precision motion compensation, the block of 3 × 4 decoded data 323 is 8 ×
8 data 314 are upsampled horizontally by 3: 8 and vertically by 1: 2 by an upsampler 313 and an 8 × 8 by an interpolator 315.
Interpolated into blocks of half-pixel resolution data 316. Next, the motion compensation unit 317 uses the half-pixel motion vector 309 to generate half-pixel resolution data 316.
And 8 × 8 half-pixel motion compensation data 318
To find the block you need.

The block containing the 8 × 8 motion compensation data 318 is transmitted to a downsampler downsampler 319 to generate a block of 3 × 4 downsampling data 320. The downsampling operation is necessary to invert the upsampling operation so that the number of data inputs to the adding means 308 includes a block of 3 × 4 data. The adding means 308 is used to store the 3 × 4 decoded data 328 to be stored in the buffer means 322.
Is performed, the block including the 3 × 4 IDCT output data 306 and the down-sampling data 320 is added.

The vertical post-processing means 325 is a raster format buffer means 3 for processing and display on a monitor.
22 is searched for the decrypted data 324. The vertical post-processing means performs down-sampling of the decoded data 324 with the correct aspect ratio and display format.

For an application such as HDTV signal display on SDTV, this embodiment obtains an image size of 720 × 540 by 3 × 4 IDCT operation by format conversion of an HDTV signal having an image size of 1920 × 1080. It is shown that it is possible. As a result, the block size required for storing in the buffer means 322 is reduced from 8 × 8 to 3 × 4. The image having the reduced size of 720 × 540 is transmitted to the vertical post-processing means 325 for post-processing to an image size of 720 × 480 for display on NTSC or SDTV. Vertical post-processing means 325 is used to perform 540: 480 downsampling to convert a 540 to 480 vertical image size. However, since the 3x4 IDCT structure already generates 720 horizontal image sizes, the present invention
No horizontal post-processing means is required to convert HDTV to SDTV.

The effect of the embodiment shown in FIG. 3 will be described below.
HDTV format conversion for display on SDTV is possible. The 3 × 4 IDCT kernel is MPE
It is not as complex as the 8 × 8 IDCT kernel of the G video decoder. Thus, a 3x4 IDCT engine is smaller, less expensive, and faster. This also reduces the data blocks that need to be stored in the buffer means. The buffer means need only store blocks of 3x4 data instead of blocks of 8x8 data as required by the MPEG video decoder. Therefore, a smaller and less expensive buffer means can be used. An unfiltered downsampling process does not add cost to the video decoder. Also, if a two-tap filter is used, there is no additional cost for the upsampling process. For applications such as format conversion of HDTV signals for display on an SDTV, the 3 × 4 IDCT operation omits the horizontal post-processing means.

One advantage of the present invention is that a low cost video decoder can be realized by using a smaller IDCT kernel. The smaller IDCT kernel uses less memory and reduces the complexity of the decoding circuitry of the video decoder. The present invention also provides
Simplify the upsampling and downsampling processes of the motion compensation process. Therefore, the power supply,
The cost and size of the video decoder integrated circuit is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a low drift decoder with minimum drift according to the prior art.

FIG. 2 is a block diagram of a decoder according to a preferred embodiment of the present invention.

FIG. 3 is a block diagram of a converter for converting HDTV into SDTV format conversion according to the present invention.

[Explanation of symbols]

 201 variable length decoding means 203 inverse quantization means 205 M × N IDCT means 208 addition means 211 motion vector processor 213 upsampler 215 half pixel interpolation circuit 217 motion compensation unit 219 downsampler 222 Buffer means 225 horizontal post-processing means 227 vertical post-processing means 300 HDTV bit stream 301 variable-length decoding means 303 inverse quantization means 305 3 × 4 IDCT means 308 addition means 311 motion vector processor 313 up Sampler 315: Half-pixel interpolation circuit 317: Motion compensation unit 319: Downsampler 322: Buffer means 325: Vertical post-processing means

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Bi Mi Michael Singapore 534415 Singapore, Thai Sen Avenue, Blocks 1022, 04-3530, Thai Sen Industrial Estate, Panasonic Singapore Research Institute Ltd. F-term (reference) 5C059 KK00 LB03 LB18 MA23 ME01 ME05 NN15 NN21 NN28 SS03 SS05 TD06 UA05

Claims (18)

[Claims] 1. A decoder for decoding and converting format of digital video data for generating an image with reduced resolution, the digital video data of an input bit stream being decoded, and a block of M × N data being added to an adding means. Bit stream processing means for generating, and processing and predicting the current frame image, and generating a block of M × N data indicating the predicted current frame image to the adder means for generating a block of M × N data. M × shown
Motion compensation processing means coupled to buffer means for retrieving a block of N decoded data, wherein the adding means reconstructs a current frame image and stores the block of M × N decoded data in the buffer means. To generate a block of M × N data from the bit stream processing means and the motion compensation processing means, and the buffer means stores the block of M × N decoded data from the adding means. There is a decoder. 2. A variable length decoding means for decoding run-length encoded data of the digital video data to generate run-length decoded video and motion vector data.
Dequantizing the run-length decoded video data to obtain U
× V discrete cosine transform, inverse quantization means coupled to said VLD for generating a block of DCT coefficients, IQ
And M × N preselected DC using M × N IDCT kernel
Performing an inverse discrete cosine transform operation on the block containing the T coefficient to generate a block of M × N IDCT output data in the adding means;
The decoder of claim 1, comprising: DCT. 3. The method of claim 2, wherein the preselected DCT coefficient is U × V D
3. The decoder according to claim 2, wherein the decoder is selected from an upper left M x N region of each block including a CT coefficient. 4. A motion vector processor coupled to the VLD for processing the run length decoded motion vector data to generate half pixel motion vectors and scaled motion vectors. Using said scaled motion vector to search for a block of M × N decoded data and up-sampling said block of M × N decoded data into a block of U × V data, An upsampler coupled to a processor and buffer means; and a half-pixel interpolator coupled to the upsampler for interpolating an upsampled block of UxV data to generate a block of half-pixel resolution data. Ux by using the half-pixel motion vector
A motion compensation unit coupled to the half pixel interpolator to generate a block of V motion compensation data and to search from the block containing half pixel resolution data; The decoder of claim 1, comprising: a downsampler coupled to the motion compensation unit and summing means for downsampling to generate a block of MxN data. 5. The method of claim 4, wherein the scaled motion vector is scaled down from the half-pixel motion vector by an M: U ratio for a horizontal component and by an N: V ratio for a vertical component. Decoder. 6. The decoder of claim 4, wherein the upsampler performs M: U horizontal upsampling and N: V vertical upsampling. 7. The decoder of claim 4, wherein the downsampler performs U: M horizontal downsampling and V: N vertical downsampling without filtering. 8. The method according to claim 1, wherein M and N have a range of [0 <M ≦ U, 0 <N <V] or [0 <M <U, 0 <N ≦ V]. The decoder as described. 9. The method according to claim 1, wherein the M, N, U, and V are 3, 4, respectively, for HDTV for SDTV format conversion.
Decoder according to any of the preceding claims, wherein the decoder is 8,8. 10. A method of decoding and format conversion of digital video data for generating an image at reduced resolution, comprising: receiving digital video data of an input bit stream; decoding the digital video data; M for
Generating a block of M × N data; and predicting the current frame image and generating a block of M × N data for addition by using a previously stored block of M × N decoded data. Processing the motion compensation of the frame image data; and adding the block of M × N data after decoding and processing the motion compensation to obtain a block of M × N decoded data indicating the current frame image for display and buffering. And buffering the block of M × N decoded data from the adding means. 11. The step of decoding digital video data further comprises: decoding a variable length of run-length encoded data of the digital video data to generate run-length decoded video and motion vector data. The run-length decoded video data is inversely quantized,
XV discrete cosine transform, generating a block of DCT coefficients; and MxN inverse discrete cosine transform of the block containing the MxN preselected DCT coefficients, generating a block of MxN IDCT output data in the adding means. 11. The method of claim 10, comprising the steps of: 12. The pre-selected DCT coefficient is U × V
12. The method of claim 11, wherein the method is selected from an upper left MxN region of each block containing DCT coefficients. 13. The motion compensation processing further comprising: processing a motion vector of the run-length decoded motion vector data to generate a half pixel motion vector and a scaled motion vector. Retrieving a block of M × N decoded data from a buffer means using a motion vector, and up-sampling said block of M × N decoded data into a block of U × V data; Interpolating the sampled block to generate a block of half-pixel resolution data; and
Generating a block of V motion compensation data and searching from said block containing half-pixel resolution data; down-sampling said block containing U × V motion compensation data to generate a block of M × N data; The method of claim 10, comprising: 14. The scaled motion vector of claim 13, wherein the scaled motion vector is scaled down from the half-pixel motion vector at a ratio of M: U for the x component and at a ratio of N: V for the y component. Method. 15. The method according to claim 15, wherein the upsampling operation is M: U.
14. The method of claim 13, wherein the horizontal upsampling and the N: V vertical upsampling are performed. 16. The downsampling operation comprises: U: M horizontal downsampling without filtering;
14. The method of claim 13, performing V: N vertical downsampling. 17. M and N are [0 <M ≦ U, 0 <N <V]
17. The method according to any of claims 10 to 16, wherein the method has the range [0 <M <U, 0 <N ≦ V]. 18. The M, N, U, and V may each be 3, 3 for HDTV for SDTV format conversion.
The method according to any of claims 10 to 17, wherein the method is 4, 8, 8.