JP2000244261A - Signal input circuit and variable gain amplifier using the same - Google Patents

Abstract

(57) [Problem] To provide a signal input circuit in which an input range in which an output signal current linearly changes with respect to an input signal voltage is expanded. SOLUTION: An input signal voltage VCN from an input terminal 10 is provided.
T is applied to one input terminal and the other input terminal
Differential amplifier 1 to which reference voltage Vref1 is applied
1, a level shift circuit 13 for shifting the DC level of the input signal voltage VCNT by a predetermined amount, and a level shift circuit 13
And a second differential amplifier 12 to which an input signal is applied to one input terminal and a second reference voltage Vref2 is applied to the other input terminal. The current is added by the adder 14 to obtain the output signal current I.
Output to the output terminal 20 as CNT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input circuit capable of widening an input signal voltage input range and a variable gain amplifier using the same as a gain control circuit.

[0002]

2. Description of the Related Art In recent years, wireless communication devices represented by mobile phones have been actively developed. These wireless communication devices are required to be low in power consumption, small in size and light in weight because they are used, for example, by humans or mounted on automobiles. For this reason, the components constituting such a device are monolithic ICs that are more suitable for miniaturization and weight reduction than the hybrid configuration in which a large number of conventional component parts are connected.
(Integrated circuit) is strongly desired. In addition to the downsizing of components, it is naturally required to reduce the price of equipment, but the use of a monolithic IC is an indispensable technology for reducing the price.

In such a wireless communication device, a variable gain amplifier is used in a wireless receiving circuit system in order to overcome the near-far problem. The gain control range of the variable gain amplifier is CD
About 80 dB for MA (Code Division Multiple Access) system
Degree is required. FIG. 10 is a diagram showing the relationship between the gain control voltage VCNT and the gain of the variable gain amplifier. Assuming that the input range of the gain control voltage VCNT is W (V), the gain sensitivity to the gain control voltage VCNT is 80 / W (dB). /
V).

The input range W of the gain control voltage VCNT
If (V) is reduced, the sensitivity of the gain to the gain control voltage VCNT increases, and the gain changes greatly with a slight voltage change, making it difficult to perform highly accurate gain control.
In the case of a portable wireless communication device, it is necessary to reduce the voltage of the power supply, so that it is necessary to make this input range W (V) as large as possible within the range of the power supply voltage. That is, an amplifier circuit (hereinafter referred to as a gain circuit) that can change the gain control voltage VCNT in a voltage range from the low voltage side voltage source Vee (hereinafter, referred to as ground GND) to the high voltage side power supply Vcc. Realization of a control circuit) is desired. The gain control circuit is required to be able to output a linear output signal (current) with respect to the gain control voltage in order to avoid a change in gain sensitivity with respect to the gain control voltage.

FIGS. 11A and 11B show a gain control circuit constructed using conventional npn transistors and its input / output characteristics. The gain control circuit shown in FIG. 11A includes transistors Q100 and Q101, an emitter degeneration resistor for expanding a linear range, and current sources I100 and I101. In this case, the output signal (current) Iout proportional to the gain control signal (voltage) VCNT can be extracted as shown in FIG.
This is when CNT is equal to or more than VBE + VCEsat. Here, VBE represents a base-emitter voltage (about 0.7 V) of the transistor Q100, and VCEsat represents a current source I
100 represents the saturation voltage of the transistor constituting 100. Here, the current source I100 comprises only a common emitter transistor. However, when the current source I100 also includes an emitter degeneration resistor, a voltage applied between the emitter degeneration resistors is added to VCEsat. Will be.

Therefore, in the configuration of FIG. 11A, the effective input range of the gain control voltage VCNT is VBE + VCEsat.
(About 1 V) to Vcc, so GND to Vc
VBE + VCEsat compared to the power supply voltage range up to c
The range is reduced by the minute. For example, Vcc = 2.5
(V), the gain control voltage VC
The effective input range of NT pressure is 1.5V, and Vcc is 60V.
%.

On the other hand, FIGS. 12A and 12B show a conventional pnp
A gain control circuit formed using transistors and its input / output characteristics. In this case, the effective input range of the gain control voltage VCNT is similarly from GND to Vcc-VBE-.
VCEsat is smaller than the power supply voltage range from GND to Vcc.

[0008]

As described above, as described above,
A conventional gain control circuit for controlling the gain of a variable gain amplifier has a high gain sensitivity to the gain control voltage because the effective input range of the gain control voltage, which is an input, is narrow, and the gain changes greatly with a small voltage change. Therefore, there is a problem that it is difficult to perform gain control with high accuracy.

An object of the present invention is to provide a signal input circuit which can expand an input range in which an output signal current changes linearly with respect to an input signal voltage and is particularly suitable for a gain control circuit for a variable gain amplifier. I do.

[0010]

In order to solve the above-mentioned problems, a signal input circuit according to the present invention provides an input signal voltage to one input terminal and a first reference voltage to the other input terminal. A first differential amplifier, a level shift circuit for shifting the DC level of the input signal voltage by a predetermined amount, an output signal voltage of the level shift circuit is applied to one input terminal, and the second input terminal is And a second differential amplifier to which a reference voltage is applied, and outputs a current obtained by adding an output current of the first differential amplifier and an output current of the second differential amplifier as an output signal current. It is characterized by.

More specifically, the level shift circuit includes, for example, a transistor having a base terminal as an input terminal, a collector terminal connected to ground or a power supply, and an emitter terminal as an output terminal, and a transistor connected directly or with a resistor to the emitter terminal of the transistor. And a current source connected via the

Further, the first differential amplifier comprises a first transistor having a base terminal as one input terminal and a second transistor having a base terminal as the other input terminal and a collector terminal as an output terminal. The second differential amplifier includes a third transistor having a base terminal as one input terminal, a third transistor having a base terminal as the other input terminal, a collector terminal as an output terminal, and a second transistor having a second terminal. A second differential transistor pair including a collector terminal and a fourth transistor commonly connected is provided.
Then, an output signal current is output from the commonly connected collector terminals of the second transistor and the fourth transistor.

In this signal input circuit, the linear operation range of the first differential amplifier to which the input signal voltage is directly input and the linear operation range of the differential amplifier to which the input signal voltage is input via the level shift circuit are set. Therefore, by adding the output currents of the first and second differential amplifiers to obtain an output signal current, the range of the input signal voltage in which the output signal current changes linearly with respect to the input signal voltage is obtained. It is enlarged.

Another signal input circuit according to the present invention includes a first differential amplifier having an input signal voltage applied to one input terminal, a level shift circuit for shifting a DC level of the input signal voltage by a predetermined amount, A second differential amplifier in which an output signal voltage of the level shift circuit is supplied to one input terminal and a second reference voltage is supplied to the other input terminal;
A control circuit. The state detection / control circuit detects whether the second differential amplifier is in a linear operation state with respect to the output signal voltage of the level shift circuit, and if the second differential amplifier is in the linear operation state, the second differential amplifier The output current of the first differential amplifier obtained when the first reference voltage is applied to the other input terminal of the first differential amplifier when the linear amplifier is not in a linear operation state. Control is performed to output a current obtained by adding the difference current between the current and the predetermined control current and the output current of the second differential amplifier as an output signal current.

The state detection / control circuit comprises, for example, a fifth transistor having a base terminal connected to the emitter terminal of a third transistor of the second differential amplifier, and a current connected to the emitter of the fifth transistor. A source and a current mirror circuit having an input terminal connected to the collector terminal of the fifth transistor, and an output terminal connected to the collector terminal of the second transistor and the collector terminal of the fourth transistor.

In this signal input circuit, the output currents of the first and second differential amplifiers are extracted as output signal currents only when each of them is in a linear operation state, so that the output signal current becomes linear with respect to the input signal voltage. The range of the changing input signal voltage is further expanded.

In the signal input circuit of the present invention, when the input signal voltage is within a predetermined range, the current bypassing the current between the collector terminal and the emitter terminal of each of the first transistor, the second transistor and the fifth transistor. A bypass circuit may be further provided.

In this current bypass circuit, specifically, a reference voltage source, each base terminal is commonly connected to the reference voltage source, and each collector terminal is connected to a first transistor, a second transistor and a fifth transistor. Sixth, seventh, and eighth transistors connected to the respective collector terminals of the first, second, third, and eighth transistors, and the emitter terminals of the sixth, seventh, and eighth transistors, and the first, second, and third transistors. The first, second and third resistors are connected between the respective emitter terminals of the five transistors.

Further, according to the present invention, a gain control circuit is provided, in which a gain control voltage corresponding to the gain control voltage is provided as an output signal current by providing a gain control voltage as an input signal voltage by the signal input circuit described above, A variable gain amplifier is provided in which the gain is controlled by supplying the gain control current from the gain control circuit to the gain control amplifier.

[0020]

FIG. 1 shows a variable gain amplifier as an application example of a signal input circuit according to the present invention. The input signal to the input terminal IN is amplified by the gain control amplifier 1 and output to the output terminal OUT. The gain of the gain control amplifier 1 is controlled by a gain control circuit 2. The gain control circuit 2 receives the gain control voltage VCNT and outputs a corresponding gain control current ICNT to the gain control amplifier 1. The signal input circuit according to the present invention is applied to the gain control circuit 2. .

Hereinafter, embodiments of the signal input circuit according to the present invention will be described. In the following, a case where the signal input circuit is applied to the gain control circuit 2 will be described as an example, and the input signal voltage of the signal input circuit will be described as a gain control voltage VCNT and the output signal current will be described as a gain control current ICNT.

(First Embodiment) FIG. 2 shows a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a schematic configuration of a signal input circuit (gain control circuit) according to the embodiment. The gain control voltage VCNT input to the control signal input terminal 10 is supplied to a first differential amplifier (DIF
F1) While being directly input to one input terminal of 11,
After the DC level is shifted by a predetermined amount by the level shift circuit 13, the DC level is input to one input terminal of the second differential amplifier (DIFF 2) 12. A first reference voltage Vref1 is input to the other input terminal of the first differential amplifier 11,
The other input terminal of the second differential amplifier 12 receives the second reference voltage Vref2.

The outputs of the first and second differential amplifiers 11 and 12 are summed by an adder 14, and this current signal is output to a control signal output terminal 20 as a gain control current ICNT corresponding to the gain control voltage VCNT. You. In the following description, it is assumed that the level shift circuit 13 uses an emitter follower circuit, and the output is taken from the emitter terminal. Although not shown in FIG. 1, Vcc is used as the high-potential power supply, and ground GND is used as the low-potential power supply (Vee).

Next, the operation of the signal input circuit will be described. First, the first differential amplifier 11 has a gain control voltage VCN
Since T is directly input, as shown in FIG. 11B, the gain control voltage VCNT is changed from VBE + VCEsat to Vc
It operates to respond to the change up to c.

On the other hand, the second differential amplifier 12 converts the input gain control voltage VCNT to VBE by the level shift circuit 13.
Since the voltage level-shifted to the high potential side by the amount corresponding to the input voltage is input, the gain control voltage VCNT is VCEsat (= 0.3
It can operate in response to a change from V) to Vcc-VBE-VCEsat. Here, the lower limit VCEs
at is the lower limit of operation (VCEsat) of the current source provided in the second differential amplifier 12, and Vcc−
VBE-VCEsat is determined by the operation upper limit of the emitter follower circuit.

Therefore, the first and second differential amplifiers 11, 1
2 is added by an adder 13 to obtain a gain control current IC.
By outputting as NT, the gain control voltage VCNT
Can be expanded from VCEsat to Vcc.

Next, a more specific embodiment of the present embodiment will be described. FIG. 3 shows a specific circuit example of the signal input circuit of FIG. The first differential amplifier 11 includes transistors Q2, Q3,
It comprises current sources I1 and I2 connected to the emitters of the emitter degeneration resistors R1 and Q2 and Q3, respectively. The base terminal of the transistor Q3 has a first reference voltage Vre
f1 is input, and the collector terminal of the transistor Q2 is connected to the power supply Vcc.

On the other hand, the second differential amplifier 12 includes a current source I connected to the transistors Q4 and Q5, the emitter degeneration resistor R2 and the emitters of the transistors Q4 and Q5, respectively.
The second reference signal Vref2 is input to the base terminal of the transistor Q5, and the collector terminal of the transistor Q4 is connected to the power supply Vcc.

The level shift circuit 13 includes a transistor Q
1 and a current source I10, and has a base terminal of the transistor Q1 as an input terminal to which a gain control voltage VCNT is input. The collector terminal of transistor Q1 is grounded or connected to power supply Vee, and the emitter terminal is connected to power supply Vcc via current source I10.

A voltage obtained by level-shifting the gain control voltage VCNT is obtained from the emitter terminal of the transistor Q1, which is the output terminal of the level shift circuit 13, and is input to the base terminal of the transistor Q4. The collector terminal of the transistor Q3 and the collector terminal of the transistor Q5 are commonly connected, and the gain control current ICNT is taken out to the output terminal 20 by adding these collector currents. That is, the adder 14 shown in FIG. 2 is realized only by connecting the patterns by commonly connecting the collectors of the transistors Q4 and Q5, and does not require a special hardware circuit.

Next, the operation of the signal input circuit shown in FIG. 3 will be described with reference to FIG. First, as shown in FIG. 11B, the first differential amplifier 11 has an input gain control voltage VC
When NT is in the range of VBE + VCEsat or more, a linear current is output to VCNT. Second differential amplifier 12
Sets the gain control voltage VCNT to V
Since the voltage level-shifted by BE is input to the base terminal of the transistor Q4, VCNT is VCEs necessary for the operation of the current source I3 in the second differential amplifier 12.
If at becomes higher than at, a linear current can be output to VCNT. VCNT is Vcc-VBE-VC
If Esat or more, the output (emitter terminal) of the level shift circuit 13 is saturated, so that the input voltage of the second differential amplifier 12 is constant and the output current is also constant. Here, VBE is the base-emitter voltage of Q1,
CEsat is a voltage required for the operation of the current source I10.

Since the gain control current ICNT output from this signal input circuit is the sum of the respective output currents of the first and second differential amplifiers 11 and 12, the gain control of the output with respect to the input gain control voltage VCNT is performed. The change of the current ICNT is as shown in FIG. In the example of FIG.
In the range from (V) to VCEsat, a current of 4Io is output. Io is the current of the current sources I1, I2, I3 and I4. However, the reference voltages Vref1, Vref2
Although there is a possibility that the gain control current ICNT becomes smaller than 4Io due to the bias setting of the reference voltage source that generates the above, this is not considered here, and it is treated as 4Io.

When the gain control voltage VCNT is in the range from VCEsat to VBE + VCEsat, the second differential amplifier 1
2 is operating, and the first differential amplifier 11 is passing a constant current. Gain control voltage VCNT is VBE + VC
In the range from Esat to Vcc-VBE-VCEsat, since both the first and second differential amplifiers 11 and 12 output linear currents, the change of the gain control current ICNT with respect to the gain control voltage VCNT is VCNT. VC
Double the change in the range from Esat to VBE + VCEsat.

When the gain control voltage VCNT is Vcc-VBE-
In the range from VCEsat to Vcc, since only the first differential amplifier 11 is operating, the gain control voltage VC
The change of the gain control current ICNT with respect to NT is VCNT
In the range from VCEsat to VBE + VCEsat. Therefore, when the gain control voltage VCNT is swept in the range from GND to Vcc, the gain control current ICNT does not change linearly with respect to VCNT, but there is a response to VCNT in the range from VCEsat to Vcc. It is possible to correct ICNT so that it changes linearly using.

FIG. 4 shows that VBE + VCEsat = V
When cc-VBE-VCEsat is satisfied, the first and second differential amplifiers 11 and 12 do not operate at the same time, so that the gain control voltage VCNT changes from VCEsat to VCEsat.
It can be seen that up to cc, the gain control current ICNT changes linearly with respect to VCNT. However, in this case, Vc
The condition of c = 2 (VBE + VCEsat) is added and about 2
The power supply voltage is limited to about V.

As described above, in the signal input circuit shown in FIG. 3, the input range of the gain control voltage VCNT is changed to the conventional Vcc-VBE-
It can be increased from VCEsat to Vcc-VCEsat. In this example, the level shift amount of the level shift circuit 13 is only VBE of the transistor Q1, but if the level shift amount is VBE + VCEsat, the input range of the gain control voltage VCNT is Vcc-VCEsat.
(V) to Vcc (V). As will be described in detail later, VCE is connected to the emitter of the transistor Q1.
It can be easily realized by connecting a resistor R10 having a value of sat = R10 × Io. Here, Io is the current source I10
Is the current value.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
3 shows a signal input circuit according to the embodiment. The parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and only the differences from the first embodiment will be described. In this embodiment, the signal input circuit of the first embodiment shown in FIG. Circuit (SENSE a
(nd CONTROL CIRCUIT) 21 and a subtractor 22 are added, and an adder 23 is further provided. The state detection / control circuit 21 determines that the second differential amplifier 12 is in a linear operation state,
That is, the circuit detects whether or not the output signal is linear with respect to the input signal, and controls each unit based on the detection to control the output state of the output signal current ICNT.

More specifically, when the differential amplifier 12 is in a linear operation state, the state detection / control circuit 21 outputs the output current of the differential amplifier 12 to the output terminal 20 via the adder 23 to the gain control current ICNT. And the output of the first differential amplifier 11 is controlled to be 0. If the second differential amplifier is not in the linear operation state, the state detection / control circuit 21 outputs the output current of the first differential amplifier 11 already in the linear operation state and the state detection / control circuit 21. A subtractor 22 obtains a difference current from the current Ic of the provided reference current source, and the adder 23 adds the current to the output current of the second differential amplifier 12 so as to take out as a gain control current ICNT. . With such a configuration, the linear operation range of the signal input circuit can be further expanded.

Next, a more specific embodiment of the present embodiment will be described. FIG. 6 shows a first specific circuit example of the signal input circuit of FIG. 3 will be described. In FIG. 6, a state detection / control circuit 21 including a transistor Q6, a current source I1, and a current mirror circuit CM is newly provided. In the signal input circuit shown in FIG. 3, the base terminal of the transistor Q3 of the first differential amplifier 11 is connected to a reference voltage source that generates a first reference voltage Vref1, but in FIG. It is connected to the emitter terminal of the transistor Q4 of the operational amplifier 12.

Next, the state detection / control circuit 21 will be described in detail. The emitter terminal of the transistor Q6 is connected to a current source I5 that outputs the same current as the current source I2 connected to the emitter terminal of the transistor Q3, and the base terminal is a transistor Q4 like the base terminal of the transistor 3.
And the collector terminal is connected to the current input terminal of the current mirror circuit CM.

The current output terminal of the current mirror circuit CM is common to the collector terminal of the transistor Q3, which is the output terminal of the first differential amplifier 11, and the collector terminal of the transistor Q5, which is the output terminal of the second differential amplifier 12. And the commonly connected collector terminals of the transistors Q3 and Q5 become the output terminal 20 of the signal input circuit. Since the current mirror circuit CM outputs the same current as the current at the current input terminal (collector terminal of the transistor Q6) to the current output terminal (collector terminal of the transistor Q3), the difference current between the collector currents of the transistors Q3 and Q6 is detected. ,
Current output terminal and output terminal 20 of current mirror circuit 21
Will flow between.

Next, the operation of the signal input circuit of FIG. 6 will be described with reference to FIG. 7A and 7B are diagrams showing the operation of the signal input circuit of FIG. 6, and FIG. 7A shows the output current I1 of the second differential amplifier 12 and the output current of the first differential amplifier 11 with respect to the gain control voltage VCNT. And a change in a difference current I2 (a difference between the collector current of the transistor Q3 and the output current of the current mirror circuit CM) from the output current of the state detection / control circuit 21.
(B) shows a change in the output gain control current ICNT = I1 + I2 with respect to the gain control voltage VCNT.

In the signal input circuit of FIG. 6, since the second differential amplifier 12 performs the same operation as the signal input circuit of FIG. 3, the gain control voltage VCNT changes from VCEsat to Vc
In the range from c-VBE to VCEsat, a current proportional to the gain control voltage VCNT is output from the collector of the transistor Q5.

On the other hand, in the first differential amplifier 11, since the base terminal of the transistor Q3 is connected to the emitter terminal of the transistor Q4, the gain control voltage VCNT is VCE.
In the range of Vcc-VBE-VCEsat or more, the base voltage of Q3 is VCNT + VBE-VBE =
VCNT, which is the same voltage as the gain control voltage VCNT. Therefore, the base voltages of the transistors Q2, Q3, and Q6 are equal to or higher than VCEsat and Vccsat.
Below -VBE-VCEsat, it is VCNT.

When gain control voltage VCNT is in the range from VCEsat to VBE + VCEsat, transistors Q2 and
Current sources I1, I connected to the emitter terminals of Q3, Q6
2, I5 cannot operate normally, that is, cannot output the set current Io.
Since the bias points of the transistors Q3 and Q6 are substantially the same, the collector currents of the transistors Q3 and Q6 are equal.
As described above, in the current mirror circuit CM, the difference current I2 between the collector currents of the transistors Q3 and Q6 is detected, so that the gain control voltage VCNT is equal to the aforementioned VCEsat.
The difference current I2 is 0 in the range from to VBE + VCEsat.

On the other hand, when the gain control voltage VCNT is VBE + V
In the range from CEsat to Vcc-VBE-VCEsat, the current sources I1, I2 and I5 connected to the emitter terminals of the transistors Q2, Q3 and Q6 operate normally, but the base voltages of the transistors Q2, Q3 and Q6 are all Gain control voltage VCNT is equal to current source I1, I
2 and I5 almost entirely flow through the collector terminals of the transistors Q2, Q3 and Q6. Therefore, the gain control voltage VCNT changes from VBE + VCEsat to Vcc-VB
Even in the range of E-VCEsat, the difference current I2 becomes zero.

Next, when the gain control voltage VCNT is Vcc-V
The operation of the first and second differential amplifiers 11 and 12 when they are in the range from BE-VCEsat to Vcc will be described.
Since the emitter voltage of the transistor Q1 of the level shift circuit 13 is fixed at Vcc-VCEsat, the output current of the second differential amplifier 12 is fixed. On the other hand, the gain control voltage VCNT is input to the base terminal of the transistor Q2 of the first differential amplifier.
Is fixed at Vcc-VCEsat-VBE, the output current of the first differential amplifier 11 is output in proportion to the gain control voltage VCNT.

The current flows to the collector terminal of the transistor Q6,
Further, since the current input to the current mirror circuit CM is constant at Io, the difference current I2 between the current output from the current mirror circuit CM and the collector current of the transistor Q3 is obtained.
Is proportional to the control voltage VCNT, and the second differential amplifier 12
Of the current gain. However, this is the case where the resistance values of the emitter degeneration resistors R1 and R2 in the differential amplifiers 11 and 12 are equal. Since the gain control current ICNT which is the output current of this signal input circuit is I1 + I2, a current proportional to the control voltage VCNT is output even in this range.

As described above, according to the signal processing circuit shown in FIG. 6, the relationship between the gain control voltage VCNT as an input signal and the gain control current ICNT as an output signal is as follows.
It becomes linear between CEsat and Vcc, and the input range of VCNT in which a linear characteristic is obtained is expanded.

FIG. 8 shows a second specific example of the signal input circuit of FIG. 5, which is a further improved configuration of FIG.
6 in that a reference voltage source Vref3, a current bypass circuit 24 including transistors Q7, Q8, Q9 and resistors R3, R4, R5 are newly added.

The current bypass circuit 24 has a gain control voltage V
This circuit bypasses the current between the collector terminal and the emitter terminal of the transistors Q2 and Q3 of the first differential amplifier 11 and the transistor Q6 of the state detection / control circuit 21 when CNT is within a predetermined range. That is, the transistor Q
7 has a base terminal connected to the reference voltage source Vref3, a collector terminal connected to the power supply Vcc (collector terminal of the transistor Q2), and an emitter terminal connected to the emitter terminal of the transistor Q2 via the resistor R3. The base terminal of transistor Q8 is connected to reference voltage source Vref3, the collector terminal is connected to the collector terminal of transistor Q3, and the emitter terminal is connected to the emitter terminal of transistor Q3 via resistor R4. Transistor Q9
Is connected to the reference voltage source Vref3, the collector terminal is connected to the collector terminal of Q6, and the emitter terminal is connected to the emitter terminal of the transistor Q6 via the resistor R5.

Next, the operation of the signal input circuit of FIG. 8 will be described. However, it is assumed that the current source of each part is a general one using a common-emitter transistor.

In the signal input circuit shown in FIG. 6, the gain control voltage VCNT is changed from VCEsat to VBE + VCEsat.
During this period, the current sources I1, I2 and I5 connected to the emitters of the transistors Q2, Q3 and Q6 do not operate normally. In other words, if the VCE of the transistor constituting the current source is set to VCEsat or less, the transistor enters the saturation region, so that the collector current, which is the output current of the current source, becomes small, and the current from the base terminal of the transistor greatly increases. Will flow. As a result, there is a possibility that the bias voltage for driving the current source applied to the base terminal of the transistor constituting the current source is reduced. Here, when the reduced bias voltage is applied to the base terminals of the transistors constituting the current sources I3 and I4 of the second differential amplifier 12, the current Io of the current sources I3 and I4 decreases. For this reason, the input / output relationship of the differential amplifier 12 depends on the current I
The nonlinear component increases compared to the case where o has not decreased,
The linearity between input and output deteriorates.

The signal input circuit of FIG. 8 is an example in which this point is improved, and the gain control voltage VCNT is VBE + VCEsa
t, the current Io of the current source I1 is
7 to the power supply Vcc. And V
CNT changes from VBE + VCEsat to Vcc-VCEsa
During t-VBE, the current Io of the current source I1 changes from Q7 to Q2.
And the voltage of the reference voltage source Vref3 is set so that the current flows. Thus, saturation of the transistor constituting the current source I1 can be avoided. Specifically, the voltage of the reference voltage source Vref3 is set as follows. VCEsat + Io × R3 + VBE <Vref3 <Vc
c-VCEsat-VBE When the voltage of the reference voltage source Vref3 is set as described above,
When the gain control voltage VCNT is equal to or lower than VBE + VCEsat, the current Io of the current source I2 flows to the collector terminal of Q3 via the resistors R4 and Q8, and VCNT becomes VBE + VCEsat.
, The current path changes so that the current Io of the current source I2 flows from Q8 to the emitter terminal of Q3 between Vcc-VCEsat-VBE.

Similarly, when the gain control voltage VCNT is VBE +
Below VCEsat, the current Io of the current source I5 is
5, and flows to the collector terminal of Q6 via Q9, and VCNT
From VBE + VCEsat to Vcc-VCEsat-V
During BE, the current path changes so that the current Io of the current source I5 flows from Q9 to the emitter terminal of Q6.

That is, when the first differential amplifier 11 does not contribute to the linear output, the current bypass circuit 24 controls the transistors Q2 and Q3 and the state detection /
By forming a current bypass between the collector terminal and the emitter terminal of the transistor Q6 of the control circuit 21, the gain control voltage VCNT is changed from VCEsat to VBE +
It is possible to operate stably in the range of VCEsat.

FIG. 9 shows a third specific example of the signal input circuit of FIG. 5, which has a further improved configuration of FIG.
The difference from FIG. 8 is that a resistor R10 connected between the emitter terminal of the transistor Q1 and the current source I10 is added to the level shift circuit 13. As already described in the description of the circuit of FIG. 3, Io × R10 ≧ VCE
By setting sat, the input range of the gain control voltage VCNT can be expanded from GND to Vcc.

In the above embodiment, the differential amplifier 1
1 and 12, an npn transistor is used for the state detection / control circuit 21 and the current bypass circuit 24, and a pnp transistor is used for the level shift circuit 13. On the contrary, the differential amplifiers 11 and 12, the state detection / control circuit 21 and the current Similar effects can be obtained by using a pnp transistor for the bypass circuit 24 and an npn transistor for the level shift circuit 13.

Further, in the above embodiment, the case where the circuit is constituted by using the bipolar transistor has been described. However, the signal input circuit of the present invention can be similarly constructed by using a field effect transistor (FET) such as a CMOS transistor. Can be realized. When an FET is used, the connection may be made by replacing the base terminal, collector terminal, and emitter terminal of the bipolar transistor with the gate terminal, drain terminal, and source terminal of the FET, respectively.

[0060]

As described above, according to the signal input circuit of the present invention, the input range of the input signal voltage can be increased, and the voltage and power consumption of various circuits connected at the subsequent stage can be reduced. Becomes possible.

The signal input circuit of the present invention can provide a gain control circuit for supplying a gain control signal to a gain control amplifier in, for example, a variable gain amplifier, and in particular, can perform a wide range of gain control as used in portable radio equipment of a W-CDMA system. Useful as a gain control circuit for the required variable gain amplifier, avoiding fluctuations in gain sensitivity to gain control voltage,
Stable and highly accurate gain control can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a variable gain amplifier to which the present invention is applied;

FIG. 2 is a block diagram showing a schematic configuration of a signal input circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration example of a signal input circuit according to the first embodiment;

FIG. 4 is a diagram showing input / output characteristics of the signal input circuit of FIG. 3;

FIG. 5 is a block diagram showing a schematic configuration of a signal input circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a first specific configuration example of a signal input circuit according to a second embodiment;

FIG. 7 is a diagram showing input / output characteristics of the signal input circuit of FIG. 6;

FIG. 8 is a circuit diagram showing a second specific configuration example of the signal input circuit according to the second embodiment;

FIG. 9 is a circuit diagram showing a third specific configuration example of the signal input circuit according to the second embodiment;

FIG. 10 is a diagram showing a relationship between a gain control voltage and a gain of a variable gain amplifier.

FIG. 11 is a diagram showing a conventional signal input circuit and its input / output characteristics.

FIG. 12 is a diagram showing another conventional signal input circuit and its input / output characteristics.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 gain control amplifier 2 gain control circuit (signal input circuit) 10 gain control voltage input terminal 11 first differential amplifier 12 second differential amplifier 13 level shift circuit 14 adder 20 gain Control current output terminal 21 State detection / control circuit 22 Subtractor 23 Adder 24 Current bypass circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J066 AA01 AA12 CA32 CA36 CA37 CA88 FA15 HA08 HA10 HA17 HA25 KA00 KA02 KA05 KA07 KA09 KA18 KA26 MA01 MA21 MD04 ND01 ND12 ND25 PD01 SA13 TA02 5J100 AA02 AA03 AA01 BB CA02 CA05 CA18 CA21 DA06 EA02

Claims (8)

[Claims] An input signal voltage is applied to one input terminal and a first reference voltage is applied to the other input terminal.
A level shift circuit that shifts the DC level of the input signal voltage by a predetermined amount; an output signal voltage of the level shift circuit is supplied to one input terminal, and a second reference voltage is supplied to the other input terminal. And outputting a current obtained by adding the output current of the first differential amplifier and the output current of the second differential amplifier as an output signal current. Characteristic signal input circuit. 2. A first differential amplifier having an input signal voltage applied to one input terminal, a level shift circuit for shifting a DC level of the input signal voltage by a predetermined amount, and an output signal voltage of the level shift circuit. Is supplied to one input terminal, and a second reference voltage is supplied to the other input terminal; and a second differential amplifier is provided for the output signal voltage of the level shift circuit. Detecting whether or not the device is in a linear operation state; if the device is in a linear operation condition, the output current of the second differential amplifier is used as an output signal current; A difference current between an output current of the first differential amplifier and a predetermined control current obtained in a state where a first reference voltage is applied to the other input terminal of the amplifier, and an output current of the second differential amplifier. The added current is output as the output signal current. Signal input circuit, characterized by comprising a state detection / control circuit for controlling. 3. The level shift circuit includes a transistor having a base terminal as an input terminal, a collector terminal connected to ground or a power supply, and an emitter terminal as an output terminal, and a transistor connected directly or via a resistor to an emitter terminal of the transistor. 2. A connected current source.
Or the signal input circuit according to 2. 4. The first differential amplifier comprises: a first transistor having a base terminal as one input terminal; and a second transistor having a base terminal as the other input terminal and a collector terminal as an output terminal. The second differential amplifier has a third transistor having a base terminal as one input terminal, a third transistor having a base terminal as the other input terminal, and a collector terminal as an output terminal. Second
A second differential transistor pair consisting of a collector terminal of the second transistor and a fourth transistor connected in common, and the output signal current flows from a commonly connected collector terminal of the second transistor and the fourth transistor. 3. The signal input circuit according to claim 1, wherein 5. The first differential amplifier comprises: a first transistor having a base terminal as one input terminal; and a second transistor having a base terminal as the other input terminal and a collector terminal as an output terminal. The second differential amplifier has a third transistor having a base terminal as one input terminal, a third transistor having a base terminal as the other input terminal, and a collector terminal as an output terminal. Second
A second differential transistor pair including a collector terminal of the third transistor and a fourth transistor connected in common, wherein the state detection / control circuit has a base terminal connected to an emitter terminal of the third transistor. A fifth transistor, a current source connected to the emitter of the fifth transistor, an input terminal connected to the collector terminal of the fifth transistor, and an output terminal connected to the collector terminal of the second transistor. A current mirror circuit connected to a collector terminal of a fourth transistor, wherein the output signal current is output from a commonly connected collector terminal of the second transistor and the fourth transistor. Item 3. The signal input circuit according to Item 2. 6. A current bypass circuit for bypassing a current between a collector terminal and an emitter terminal of each of the first transistor, the second transistor, and the fifth transistor when the input signal voltage is within a predetermined range. The signal input circuit according to claim 5, wherein 7. A current bypass circuit comprising: a reference voltage source;
Sixth, seventh and seventh power supply units each having a base terminal connected in common to the reference voltage source, and a collector terminal connected to a respective collector terminal of the first transistor, the second transistor and the fifth transistor. An eighth transistor, and an emitter terminal of each of the sixth, seventh, and eighth transistors and an emitter terminal of each of the first, second, and fifth transistors. 1st, 2nd
And a third resistor.
2. The signal input circuit according to 1. 8. A signal input circuit according to claim 1, wherein a gain control voltage is applied as an input signal voltage to output a gain control current corresponding to the gain control voltage. A variable gain amplifier, comprising: a gain control circuit serving as a current; and a gain control amplifier whose gain is controlled by being supplied with the gain control current from the gain control circuit.