JP2000243864A - Semiconductor device and its manufacturing method, circuit board, and electronic equipment - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device in which resin does not easily peel off, a method for manufacturing the same, a circuit board, and an electronic device. A semiconductor device includes a semiconductor chip, a substrate on which a wiring pattern is formed, and a resin provided on the wiring pattern.
When the temperature decreases from the temperature exceeding the glass transition temperature to the glass transition temperature, the force generated by the contraction of the volume is smaller than the adhesive force to the wiring pattern 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.

[0002]

BACKGROUND OF THE INVENTION In the process of assembling a semiconductor device, a resin is sometimes provided on a wiring pattern formed on a substrate. For example, in face-down mounting, a resin is filled between a semiconductor chip and a substrate to eliminate a gap and improve reliability. The resin is provided by being heated once, and is cooled and hardened. This resin may peel off from the wiring pattern on the substrate due to shrinkage upon cooling. In particular,
When the wiring pattern was plated, peeling was likely to occur because the adhesion between the plating and the resin was extremely weak.

An object of the present invention is to solve this problem, and an object of the present invention is to provide a semiconductor device in which resin does not easily peel off, a method of manufacturing the same, a circuit board, and electronic equipment.

[0004]

(1) A semiconductor device according to the present invention includes a semiconductor chip, a substrate having a wiring pattern formed thereon, and a resin provided on the wiring pattern. When the temperature decreases from the temperature exceeding the glass transition temperature to the glass transition temperature, the force generated by the contraction of the volume is smaller than the adhesive force to the wiring pattern.

[0005] In general, a semiconductor device may go through a high-temperature process during its manufacture or when it is mounted on a circuit board, and the temperature at that time exceeds the glass transition temperature of the resin. When the temperature exceeds the glass transition temperature, the adhesive strength of the resin to the wiring pattern decreases. Moreover, when the temperature decreases from the temperature exceeding the glass transition temperature to the glass transition temperature, the resin shrinks. According to the present invention, since the force generated by the shrinkage of the resin is smaller than the adhesive force of the resin to the wiring pattern, peeling between the resin and the wiring pattern is less likely to occur.

(2) In this semiconductor device, the resin may contain a filler for lowering the coefficient of thermal expansion at a temperature equal to or higher than the glass transition temperature, so that shrinkage in volume may be suppressed.

According to this, when the resin is heated to a temperature equal to or higher than the glass transition temperature, that is, when the adhesive strength of the resin to the wiring pattern is small, the coefficient of thermal expansion of the resin is reduced. Accordingly, since the resin is suppressed from shrinking in volume when the adhesive strength is small, it is difficult for the resin to peel off from the wiring pattern.

(3) In this semiconductor device, the resin may have a high crosslinking density, so that the glass transition temperature is raised and the shrinkage of the volume is suppressed.

According to this, since the glass transition temperature is high, the difference between the maximum temperature of the process and the glass transition temperature is reduced, and the expansion of the resin volume is reduced, and as a result, the volume shrinkage during cooling is also reduced. And peeling is less likely to occur between the resin and the wiring pattern.

(4) In this semiconductor device, the wiring pattern may be plated.

Although the adhesive strength of the resin is particularly small with respect to the plated wiring pattern, peeling can be avoided by applying the present invention.

(5) In this semiconductor device, the resin is an adhesive and contains conductive particles to form an anisotropic conductive material, and the semiconductor chip is connected to the face via the anisotropic conductive material. It may be implemented down.

By using an anisotropic conductive material, highly reliable bonding can be ensured.

(6) The semiconductor device is mounted on a circuit board according to the present invention.

(7) An electronic apparatus according to the present invention includes the above semiconductor device.

(8) In the method of manufacturing a semiconductor device according to the present invention, a step of providing a resin on the wiring pattern of a substrate on which a wiring pattern electrically connected to electrodes of a semiconductor chip is formed; A step of heating to a temperature above the glass transition temperature, and a step of cooling the resin to a temperature equal to or lower than the glass transition temperature after the heating step;
In the cooling step, when the temperature decreases from the maximum temperature of the heating step to the glass transition temperature, a force generated by shrinkage of the resin is smaller than an adhesive force of the resin to the wiring pattern.

According to the invention, the resin is heated to a temperature above the glass transition temperature and then cooled to a temperature below the glass transition temperature. When the resin exceeds the glass transition temperature, the adhesive strength of the resin to the wiring pattern decreases, and the resin shrinks when the temperature decreases from the temperature exceeding the glass transition temperature to the glass transition temperature. According to the present invention, since the force generated by the shrinkage of the resin is smaller than the adhesive force of the resin to the wiring pattern, peeling between the resin and the wiring pattern is less likely to occur.

(9) In the method of manufacturing a semiconductor device, the resin may be a thermosetting resin, and may be accompanied by a curing reaction during the heating step.

(10) In this method of manufacturing a semiconductor device, the resin may contain a filler for lowering the coefficient of thermal expansion at a temperature equal to or higher than the glass transition temperature, so that the volume shrinkage may be suppressed.

According to this, when the resin is heated to a temperature equal to or higher than the glass transition temperature, that is, when the adhesive strength of the resin to the wiring pattern is small, the coefficient of thermal expansion of the resin is reduced. Accordingly, since the resin is suppressed from shrinking in volume when the adhesive strength is small, it is difficult for the resin to peel off from the wiring pattern.

(11) In this method of manufacturing a semiconductor device, the resin may have a high cross-linking density, thereby increasing a glass transition temperature and suppressing volume shrinkage.

According to this, since the glass transition temperature is high, the difference between the maximum temperature of the process and the glass transition temperature is reduced, and the expansion of the resin volume is reduced. As a result, the volume shrinkage during cooling is also reduced. And peeling is less likely to occur between the resin and the wiring pattern.

(12) In this method of manufacturing a semiconductor device, the wiring pattern may be plated.

In particular, the resin has low adhesive strength to a plated wiring pattern, but by applying the present invention, peeling can be avoided.

(13) In this method of manufacturing a semiconductor device, the resin is an adhesive and contains conductive particles to form an anisotropic conductive material, and the semiconductor chip is made of the anisotropic conductive material. It may be mounted face-down through the interface.

If an anisotropic conductive material is used, bonding can be performed in a simple process.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. The semiconductor device 1 includes a semiconductor chip 10 and a substrate 20. When the planar shape of the semiconductor chip 10 is rectangular (square or rectangular), a plurality of semiconductor chips 10 are arranged on one surface (active surface) of the semiconductor chip 10 along at least one side (including two opposing sides or all sides). Electrodes 12 are formed. The bumps 1 are formed on the electrodes 12 by solder balls, gold wire balls, gold plating, or the like.
4 are provided. The electrode 12 itself may be in the form of a bump. Nickel, chromium, titanium, or the like may be added between the electrode 12 and the bump 14 as a diffusion preventing layer for the bump metal. The bumps 14 may be formed not on the semiconductor chip 10 side but on a part (for example, the land portion 24) of the wiring pattern 21 of the substrate 20.

The overall shape of the substrate 20 is not particularly limited, and may be a rectangle, a polygon, or a combination of a plurality of rectangles, but may be similar to the planar shape of the semiconductor chip 10. . The thickness of the substrate 20 is often determined by its material, but is not limited thereto.
The substrate 20 may be formed of any of an organic or inorganic material, and may be formed of a composite structure thereof, but is preferably punched out. The substrate 20 can be formed by punching out a tape-shaped flexible substrate formed from an organic material.

FIG. 2 is a plan view of the substrate of the semiconductor device shown in FIG. As shown in FIGS. 1 and 2, a plurality of wirings (leads) 22 are formed on one surface of the substrate 20.
The wiring pattern 21 is configured. Each wiring 22
Are formed at both ends. In many cases, the lands 24 and 26 are formed to have a larger width than a portion connecting them. One land 24 is formed on the substrate 20 at a position near the end of the semiconductor device as a final product, and the other land 26
May be formed at a position near the center of the substrate 20.

The substrate 20 has a plurality of through holes 28 formed therein. One of the wirings 22 passes through each through hole 28. The end of the wiring 22 may be located on the through hole 28. When the land 26 is formed at the end of the wiring 22, the land 26 is located on the through hole 28.

A plating layer 30 is formed on the wiring pattern 21 by plating. Plating layer 30
Is formed on the surface of the wiring pattern 21 opposite to the surface to be bonded to the substrate 20. The plating layer 30 is also formed in a region inside the through hole 28 on the bonding surface of the wiring pattern 21 with the substrate 20. Wiring pattern 2
1 may be formed of copper, and the plating layer 30 may be formed of nickel, gold, solder, or tin. By forming the plating layer 30, conductivity is ensured. Specifically, good soldering with external terminals is enabled, and the wiring pattern 2
1 is prevented from being oxidized, and the electrical connection resistance with the bump is reduced. Note that a plating lead (not shown) may be formed by connecting to the wiring pattern 21 and may be subjected to electroplating or electroless plating.

On the wiring pattern 21, a resin 32 is provided. The resin 32 may be an adhesive having an adhesive force such as thermoplastic rubber, silicon, or polyimide, but a thermosetting epoxy resin is often used. this is,
This is because the reliability at high temperatures is often improved. The resin 32 covers and protects the wiring pattern 21 and may be an underfill material. Alternatively, resin 32
Is an anisotropic conductive material containing conductive particles in an adhesive, the anisotropic conductive material is used for electrical connection between the semiconductor chip 10 and the wiring pattern 21. The resin 32 may be a thermosetting resin.

The present embodiment is applicable to a general face-down mounting system in which an active element forming surface of a semiconductor chip 10 and a wiring pattern 21 of a substrate 20 are opposed to each other.
The method using an anisotropic conductive material as shown in the above, the method of heating (pressing if necessary) a semiconductor chip with solder bumps, the method of heating and
The present invention can also be applied to a method of applying pressure (ultrasonic bonding if necessary) or a method of face-down bonding using a curing shrinkage force of a resin. This is the same in the following embodiments.

FIG. 3 is a diagram showing characteristics of the resin 32.
The relationship between the displacement due to expansion (contraction) of the volume and the temperature, that is, the thermal expansion coefficients α1 and α2 are shown. Temperature lower than glass transition temperature (glass transition point) Tg (including room temperature Tr)
From the glass transition temperature Tg to the glass transition temperature Tg, the coefficient of thermal expansion of the resin 32 is represented by α1, indicating a characteristic as a resin (plastic). The glass transition temperature (glass transition point) Tg
Above or above, the thermal expansion coefficient of the resin 32 is α2
The resin 32 is in a rubber state (an elastic state). If the resin 32 is a thermosetting resin, a curing reaction accompanies the heating step.

In general, the coefficient of thermal expansion of a resin rapidly increases when the temperature exceeds the glass transition temperature, and the adhesive strength often decreases rapidly. As a result, when the temperature falls from the maximum temperature Th in the process exceeding the glass transition temperature Tg to the glass transition temperature Tg, the resin may be peeled off due to low adhesive strength. For example, in order to melt solder when a completed semiconductor device is mounted on a circuit board, the semiconductor device may be exposed to a high temperature in a reflow process. Alternatively, in the manufacturing process of the semiconductor device, the resin 32 is exposed to a high temperature equal to or higher than the glass transition temperature Tg in order to soften the resin 32,
It may be unavoidable that the resin 32 is exposed to a high temperature in order to melt a member such as solder.

In this embodiment, the resin 32 has a glass transition temperature Tg from the maximum temperature Th exceeding the glass transition temperature Tg.
When the temperature is lowered, the force generated by the contraction of the volume is smaller than the adhesive force to the wiring pattern 21.

For example, when a silica-based filler is mixed into the resin 32 to reduce or exceed the glass transition temperature (glass transition point) Tg or more, the thermal expansion coefficient α2 is reduced.
Specifically, when a conventional epoxy resin is used as the resin 32, α2 ′ = 200 ppm / ° C., but by mixing a silica-based filler into the resin 32, α2 = 50 ppm.
It can be about ppm / ° C. When the coefficient of thermal expansion α2 is reduced, the contraction of the volume is reduced, and a force sufficient to peel off the wiring pattern 21 is not generated. The shrinkage volume in this case is obtained by (Th−Tg) × α2.

Alternatively, the glass transition temperature of the resin 32 is set to T
g 'may be increased to Tg. For example, the crosslinking density of the resin 32 is increased, that is, the resin 32 containing a bulky molecule is used, or a monomer having a large number of reactive groups is used so that the bulk is increased after the reaction. For example, a resin having a high aromatic component ratio, such as phenol novolak, is used. By doing so, the value of (Th−Tg) becomes smaller, so that the contracted volume becomes smaller, and the resulting force (the force that causes peeling) also becomes smaller. Further, since α1 and α2 are also reduced, the effect is doubled.

As described above, the wiring pattern 21 and the resin 3
Since the adhesiveness with the second member 2 is improved, it is possible to prevent the formation of a gap due to peeling and prevent the accumulation of moisture.

The semiconductor chip 10 may be mounted face down on the substrate 20. A bump 14 of the semiconductor chip 10, a wiring pattern 21 formed on the substrate 20,
Are electrically connected. When the lands 24 and 26 are formed on the wiring 22 forming the wiring pattern 21, one of the lands 24 and the bump 14 are electrically connected.
When the resin 32 is an anisotropic conductive material in which conductive particles are contained in an adhesive, the conductive particles are interposed between the wiring pattern 21 and the bumps 14 to achieve electrical conduction. . The anisotropic conductive material may be an anisotropic conductive film or an anisotropic conductive adhesive.

External terminals 34 are electrically connected to the wiring pattern 21. The external terminal 34 is often a solder ball, but may be a conductive protrusion such as plating or conductive resin. The external terminal 34 is a through hole 28
It can be electrically connected to the wiring pattern 21 via the conductive member inside. An external terminal 34 may be provided directly on the wiring pattern 21 by filling the through hole 28 with a conductive member such as solder. A second wiring that is electrically connected to the wiring pattern 21 through the through hole 28 may be formed on the other surface of the substrate 20, and an external terminal may be provided on the second wiring. In this case, the substrate 20 is a double-sided substrate since wiring is formed on both surfaces. Further, the substrate 2
As 0, a multilayer substrate or a build-up type substrate may be used. When a build-up type substrate or a multi-layer substrate is used, if the wiring pattern 21 is formed on a beta land layer extending in a plane, a microstrip structure without an extra wiring pattern is obtained, so that signal transmission characteristics are further improved. be able to.

FIG. 1 shows a FAN-type in which the wiring pattern 21 is formed only in the mounting area of the semiconductor chip 10 and the external terminal 34 is provided only in the mounting area of the semiconductor chip 10.
Although an IN type semiconductor device is shown, the present invention is not limited to this. For example, the FAN-OUT in which the wiring patterns 21 are drawn out of the semiconductor chip 10 and the external terminals 34 are provided only outside the mounting area of the semiconductor chip 10 is provided.
The present invention can also be applied to a semiconductor device of the FAN-IN / OUT type in which the FAN-IN type is combined with the semiconductor device of the FAN-IN type. In addition, FAN-OUT type or FA
In an N-IN / OUT type semiconductor device, a stiffener may be attached to the outside of the semiconductor chip with a resin covering the wiring pattern.

In addition to the above-described embodiment, before mounting the semiconductor chip, one or more holes (for example, long holes) are preferably partially or preferably not less than half of the outer position of the semiconductor device.
May be formed, and after mounting the semiconductor chip, the remaining portion (for example, a portion between a plurality of holes) of the outer shape position may be punched.

In this embodiment, a semiconductor chip is
(Ball Grid Array) Although the example of face-down mounting (mounting in which the active element forming surface of the semiconductor chip is opposed to the wiring pattern of the substrate) to the substrate is described above, the semiconductor chip is simply mounted face-down to the substrate. This form can be applied to all.

The present embodiment is configured as described above, and its manufacturing method will be described below.

The above-described substrate 20 can be formed by punching a larger substrate (substrate). For example, a plurality of wiring patterns 21 corresponding to a plurality of substrates 20
Is prepared, and a plurality of substrates 20 can be obtained by punching out the tape carrier. The wiring pattern 21 formed on the tape carrier is preferably plated with gold or the like.

The resin 32 is formed on the wiring pattern 21 of the substrate 20.
Is provided. For example, when the resin 32 is an anisotropic conductive material, the resin 32 is disposed between the substrate 20 and the semiconductor chip 10.
Is provided. At this time or thereafter, a step of heating the resin 32 to a temperature above the glass transition temperature may be performed, and then a step of cooling to a temperature equal to or lower than the glass transition temperature may be performed. Even in that case, the maximum temperature T of the heating process
When the temperature decreases from h to the glass transition temperature Tg, the force generated by the contraction of the resin 32 is smaller than the adhesive force of the resin 32 to the wiring pattern 21. As a result, separation does not occur between the resin 32 and the wiring pattern 21.

Then, the semiconductor device 1 can be manufactured by including the step of mounting the semiconductor chip 10 on the substrate 20 and the step of providing the external terminals 34.

FIG. 4 shows a circuit board 50 on which the semiconductor device 1 according to the present embodiment is mounted. Circuit board 5
For 0, an organic substrate such as a glass epoxy substrate is generally used. A wiring pattern 52 made of, for example, copper is formed on the circuit board 50 so as to form a desired circuit, and the electrical connection between the wiring pattern and the external terminal 34 of the semiconductor device 1 is made by mechanical connection. Conduct continuity.

To mount the semiconductor device 1 on the circuit board 50, the semiconductor device 1 is mounted on the wiring pattern 52 of the circuit board 50.
The reflow process may be performed with the external terminal 34 of the above. Then, the wiring patterns 52 and the external terminals 34 are electrically connected by heating and melting the external terminals 34. According to the present embodiment, the resin 32 and the wiring pattern 2
No delamination occurs between them.

As an electronic apparatus 60 having the semiconductor device 1 to which the present invention is applied, a notebook personal computer is shown in FIG.

It should be noted that the constituent element "semiconductor chip" of the present invention is replaced with "electronic element", and an electronic element (regardless of active element or passive element) is mounted on a substrate like a semiconductor chip. Parts can also be manufactured. Electronic components manufactured using such electronic elements include, for example, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, or fuses.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a substrate of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a diagram showing characteristics of a resin according to the embodiment of the present invention.

FIG. 4 is a diagram showing a circuit board on which the semiconductor device according to the present embodiment is mounted.

FIG. 5 is a diagram illustrating an electronic apparatus including the semiconductor device according to the embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 12 Electrode 20 Substrate 21 Wiring pattern 32 Resin

Claims (13)

[Claims] A semiconductor chip, a substrate on which a wiring pattern is formed, a resin provided on the wiring pattern,
A semiconductor device in which, when the temperature decreases from a temperature exceeding a glass transition temperature to a glass transition temperature, the resin has a smaller force caused by volume contraction than an adhesive force to the wiring pattern. 2. The semiconductor device according to claim 1, wherein the resin contains a filler for lowering a coefficient of thermal expansion at a temperature equal to or higher than a glass transition temperature, so that shrinkage in volume is suppressed. 3. The semiconductor device according to claim 1, wherein the resin has a high crosslinking density, thereby increasing a glass transition temperature and suppressing a volume shrinkage. 4. The semiconductor device according to claim 1, wherein said wiring pattern is plated. 5. The semiconductor device according to claim 1, wherein the resin is an adhesive and contains conductive particles to form an anisotropic conductive material. And a semiconductor device mounted face down via the anisotropic conductive material. 6. A circuit board on which the semiconductor device according to claim 1 is mounted. 7. An electronic apparatus comprising the semiconductor device according to claim 1. 8. A step of providing a resin on the wiring pattern of a substrate on which a wiring pattern electrically connected to an electrode of a semiconductor chip is formed, and a step of heating the resin to a temperature exceeding a glass transition temperature. And wherein the resin is cooled to a temperature equal to or lower than the glass transition temperature after the heating step, wherein, in the cooling step, when the temperature decreases from the highest temperature of the heating step to the glass transition temperature, A method for manufacturing a semiconductor device, wherein a force generated by shrinking the resin is smaller than an adhesive force of the resin to the wiring pattern. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the resin is a thermosetting resin, and a curing reaction occurs during the heating step. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the resin contains a filler for lowering a coefficient of thermal expansion at a temperature equal to or higher than a glass transition temperature, so that volume shrinkage is reduced. A method of manufacturing a suppressed semiconductor device. 11. The method for manufacturing a semiconductor device according to claim 8, wherein the resin has a high cross-linking density, thereby increasing a glass transition temperature and suppressing volume shrinkage. Of manufacturing a semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 8, wherein the wiring pattern is plated. 13. The method of manufacturing a semiconductor device according to claim 8, wherein the resin is an adhesive and contains conductive particles to form an anisotropic conductive material. A method for manufacturing a semiconductor device in which a semiconductor chip is face-down mounted via the anisotropic conductive material.