JP2000243785A - Manufacturing method of semiconductor chip - Google Patents

Abstract

(57) Abstract: When forming a functional bump BF and a dummy bump BD, as shown in FIG. 2 (b), after the surface of the surface protective film 17 is flattened, as shown in FIG. 2 (c). As described above, the opening 18 for exposing a part of the surface of the internal wiring 16 is formed in a region of the surface protection film 17 facing the internal wiring 16. Subsequently, by selectively plating the internal wiring 16 exposed through the opening 18 and the flattened surface protective film 17, the functional bump BF and the functional bump BF are formed as shown in FIG. A dummy bump BD is formed. The function bumps BF and the dummy bumps BD can be formed at substantially the same height.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip-on-chip structure in which another semiconductor chip is superimposed on a surface of a semiconductor chip and bonded, or a flip in which the surface of a semiconductor chip is bonded to a printed wiring board. The present invention relates to a method for manufacturing a semiconductor chip applied to a chip bonding structure.

[0002]

2. Description of the Related Art A semiconductor device having a chip-on-chip structure in which a pair of semiconductor chips are opposed to each other and electrically connected to each other by bumps has been proposed, but there are many problems to be solved in realizing the semiconductor device. I have.

[0003]

One of the problems to be solved is that when a semiconductor device having a chip-on-chip structure in which another semiconductor chip is superimposed on and bonded to the surface of a semiconductor chip is sealed with a resin, Due to the pressure from the resin, there is a problem that the semiconductor chip is deformed in a portion not supported by the bumps, and the characteristics of the elements formed on the semiconductor chip are deteriorated.

Therefore, the inventor of the present application has provided a dummy bump on the surface of a semiconductor chip, which does not contribute to electrical connection with another semiconductor chip arranged oppositely, and alleviates the pressure received from a sealing resin by the dummy bump. Thus, it was thought that the deformation of the semiconductor chip could be prevented. When a dummy bump is provided on the surface of a semiconductor chip, the dummy bump is made of the same material as a bump (hereinafter, referred to as a “functional bump”) for electrically connecting the semiconductor chip to another semiconductor chip disposed to face the semiconductor chip. Is preferred. By doing so, the dummy bumps and the functional bumps can be formed in the same step, and an increase in the number of manufacturing steps of the semiconductor chip can be prevented.

However, as shown in FIG. 8, plating using a bump material is selectively performed on a surface protective film 93 in which an opening 92 for exposing a part of the wiring 91 is formed. When the functional bumps 94 and the dummy bumps 95 are formed on the opening 92 and the surface protective film 93, respectively, the functional bumps 94 are formed at the peripheral portion of the opening 92 more than the other portions. Is formed higher by Δh.
If the functional bumps 94 are formed higher than the dummy bumps 95, the dummy bumps 95 will not be sufficiently bonded to the other semiconductor chips when this semiconductor chip is bonded to another semiconductor chip. I can't show it.

Accordingly, an object of the present invention is to solve the above-mentioned technical problems and to manufacture a semiconductor chip capable of making the height of an electrical connection portion (functional bump) substantially equal to the height of a dummy connection portion (dummy bump). Is to provide a way.

[0007]

Means for Solving the Problems and Effects of the Invention In order to achieve the above object, the invention according to claim 1 is a method for joining an electric connection with the solid to a surface opposed to the solid surface. A method of manufacturing a semiconductor chip having an electrical connection portion for forming a dummy connection portion that does not contribute to the electrical connection with the solid, wherein an internal wiring is provided on a semiconductor substrate serving as a base of the semiconductor chip; Laminating a surface protection film on the internal wiring, flattening the surface protection film, forming an opening in the surface protection film to expose a part of the internal wiring, After the step of flattening the protective film and the step of forming the opening,
The internal wiring exposed through the opening and the flattened surface protection film are selectively plated to insulate the electrical connection and the internal wiring connected to the internal wiring through the opening. Forming a dummy connection portion formed.

The solid surface may be the surface of another semiconductor chip or the surface of a wiring board. As in the present invention, after the surface of the surface protection film is flattened, selective plating for forming the electrical connection portion and the dummy connection portion is performed, so that the electrical connection portion and the dummy connection portion have substantially the same height. Can be formed.

Therefore, the electric connection portion and the dummy connection portion can be satisfactorily connected to the solid surface. As a result, the electrical connection with the solid surface can be satisfactorily performed, and the stress generated on the semiconductor chip and the solid surface can be favorably reduced by the dummy connection portion. According to a second aspect of the present invention, there is provided a semiconductor which is joined to a solid surface and has an electric connection portion for electric connection with the solid and a dummy connection portion not contributing to the electric connection with the solid on a surface facing the solid surface. A method for manufacturing a chip, comprising: arranging internal wiring on a semiconductor substrate; laminating a surface protective film on the internal wiring; and polishing and flattening the surface protective film, A step of exposing the surface of the internal wiring from the surface protective film, and selectively plating the internal wiring and the flattened surface protective film exposed from the surface protective film to expose the surface from the surface protective film. Forming an electrical connection connected to the surface of the internal wiring and a dummy connection insulated from the internal wiring.

[0010] As in the present invention, the internal wiring is exposed by polishing the surface protective film, and then selective plating for forming the electrical connection portion and the dummy connection portion is performed. The dummy connection portion can be formed at substantially the same height. Therefore, similarly to the first aspect of the present invention, the electrical connection portion and the dummy connection portion can be satisfactorily connected to the solid surface. As a result, the electrical connection with the solid surface can be satisfactorily performed, and the stress generated on the semiconductor chip and the solid surface can be favorably reduced by the dummy connection portion.

The step of polishing and flattening the surface protective film is preferably continued until the surface of the surface protective film and the surface of the internal wiring exposed from the surface protective film are substantially flush. . According to a third aspect of the present invention, there is provided a semiconductor which is joined to a solid surface and has an electric connection portion for electric connection with the solid and a dummy connection portion not contributing to the electric connection with the solid on a surface facing the solid surface. A method of manufacturing a chip, comprising: arranging an internal wiring on a semiconductor substrate; laminating a surface protective film on the internal wiring; planarizing the surface protective film; Forming a recess in the surface protection film and an opening for exposing a part of the internal wiring; laminating a metal film on the surface protection film in which the recess and the opening are formed; Removing the metal film laminated outside the opening to form a dummy connection portion insulated from the internal wiring and an electrical connection portion connected to the internal wiring, respectively, in the concave portion and the opening. A semiconductor chip manufacturing method characterized by and.

According to a fourth aspect of the present invention, the step of forming the dummy connection portion and the electrical connection portion includes a step of polishing the surface of the metal film by a chemical mechanical polishing method. Preferably, the step of polishing by the polishing method is continued until the surface of the surface protective film and the surfaces of the metal films in the openings and recesses are substantially flush. As in the present invention, a concave portion and an opening are formed in a flattened surface protective film, a metal film is laminated on the surface protective film in which the concave portion and the opening are formed, and then laminated outside the concave portion and the opening. By removing the deposited metal film and forming a dummy connection portion and an electrical connection portion in the concave portion and the opening portion, respectively, the surfaces of the electrical connection portion and the dummy connection portion are formed substantially flush with the surface of the surface protection film. can do.

Therefore, when the semiconductor chip is bonded to a solid having, for example, functional bumps and dummy bumps, the functional bumps and the dummy bumps, which are provided solid, respectively, are preferably connected to the electrical connection portion and the dummy connection portion of the semiconductor chip. Can be joined. This makes it possible to make good electrical connection between the semiconductor chip and the solid, and to satisfactorily relieve the stress generated in the semiconductor chip and the solid.

[0014]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device to which a semiconductor chip according to an embodiment of the present invention is applied. This semiconductor device has a so-called chip-on-chip structure, and is configured by superposing and bonding a child chip 2 to a surface 11 of a parent chip 1, sealing them with a resin, and putting them in a package 3. Have been.

The parent chip 1 is made of, for example, a silicon chip. The surface 11 of the parent chip 1 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. On this surface protective film, a plurality of pads 12 for external connection are arranged so as to be exposed near the periphery of the surface 11 of the parent chip 1 having a substantially rectangular planar shape. The external connection pad 12
It is connected to a lead frame 14 by a bonding wire 13.

The child chip 2 is made of, for example, a silicon chip. The surface 21 of the child chip 2 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on the semiconductor substrate, and the outermost surface is covered with a surface protection film made of, for example, silicon nitride. Child chip 2
Is bonded to the parent chip 1 by a so-called face-down method in which the front surface 21 faces the front surface 11 of the parent chip 1 and is supported by a plurality of bumps provided between the parent chip 1 and the mother chip 1. More specifically, a plurality of child-side bumps B2 are formed on the surface 21 of the child chip 2 so as to protrude.
The parent bumps B1 are respectively formed at positions corresponding to. And the child chip 2 is a child-side bump B2.
Are supported above the parent chip 1 by being connected to the corresponding parent bumps B1.

The child-side bump B2 includes a functional bump BF connected to the internal wiring of the child chip 2 and a dummy bump BD insulated from an internal circuit of the child chip 2.
On the other hand, the parent-side bump B1 also includes a functional bump BF connected to the internal wiring of the parent chip 1 and a dummy bump BD insulated from the internal circuit of the parent chip 1. The functional bumps BF of the parent chip 1 and the functional bumps BF of the child chip 2 are provided to face each other.
By connecting F, the internal wiring of the parent chip 1 and the internal wiring of the child chip 2 are electrically connected. On the other hand, the dummy bumps BD of the parent chip 1 and the dummy bumps BD of the child chip 2 are provided to face each other, and the connection between the dummy bumps BD is made by the electric connection between the internal circuits of the parent chip 1 and the child chip 2. Does not contribute to the connection.

FIG. 2 is a cross-sectional view showing a configuration of a main part of the parent chip 1 and a manufacturing process. An interlayer insulating film 15 made of, for example, silicon oxide is formed on a semiconductor substrate (not shown) serving as a base of the parent chip 1, and an internal wiring 16 is provided on the interlayer insulating film 15. I have. The surfaces of the interlayer insulating film 15 and the internal wiring 16 are covered with a surface protection film 17.
Over the opening 18 formed in the surface protection film 17, an oxidation-resistant metal (for example, gold, platinum,
A functional bump BF is formed as an electrical connection made of silver, palladium, iridium, or the like. on the other hand,
The dummy bump BD as a dummy connection portion is formed on the surface protection film 17 using the same material as the functional bump BF.

The functional bump BF and the dummy bump BD
They are formed at substantially the same height, and can be formed simultaneously in the manufacturing process. That is, the functional bump B
In forming the dummy bumps BD and the dummy bumps BD, first, FIG.
As shown in (a), a surface protection film 17 made of, for example, silicon nitride is laminated on the interlayer insulating film 15 on which the internal wiring 16 is provided. The thickness of the surface protective film 17 is
The thickness is set larger than the thickness of the internal wiring 16.

Next, by performing a flattening process,
As shown in FIG. 2B, the surface of the surface protection film 17 is flattened. Thereafter, as shown in FIG. 2C, the internal wiring 1 is formed on the surface protective film 17 by photolithography.
An opening 18 for exposing a part of the surface of the internal wiring 16 is formed in a region opposed to 6. Subsequently, a seed film (not shown) is formed on the surface protection film 17 in which the opening 18 is formed. For example, when the functional bumps BF and the dummy bumps BD are made of Au (gold), this seed film is formed on the surface protective film 17 by TiW sputtering.
It is preferable that a (titanium tungsten) film is formed and Au is deposited on the TiW film by a sputtering method.

Next, as shown in FIG. 2D, after a resist pattern 19 is selectively formed on the seed film by photolithography, plating using the material of the functional bump BF and the dummy bump BD is performed. As a result, a plating material is deposited on the opening 18 and the region where the dummy bump BD is to be formed. At this time, the plating material grows substantially uniformly on the area where the opening 18 and the dummy bump BD are to be formed, and the surface of the surface protection film 17 is flattened by the HDP process. The plating material will be deposited at approximately the same height on the portion 18 and on the region where the dummy bump BD is to be formed.

Then, after plating is completed, the resist pattern 19 on the seed film is removed, and the seed film exposed by removing the resist pattern 19 is removed, so that the surface is protected as shown in FIG. A functional bump BF and a dummy bump BD having substantially the same height from the surface of the film 17 to the upper end surface are obtained. According to this embodiment, the surface protection film 17 is stacked thicker than the internal wiring 16,
After the surface of the surface protective film 17 is flattened, selective plating for the functional bump BF and the dummy bump BD is performed, so that the functional bump BF and the dummy bump BD having substantially the same height can be obtained. Therefore, if the child chip 2 is also manufactured in the same manner as the parent chip 1, when the parent chip 1 and the child chip 2 are joined, the child bump 2 is attached to the functional bump BF and the dummy bump BD of the parent chip 1 respectively. The functional bump BF and the dummy bump BD of the chip 2 can be satisfactorily bonded.
Thus, the parent chip 1 and the child chip 2 can be reliably electrically connected, and the parent chip 1 and the child chip 2 can be electrically connected.
Can be favorably alleviated.

Further, since the surface of the surface protective film 17 is flattened, the resist pattern 19 can be favorably patterned by the photolithography technique, so that the functional bumps BF and the dummy bumps BD are located at desired positions. It can be formed with high accuracy. In this embodiment, the surface of the surface protection film 17 is flattened by a flattening process.
(Chemical Vapor Deposition)
By depositing the above material, a surface protection film 17 having a substantially flat surface may be formed on the interlayer insulating film 15.

FIG. 3 is a cross-sectional view showing a configuration of a main part and a manufacturing process of a semiconductor chip according to a second embodiment of the present invention. In FIG. 3, parts corresponding to the respective parts in FIG. 2 are denoted by the same reference numerals as in FIG. 2, and the following description will focus on differences from the first embodiment. explain. Semiconductor chip 4 according to the second embodiment
Can be used, for example, in place of the parent chip 1 of the first embodiment described above.
On the upper surface, a surface wiring 41 as an electrical connection portion connected to the internal wiring 16 and a dummy bump BD as a dummy connection portion are provided. In this embodiment, the functional bumps BF and the dummy bumps BD of the child chip 2 are bonded to the surface wirings 41 and the dummy bumps BD provided on the surface protection film 17, respectively. Chip-on-chip bonding is achieved.

The surface wiring 41 is made of the same material as the dummy bump BD, and is formed simultaneously with the dummy bump BD in the manufacturing process. That is, FIG.
As shown in FIG.
After the surface protective film 17 is laminated thereon, CMP (Chemical
The surface of the surface protection film 17 is flattened by a (Mechanical Polishing) process. This C
The MP process is continued until almost the entire surface (upper surface) of the internal wiring 16 is exposed and the exposed surface of the internal wiring 16 is flattened, as shown in FIG. As a result, the surface of the internal wiring 16 and the surface of the surface protection film 17 become substantially flush.

Thereafter, a seed film (not shown) is formed on the surfaces of the planarized internal wiring 16 and surface protection film 17, and a region facing the internal wiring 16 on this seed film and a dummy bump BD are formed. In the area other than the area to be
As shown in FIG. 3C, after the resist pattern 19 is formed by the photolithography technique, the surface wiring 41 is formed.
Then, plating using the material of the dummy bump BD is performed.

Thus, the plating material is deposited at substantially the same height on the region facing the internal wiring 16 and the region where the dummy bump BD is to be formed. Therefore, after completion of the plating, the resist pattern 19 on the seed film is removed, and the seed film exposed by the removal of the resist pattern 19 is removed, so that almost the same height as shown in FIG. The surface wiring 41 and the dummy bump BD having the same can be obtained.

According to this embodiment, the internal wiring 16 is exposed by polishing the surface protective film 17, and after the exposed surface of the internal wiring 16 and the surface of the surface protective film 17 are substantially flush with each other. , Selective plating for the surface wiring 41 and the dummy bump BD is performed. Thus, the surface wiring 41 and the dummy bump BD having substantially the same height H can be obtained, and the same effects as those of the first embodiment can be obtained.

The surface of the internal wiring 16 and the surface protection film 1
7 are almost flush with each other, so that the surface wiring 41
The upper surface of the surface wiring 41 can be formed flat without causing unevenness (see FIG. 2E) due to the step between the internal wiring 16 and the surface protection film 17 on the upper surface of the substrate. Thereby, the bonding between the surface wiring 41 and the functional bumps BF of the sub chip 2 can be performed more favorably.

FIG. 4 is a cross-sectional view showing the configuration and manufacturing steps of a main part of a semiconductor chip according to still another embodiment of the present invention. In FIG. 4, portions corresponding to the respective portions in FIG. 2 are denoted by the same reference numerals as those in FIG. 2, and the following description will focus on differences from the first embodiment. explain. The semiconductor chip 5 according to the third embodiment can be used, for example, in place of the parent chip 1 of the first embodiment described above.
A function pad 51 as an electrical connection connected to 6 and a dummy pad 52 as a dummy connection insulated from the internal circuit are provided in a state embedded in the surface protection film 17. In the third embodiment, the functional bumps BF and the dummy bumps BD of the child chip 2 are bonded to the functional pads 51 and the dummy pads 52 provided on the surface protection film 17, respectively. Chip-on-chip bonding with the daughter chip 2 is achieved.

The function pad 51 and the dummy pad 52
The same metal having oxidation resistance (eg, gold, platinum,
Silver, palladium or iridium), and are formed simultaneously in the manufacturing process. When forming the functional pad 51 and the dummy pad 52, first, FIG.
As shown in (a), a surface protection film 17 made of, for example, silicon nitride is laminated on the interlayer insulating film 15 on which the internal wiring 16 is provided. The thickness of the surface protective film 17 is
The thickness is set larger than the thickness of the internal wiring 16.

Next, as shown in FIG. 4B, the surface of the surface protection film 17 is flattened by performing the HDP process. Thereafter, as shown in FIG. 4C, the internal wiring 1 is formed on the surface protection film 17 by photolithography.
An opening 18 and a concave portion 53 for exposing a part of the surface of the internal wiring 16 are formed in a region facing the semiconductor device 6 and a region where the dummy pad 52 is to be formed.

Subsequently, after a seed film (not shown) is formed on the surface protective film 17 in which the opening 18 and the concave portion 53 are formed, a functional pad 51 and a dummy pad 52 are formed on the surface of the seed film. Electroplating using the material is performed. This electroplating is continued until the inside of the opening 18 and the recess 53 is filled with the plating material as shown in FIG. 4D, whereby the opening 18 and the recess 53 are formed on the surface protection film 17. A metal film 54 having a thickness greater than the depth is formed.

Thereafter, the metal film 54 formed on the surface protection film 17 is chemically and physically polished by performing a CMP process. Then, as shown in FIG.
All of the metal film 54 outside the opening 18 and the concave portion 53 is removed, and the surface 17a of the surface protection film 17 is exposed. The surface 17a and the plating material (metal film 54) deposited in the opening 18 and the concave portion 53 are removed. When the surface is almost flush with the surface, the CMP process is terminated. Thereby, the surface protective film 1
7, the functional pad 5 having a surface substantially flush with the surface of the surface protection film 17 is provided in the opening 18 and the concave portion 53, respectively.
1 and the dummy pad 52 can be obtained.

Therefore, when the child chip having the functional bumps BF and the dummy bumps BD is bonded to the parent chip 1, the functional pads 51 and the dummy pads 52
Then, the functional bumps BF and the dummy bumps BD of the child chips can be satisfactorily bonded. As a result, the parent chip 1 and the child chip can be reliably electrically connected, and the stress generated in the parent chip 1 and the child chip can be favorably reduced.

Although the three embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, as shown in FIG. 5 or FIG. 6, the present invention provides a semiconductor chip having a so-called multilayer wiring structure in which a plurality of internal wirings 61 and 62 are arranged one above the other via an interlayer insulating film 63. Can also be applied. In this case, the surface protection film 64 laminated on the outermost surface
Only the surface protection film 64 may be planarized, or both the surface protection film 64 and the interlayer insulating film 63 provided below the surface protection film 64 may be planarized.

In the first embodiment, the electrical connection between the parent chip and the child chip is achieved by joining the functional bumps of the child chip to the functional bumps of the parent chip. Alternatively, on the surface protection film of the child chip, a surface wiring as an electrical connection portion connected to the internal wiring through an opening formed in the surface protection film is provided, and this surface wiring is connected to the child chip or the parent chip. The electrical connection between the parent chip and the child chip may be achieved by joining the functional bumps. In addition, the surface wiring may be provided on both the parent chip and the child chip, and the surface wirings may be joined to each other to achieve electrical connection between the parent chip and the child chip.

When a surface wiring as an electric connection portion is provided on the surface protection film, the surface protection film having a thickness larger than the thickness of the internal wiring is formed on the interlayer insulating film provided with the internal wiring. Is formed to planarize the surface of the surface protective film, and then an opening is formed in the planarized surface protective film.
Then, a seed film is deposited on the surface of the surface protective film in which the opening is formed by, for example, a sputtering method, and plating is selectively performed on a portion of the seed film facing the opening and a portion where the surface wiring is to be formed. By doing so, it is preferable to form the surface wiring drawn out from the opening onto the surface protection film. As a result, the following effects can be obtained.

As shown in FIG. 7, the internal wirings 71, 72,
When the surface protection film 74 formed on the surface 73 has a mushroom-shaped cross section, a seed film is attached to the surface of the surface protection film 74 by a sputtering method, and selective plating is performed on the seed film to form a surface. When the wiring 75 is formed, the internal wirings 71, 72 and the internal wiring 72,
Since the seed film does not adhere well on the surface protection film 74 between the layers 73, plating does not grow in this portion, and the surface protection film 7
There is a possibility that a void may be generated between the wiring 4 and the surface wiring 75, or the surface wiring 75 may be disconnected. On the other hand, when the surface wiring is formed after the surface protection film is flattened, the seed film can be satisfactorily deposited on the entire surface of the surface protection film. There is no risk of occurrence.

Further, in the above-described second and third embodiments, the case where the method of manufacturing a semiconductor chip according to each embodiment is applied to the manufacture of a parent chip is taken as an example.
The manufacturing methods according to the second and third embodiments can also be applied to the manufacture of a child chip. Further, in the above-described embodiment, the parent chip and the child chip are both chips made of silicon.
A semiconductor chip using any other semiconductor material such as a gallium arsenide semiconductor or a germanium semiconductor may be used.
In this case, the semiconductor material of the parent chip and the semiconductor material of the child chip may be the same or different.

Further, in the above-described embodiment, the chip-on-chip structure has been described. However, the semiconductor chip according to the present invention has a flip-chip bonding structure in which the surface of the semiconductor chip is opposed to the printed wiring board and bonded. Also applicable to In addition, various design changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device to which a semiconductor chip according to a first embodiment of the present invention is applied;

FIG. 2 is a cross-sectional view showing a configuration and a manufacturing process of a main part of a parent chip.

FIG. 3 is a cross-sectional view illustrating a configuration and a manufacturing process of a main part of a semiconductor chip according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a configuration and a manufacturing process of a main part of a semiconductor chip according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view for describing a configuration example of a semiconductor chip having a multilayer wiring structure to which the present invention is applied.

FIG. 6 is a cross-sectional view for describing another configuration example of a semiconductor chip having a multilayer wiring structure to which the present invention is applied.

FIG. 7 is a cross-sectional view for describing an effect when the method for manufacturing a semiconductor chip according to the first embodiment is applied to formation of a surface wiring;

FIG. 8 is a cross-sectional view for describing a problem that occurs when a dummy bump is formed in the same step as a functional bump.

[Explanation of symbols]

 Reference Signs List 1 parent chip (semiconductor chip) 11 surface (surface opposed to solid surface) 16 internal wiring 17 surface protective film 18 opening BF functional bump (electric connection) BD dummy bump (dummy connection) 2 child chip (solid) 21 surface (Solid Surface) 4 Semiconductor Chip 41 Surface Wiring (Electrical Connection) 5 Semiconductor Chip 51 Function Pad (Electrical Connection) 52 Dummy Pad (Dummy Connection) 53 Recess 54 Metal Film 61, 62 Internal Wiring (Electrical Connection) 64 Surface protective film 65 Surface wiring (electrical connection)

Claims (4)

[Claims] 1. A semiconductor chip which is joined to a solid surface and has an electric connection portion for electric connection with the solid and a dummy connection portion not contributing to the electric connection with the solid on a surface facing the solid surface. A method comprising: arranging an internal wiring on a semiconductor substrate forming a base of the semiconductor chip; laminating a surface protective film on the internal wiring; and planarizing the surface protective film; A step of forming an opening for exposing a part of the internal wiring in the surface protection film; and a step of flattening the surface protection film and a step of forming the opening. By selectively plating the internal wiring and the flattened surface protection film, an electric connection portion connected to the internal wiring through the opening and a dummy connection insulated from the internal wiring. The method of manufacturing a semiconductor chip, which comprises a step of forming a. 2. Production of a semiconductor chip which is joined to a solid surface and has on its surface facing the solid surface an electrical connection for electrical connection with the solid and a dummy connection which does not contribute to the electrical connection with the solid. A method of arranging an internal wiring on a semiconductor substrate, a step of laminating a surface protective film on the internal wiring, and polishing and flattening the surface protective film to form the internal wiring. A step of exposing a surface from the surface protective film; and selectively plating the internal wiring exposed from the surface protective film and the flattened surface protective film to thereby expose the internal wiring from the surface protective film. Forming an electrical connection portion connected to the surface of the semiconductor chip and a dummy connection portion insulated from the internal wiring. 3. Production of a semiconductor chip which is joined to a solid surface and has an electric connection portion for electric connection with the solid and a dummy connection portion not contributing to the electric connection with the solid on a surface facing the solid surface. A method, comprising: arranging an internal wiring on a semiconductor substrate; laminating a surface protective film on the internal wiring; planarizing the surface protective film; and a planarized surface protective film. Forming a concave portion and an opening for exposing a part of the internal wiring, a step of laminating a metal film on the surface protection film having the concave portion and the opening formed therein, Forming a dummy connection portion insulated from the internal wiring and an electrical connection portion connected to the internal wiring, respectively, in the concave portion and the opening by removing the metal film laminated on The method of manufacturing a semiconductor chip according to claim Mukoto. 4. The step of forming the dummy connection section and the electrical connection section includes a step of polishing the surface of the metal film by a chemical mechanical polishing method. The step of polishing by the chemical mechanical polishing method includes: 4. The method of manufacturing a semiconductor chip according to claim 3, wherein the process is continued until the surface of the surface protective film and the surfaces of the metal films in the openings and the recesses are substantially flush.