JP2000242231A - Method for driving AC plasma display panel and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce display brightness and stabilize sustain discharge of an AC type PDP with high definition and high gradation without accompanying a reduction in a period of a sustain pulse and a reduction in the number of pulses in a sustain period. Improve sex. A 2N scanning line is divided into two, and when one block is in an address period AD0, the other block is set in a sustain period S1. The sustain electrodes and scan electrodes belonging to the block in the sustain period S1 are supplied with (Von + Voff) with respect to the voltages Von and Voff based on the image data.
f) An AC sustaining pulse that changes between the voltage Vg and the voltage Vs0 that satisfies the relation that (/ 2) and (Vs0 + Vg) / 2 + 10 Volt are substantially equal is applied. When one block is in the erasing period R0 or the address period AD0, a freezing period F is set for the other block so that the discharge cells belonging to the block maintain the state immediately before. If both blocks are in the sustain period, the sustain period S2 is set as the period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an AC plasma display panel (hereinafter, also referred to as "AC PDP" or simply "PDP").
In particular, the present invention relates to a driving method suitable for high definition and high gradation of an AC type PDP.

[0002]

2. Description of the Related Art FIG. 11 shows a general conventional AC type PDP.
FIG. 2 is an exploded perspective view showing the structure of FIG.

[0003] As shown in FIG.
51P (hereinafter simply referred to as “PDP51P”)
Front panel 51FP and rear panel 51RP are arranged such that cathode film 4P and the top of barrier rib 7P are in contact with each other to form discharge gas space or discharge space 51SP. The front panel 51FP and the rear panel 51RP are sealed at a peripheral portion (not shown), and a discharge gas such as a Ne-Xe mixed gas or a He-Xe mixed gas is sealed in the discharge space 51SP.

In the front panel 51FP, 2S strip-shaped transparent electrodes 1P are formed on the surface of the front glass substrate 5P serving as the display surface on the discharge space 51SP side, in parallel with the surface.
They are formed parallel to each other along the direction D2. Furthermore,
A strip-shaped bus electrode 2P made of a metal material for supplementing the conductivity of the transparent electrode 1P and supplying a voltage to the electrode 1P is provided on the surface of the transparent electrode 1P on the discharge space 51SP side.
It is formed along P. The (plural) electrodes having a structure composed of the transparent electrode 1P and the bus electrode 2P are paired with each other every two adjacent electrodes, and one pair of the electrodes forms one scanning line or display line. I have. At this time,
As shown in FIG. 11, the n-th (1 ≦ n ≦ S) scanning line S
Ln is constituted by two electrodes Xn and Yn that form a pair with each other. Each of the bus electrodes 2P of the electrodes Xn and Yn is a part of the surface of the transparent electrode 1P on the side of the scanning lines SLn-1 and SLn + 1 adjacent to the scanning line SLn, that is, the scanning line Sn.
It is formed at a position farthest from the central axis of Ln. In addition, a region between the opposing edges of the electrode pair Xn and Yn (each transparent electrode 1P thereof) (including a three-dimensional region in the third direction D3 perpendicular to the surface of the front glass substrate 5P) is referred to as “ This is referred to as "internal gap G".

[0005] A dielectric or dielectric layer 3P is formed over the entire surface of the front glass substrate 5P so as to cover the transparent electrode 1P and the bus electrode 2P, and a discharge space of the dielectric 3P is formed. On the surface on the 51SP side,
An MgO vapor-deposited film or a cathode film 4P functioning as a cathode during discharge is formed. The dielectric layer 3
P and the cathode film 4P are also collectively referred to as a “dielectric layer”.

On the other hand, on the rear panel 51RP, on the surface of the rear glass substrate 9P on the side of the discharge space 51SP, along the first direction D1 orthogonal to the second and third directions D2 and D3, that is, the electrodes Xn and M writing electrodes or address electrodes 6P (or Am (1 ≦ m ≦ M)) are formed to extend in the direction orthogonal to Yn, and the back glass substrate 9P is formed so as to cover the address electrodes 6P. A glaze layer or overglaze layer 10P made of a dielectric is formed over the entire surface. A barrier rib 7P is formed on the surface of the overglaze layer 10P on the discharge space 51SP side located in the region between the adjacent address electrodes 6P. The barrier rib 7P is
It may be formed along a scanning line, that is, on a region corresponding to between adjacent scanning lines along the second direction D2. Then, red, green, and blue colors are respectively formed on the surface or inner surface of the U-shaped groove formed by the side wall surfaces of the adjacent barrier ribs 7P facing each other and the surface of the overglaze layer 10P on the discharge space 51SP side. Phosphors or phosphor layers 8RP, 8GP, 8BP (each of which is collectively referred to as “phosphor (layer) 8P”) that emits each fluorescent color are formed.

In the AC type PDP 51P, the structure at each point where the scanning line formed by the electrode pair and the address electrode 6P cross three-dimensionally forms one discharge cell or one light emitting cell as one pixel in the display panel. And a large number of the discharge cells are arranged in a matrix.
A screen or a display area of P is constituted. In the following description, the scanning line SLn (therefore, the electrode pair Xn,
The discharge cell or the light emitting cell at the position where the address electrode Yn crosses the address electrode Am three-dimensionally is referred to as "address (n, m) discharge cell or light emitting cell". And each electrode X
By applying a predetermined voltage to n, Yn, and Am, a discharge is generated in the discharge space 51SP of the discharge cell at the address (n, m).

As an example of a PDP driving method, for example, 1
There is a method of driving by dividing the video display time for a screen into a plurality of subfields each having an erasing period, an address period, and a sustaining period. In such a driving method, first,
The display history of the immediately preceding subfield is deleted during the deletion period. In the subsequent address period, based on the input image data, information as to whether or not to generate a sustain discharge in a subsequent sustain period is given to each discharge cell. At this time, the electrode Yn as a scanning electrode (in contrast, the electrode Xn is referred to as a “sustain electrode X”
n)) (scan)
At the same time, by applying a predetermined voltage Von or voltage Voff based on the input image data to the address electrodes Am, the above information is written to all the discharge cells.
More specifically, a write counter discharge is generated between the address electrode Am to which the voltage Von based on the image data in the ON state is applied and the scan electrode Yn to which the voltage (−Vy) is applied. Then, the pair of electrodes X is triggered by the opposite discharge.
A writing surface discharge is generated between n and Yn to accumulate wall charges as the information on each surface of the cathode film 4P located above the electrodes Xn and Yn (at this time, a voltage is applied to the sustain electrode Xn). Vx is applied). Then, in the subsequent sustain period, a sustain discharge for performing display light emission is generated in the discharge cell in which the information has been written, whereby PD
The image of P is displayed.

[0009]

By the way, as the resolution and gradation of AC type PDP are promoted, the number of scanning lines or 1 is required.
Since the number of subfields that compose the screen increases,
The ratio of the writing operation period or the address period to the video display time for one screen increases.

At this time, in order to realize a desired level of high definition or high gradation, it is necessary to reduce the sustain operation period or the time allocated to the sustain period by an increase in the ratio of the address period. In this case, if the number of sustain pulses applied to the electrodes Xn and Yn in the sustain period is reduced to reduce the time allotted for the period, the display luminance will decrease. Therefore, in order to maintain the display luminance at the same level as that of the related art, a measure to secure the same number of sustain pulses as in the conventional driving method by shortening the period of the sustain pulse is considered. However, if the period of the sustain pulse is shortened, another problem in display quality that the start of the sustain discharge becomes unstable is caused.

On the other hand, a countermeasure for suppressing an increase in the occupation time of the address period itself can be considered. Such a measure can be realized by shortening the time of the address operation or the address operation per scanning line, that is, the period of the address scanning. However, when the period of the address pulse or the address pulse is shortened, there arises a problem that the start of the address discharge becomes unstable similarly to the shortening of the period of the sustain pulse.

Therefore, in order to stably start the address discharge while shortening the period of the address pulse, a voltage for generating the address discharge, that is, the voltage Von applied to the address electrode Am and the selected scanning voltage are selected. It is conceivable to make the voltage (-Vy) applied to the electrode Yn and the voltage difference (Von + Vy) larger. At this time, the voltage value Vy
Is larger, the voltage or voltage difference (Voff) applied to the discharge cells that do not need to generate the address discharge is increased.
+ Vy) also increases. As a result, an address discharge is likely to occur erroneously in the discharge cells corresponding to the image data in the OFF state (the occurrence of an erroneous address discharge).

Therefore, in order to further increase the voltage difference (Von + Vy), it is conceivable to increase the voltage Von. However, when the voltage Von is increased, the voltage difference between the voltages applied to the address electrodes Am or the switching width (Von-Voff) increases. That is, the load on the address electrode drive IC increases. At this time, in the case where the drive IC, which is required to operate at a higher speed with higher definition and higher gradation of the PDP, is required to further have a performance capable of withstanding a high load, the cost related to the drive IC, The cost of the plasma display device becomes very high.

The present invention has been made in view of the above-mentioned problems, and has been made without inconvenience in displaying images.
It is a first object of the present invention to provide a method of driving an AC plasma display panel capable of realizing higher definition and higher gradation of the AC plasma display panel.

It is a second object of the present invention to provide a plasma display device capable of displaying a high-quality image by realizing the first object.

[0016]

According to a first aspect of the present invention, there is provided a method of driving an AC type plasma display panel, comprising: a first substrate having a plurality of strip-shaped address electrodes arranged at least in parallel with each other; At least a plurality of pairs of electrodes, each of which is arranged in a direction intersecting the address electrodes and forms a scanning line and includes a plurality of strip-shaped sustaining electrodes and scanning electrodes, and a dielectric layer covering the pair of electrodes. A substrate is disposed via a discharge space filled with a discharge gas, and a plurality of discharge cells formed at each three-dimensional intersection between the plurality of address electrodes and the plurality of scanning lines are arranged in a matrix. A method for driving an AC type plasma display panel having a display area comprising:
After dividing the video display time for a screen into a plurality of subfields, each of the plurality of subfields generates an address discharge based on image data in at least a predetermined discharge cell among the plurality of discharge cells. And a sustain period for performing a sustain operation for generating a predetermined number of sustain discharges in the predetermined discharge cells in which the address discharge has occurred. After dividing the display area into blocks by dividing a scanning line into a plurality of blocks, during the video display time for one screen, the discharge cells for the discharge cells belonging to a predetermined one of the plurality of blocks are The address operation and the sustain operation for the discharge cells belonging to blocks other than the predetermined one block may be performed in parallel. The features.

(2) The method for driving an AC plasma display panel according to the invention described in claim 2 is the method for driving an AC plasma display panel according to claim 1, wherein the address electrode is provided in the address period. , A voltage based on the ON state of the image data is denoted by a symbol Von.
A voltage based on the FF state is denoted by a symbol Voff, and a voltage applied to one of the sustain electrode and the scan electrode in the sustain period is denoted by a symbol Vs0. A voltage applied to the other of the sustain electrodes is denoted by a symbol Vg, and the voltage applied to the surface of the first substrate on the discharge space side generated by the charges accumulated in the discharge cells through the address discharge. When the potential difference of the surface of the second substrate on the side of the discharge space is denoted by a symbol Vw, the voltages are represented by Voff <{(Vs0 + Vg) / 2 + Vw} <Vo
It satisfies the relationship given by n.

(3) The method for driving an AC plasma display panel according to the invention according to claim 3 is the method for driving an AC plasma display panel according to claim 2, wherein the image display for one screen is performed. During time, at least one or more of the blocks are in the sustain period, and
Each of the blocks further includes a period which is not included in the address period, and in the period, one of the voltage Von and the voltage Voff is applied to the address electrode.

(4) A plasma display device according to a fourth aspect of the present invention is driven by the method for driving an AC type plasma display panel according to any one of the first to third aspects.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, the prerequisite technology will be described.

(Base Technology) As a base technology, an AC type PD
An example of a method of driving P will be described. The driving method according to the base technology is proposed in Japanese Patent Application No. 9-173962.

In the driving method of an AC type PDP according to the base technology, a video display time for one screen is divided into a plurality of fields as a driving method for displaying a color image. Here, as shown in FIG. 1, a case where a color image of 256 gradations is obtained by dividing a video display time for one screen into eight subfields SF1 to SF8 will be described.

Each of the subfields SF1 to SF8 further includes an erasing operation period or erasing period RA or RB for erasing the light emission history in the immediately preceding subfield, and the light emission / emission of the light emitting cells in the subfield.
A write operation period or address period AD for selecting non-light emission and a sustain operation period or sustain period S for executing discharge / non-discharge a predetermined number of times according to the state selected in the immediately preceding address period AD. Has been split.
At this time, the sustain periods S of the subfields SF1 to SF8 are ranked for each of the subfields SF1 to SF8. For example, the time of the sustain period S in the subfield SF2 is the time of the sustain period S in the subfield SF1. Is set almost twice as large as That is, the duration of the sustain period S of the subfield SF (k + 1) is set to almost twice that of the subfield SFk (k: 1).
~ 7).

In the light emitting cells or discharge cells selected in the address period AD of each subfield, the sustain pulses applied during the sustain period S generate the same number of sustain discharges as the number of the sustain pulses. Visible light emission generated by the sustain discharge becomes display light emission of the light emitting cell. As described above, since the number of the sustain pulses is set to be substantially proportional to the time of the sustain period S of each of the subfields SF1 to SF8, the light emission luminance of the light emitting cell selected by the address operation in the address period AD. Almost doubles as the subfield number advances by one. Accordingly, lighting / lighting during the sustain period S in each subfield is performed.
By controlling the combination of non-lighting (ON state / OFF state of the light emitting cell), two light emitting cells can be controlled in one light emitting cell.
⁸ = 256 levels of light emission luminance, that is, display light emission of 256 gradations can be obtained.

Next, a more specific driving method in one subfield will be described with reference to the respective timing charts of FIGS. Here, the conventional AC shown in FIG.
The case where the type PDP 51P is used will be described. 2 and 3
(A) shows the address electrodes Am (1) corresponding to the predetermined address electrodes 6P of the M lines in FIG.
≦ m ≦ M), wherein (b) shows S sustain electrodes X connected in common and applied with a single voltage
5 is a timing chart of 1 to Xs (collectively referred to as “sustain electrodes X”), wherein (c) to (e) are timings of predetermined scanning electrodes Yn (1 ≦ n ≦ S) of S lines It is a chart. Each of the subfields shown in FIGS. 2 and 3 has an erasing period RA or an erasing period RB, respectively.

As shown in FIG. 2, in the erasing period RA, at the beginning of the synchronizing period RA, a priming discharge is applied at the rising of the pulse by applying a full write pulse or a priming pulse (voltage Vp) to the sustain electrode X. Wake up. Further, an erasing operation is performed by causing a self-erasing discharge when the pulse Vp falls. afterwards,
By alternately applying a charge reversal pulse (voltage Vs) to the sustain electrode X and the scan electrodes Y1 to YS, a discharge is generated in a discharge cell having wall charges still remaining even after the application of the entire address pulse, Uniform wall charge. Subsequently, a narrow erase pulse (pulse width 0.2 to 1.5 μs
c) is applied to the sustain electrode X to completely erase the wall charges on the electrodes Xn and Yn. Subsequently, by applying a negative address charge erasing pulse whose voltage value gradually changes to the scan electrodes Y1 to YS, extra wall charges existing on the address electrode Am and the scan electrodes Y1 to YS are erased. I do.

On the other hand, as shown in FIG. 3, in the erasing period RB, at the beginning of the synchronous period RB, the above-described narrow erasing pulse is applied to the sustain electrode X to erase (part of) the wall charges. Then, similarly to the erasing period RA, a charge inversion pulse (voltage Vs) is alternately applied to the sustain electrode X and the scan electrodes Y1 to YS to equalize the amount of wall charges. Subsequently, a narrow erase pulse is applied to completely erase the wall charges. Then,
Similarly to the erase period RA, the above-described address charge erase pulse is applied.

In each address period AD of FIGS. 2 and 3,
A voltage (-Vy) is sequentially applied to the scanning electrodes Yn (scanning is performed), and in synchronization with the selection scanning of the scanning electrodes Yn, an n-th scanning line SLn including an electrode pair Xn and Yn is synchronized.
(See FIG. 11).
That is, in synchronization with the application of the voltage (-Vy), a voltage Von / voltage Voff based on the ON state / OFF state of the image data is applied to the address electrode Am. Further, a predetermined voltage Vx is applied to sustain electrode X. Address electrode A
Address discharge occurs in the discharge cells to which the voltage Von is applied to m, and the image data is written (as wall charges) in the light emitting cells. On the other hand, the voltage Vo is applied to the address electrode Am.
The address discharge does not occur in the light emitting cell to which ff is applied.

In the subsequent sustain period S, an AC sustain pulse or a sustain voltage Vs is applied between the sustain electrode Xn and the scan electrode Yn. At this time, in the discharge cells in which the address discharge has occurred in the address period AD,
Sustain discharge occurs according to the timing when the above-mentioned sustain pulse Vs is applied.

Here, referring to FIGS. 4 and 5, a description will be given of a mechanism of generating the address discharge in the address period AD. When a voltage Vx and a voltage (−Vy) are applied to each of the electrodes Xn and Yn, an upper discharge space 51SP between the electrode pair Xn and Yn is applied.
Generates an electric field. However, with such an electric field alone, the electrode pair X
It does not have the electric field strength necessary to generate a surface discharge between n and Yn. In such a state, the address electrode Am
Is applied with a voltage Von based on image data in the ON state, a strong electric field is generated between the address electrode Am and the scanning electrode Yn, and as shown in FIG. An opposite discharge DC1 is generated. Then, the charged particles generated by the counter discharge DC1 serve as a trigger to generate a (writing) surface discharge DC2 between the electrode pair Xn and Yn, as shown in FIG.

The negative or positive charged particles generated by the surface discharge DC2 are attracted to the electrodes Xn and Yn having polarities opposite to the polarities of the particles, respectively. It is stored as wall charges on the surface 4SP. At this time, the electric field formed in the discharge space 51SP by the wall charges is gradually attracted to the surface 4SP because the voltage applied between the pair of electrodes Xn and Yn acts in a direction to cancel the electric field formed in the discharge space 51SP. The amount of charged particles used is reduced. When the accumulated amount of wall charges reaches a certain amount, the address discharge surface discharge DC between the pair of electrodes Xn and Yn.
2 ends. At this time, even after the voltage supply to the electrodes Xn and Yn is stopped, the wall charges accumulated on the surface 4SP of the cathode film 4P remain without being eliminated. Such wall charges are generated in the sustain period S following the address period AD.
It plays a role of applying an electric field necessary for generating a sustain discharge (surface discharge) between the electrode pair Xn and Yn to the discharge space 51SP. By the action of the wall charges, the discharge cells to which the voltage Von is applied emit light during the sustain period S.

On the other hand, in the discharge cell in which the voltage Voff based on the image data signal in the OFF state is applied to the address electrode Am in the address period AD, the address electrode Am
A sufficient electric field for generating the write facing discharge DC1 is not generated between the pixel and Yn. For this reason, the address facing discharge DC1 between the address electrode Am and the scanning electrode Yn does not occur, and therefore, the writing surface discharge DC2 between the electrode pair Xn and Yn does not occur.
Also does not occur. As a result, the discharge cell to which the voltage Voff is applied shifts to the sustain period S while the above-described wall charges are not formed, so that no sustain discharge occurs in the sustain period S. That is, the discharge cell does not emit light.

In the sustain period S, a positive voltage Va is supplied to all the address electrodes Am as shown in FIG. 2A and FIG. 3A. As described above, in the address period AD, wall charges are formed on the surface 4SP of the cathode film 4P. At this time, the overglaze layer 10P and the phosphor layer 8P are also slightly negatively charged. Therefore, the overglaze layer 1 of the phosphor layer 8P is caused by the applied voltage Va.
The potential of the space near the portion in contact with 0P is determined by the internal gap G
Is controlled to the same level as the average potential (approximately voltage (Vs / 2) + (potential exerted by positive and negative charges on the surface 4SP of the cathode film 4P)) in the space above the central axis of the above. By supplying the voltage Va to the address electrode Am, even when the voltage Vs is applied to any of the electrodes Xn and Yn, the electric field intensity distribution having spatial symmetry with respect to the center axis of the internal gap G is obtained. It can be generated in the discharge space near G. As a result, according to the driving methods shown in FIGS. 2 and 3, the voltage for starting the discharge applied between the pair of electrodes Xn and Yn can be reduced, and the efficiency of the sustain discharge can be improved. The voltage Va is applied to the electrodes Xn,
It is set so that the discharge intensity per sustain discharge (surface discharge) between Yn is maximized.

The control of the electric field distribution will be described by taking as an example a case where the voltage Vs of the sustain pulse in the sustain period S in FIGS. 2 and 3 is about 180 V. At this time, if the sustain pulse Vs is applied to the sustain electrode Xn or the scan electrode Yn, and if there is no address electrode Am (and no voltage applied to the same electrode Am) and no wall charge, a voltage between the electrodes Xn and Yn is not applied. The potential on the central axis of the internal gap G is 180 V / 2 = 90 V
Becomes Therefore, if there is no wall charge in the discharge cell, the voltage to be applied to the address electrode Am is 90V. However, as a result of the address discharge DC1 generated between the address electrode Am and the scan electrode Yn in the address period AD, the overglaze layer 10P or the phosphor layer 8P is charged. Therefore, in order to cancel the potential difference Vw of the average potential of the surface 4SP of the cathode film 4P with respect to the potential of the overglaze layer 10P or the phosphor layer 8P due to such charging, the voltage Va applied to the address electrode Am in the sustain period S is The voltage value is set to about 100 V, which is about 10 V higher than the voltage value 90 V (the voltage Vw is a voltage in a range of about −10 V to 30 V). With this voltage setting, spatial symmetry can be imparted to the electric field distribution in the discharge cells during the sustain period S.

An embodiment of the present invention will be described below.

(Embodiment 1) First, an overall configuration of a driving method of an AC plasma display panel (AC PDP) according to Embodiment 1 will be described with reference to FIG. FIG. 6 is a diagram for explaining a subfield division mode of one screen and each period in each subfield in the present driving method. Here, this driving method is applicable to the AC PDP 51P shown in FIG.
The description of the structure of the DP will be limited to the description of the AC PDP 51P. At this time, the structure on the rear panel 51RP side including at least the address electrodes 6P and the rear glass substrate 9P is regarded as a “first substrate”, and at least the front glass substrate 5P, the sustain electrodes Xn, the scan electrodes Yn, and the dielectric layer (dielectric layer) are formed. If the structure on the front panel 51FP side composed of the layer 3P or the same layer 3P and the cathode film 4P) is regarded as a "second substrate", the first substrate and the second substrate are arranged via the discharge space 51SP. I can say.

An AC type PDP to which the present driving method is applied
May be an AC PDP having a structure not having the overglaze layer 10P with respect to the AC PDP 51P of FIG. Further, since the scanning lines are generally composed of an even number, such a case will be described.

In particular, in the present driving method, 2N scanning lines S
The display area of the AC type PDP on which L1 to SL2N are arranged is a first to Nth scanning lines SL1 to SLN.
The AC type PDP is driven after being divided into a block BL1 and a second block BL2 including (N + 1) th to (2N) th scanning lines SLN + 1 to SL2N.

At this time, as shown in FIG. 6, the display time for one screen in the first and second blocks BL1 and BL2 is divided into eight subfields SF1 to SF8. Further, each of the subfields SF1 to SF8 includes
(I) an erasing operation period or erasing period R0 for erasing the display history of the immediately preceding subfield, and (ii) information based on the input image data in each discharge cell, that is, the sustain discharge in the subsequent sustain period S0. A write operation period or address period AD0 for giving information as to whether or not to generate as wall charges, and (iii) generating a sustain discharge for carrying out display light emission in a discharge cell in which the information has been written, thereby providing a PDP. It is divided into a sustain operation period or a sustain period S0 for displaying an image or an image, and a freeze period F described in detail later (iv). At this time, similar to the driving method according to the base technology, the subfield SF1
To SF8 are stored in each subfield SF1.
ＳＦSF8. Using FIG.
A driving method in each of the subfields SF1 to SF8 will be described.

(Driving Method in Subfield SF1) First, the erasing operation in the erasing period R0 of the subfield SF1 and the writing operation or the address scanning in the address period AD0 are performed on the first block BL1 (discharge cells belonging to). Execute sequentially. At this time, in the erasing period R0 and the address period AD0, the erasing operation in the erasing period RA or RB (see FIGS. 1 to 3) and the address period AD (see FIGS. 1 to 3) in the driving method according to the base technology, respectively. Is performed.

Then, from the end of the address period AD0 of the first block BL1, the erasing period R0 of the subfield SF1 starts for (the discharge cells belonging to) the second block BL2. On the other hand, during the erasing period R0 of the second block BL2, a freezing period F is provided for the first block BL1 in which none of the erasing operation, the writing operation, and the sustaining operation is performed. As described above, in the present driving method, when one of the first and second blocks BL1 and BL2 is in the erasing period R0, the freezing period F is set for the other block BL2 or BL1 (setting). Condition (a)).

The freezing period F is provided for the following reason. That is, in the present driving method, the display area is divided into the first and second blocks BL1 and N1, each having N scanning lines.
After division into BL2, a predetermined driving method is applied to both blocks BL1 and BL2. At this time, each block B
The voltages applied to the scanning lines belonging to L1 and BL2 (that is, the scanning electrodes Xn and the sustain electrodes Yn) are controlled in block units. On the other hand, since the (plural) address electrodes Am are shared (not divided) by both blocks BL1 and BL2, the voltage applied to the address electrodes Am is independently applied to each of the blocks BL1 and BL2. Can't control. Therefore, in the present driving method, since a predetermined voltage for one block BL1 or BL2 is applied to the address electrode Am, any one of the erasing operation, the writing operation, and the sustaining operation is applied to the other block BL2 or BL1. In some cases, the operation cannot be performed. Therefore, in the present driving method, in such a case, the other block BL
A freezing period F is set for 2 or BL1. Specifically, the freeze period F is defined as a case where one block is in the erase period, a role of the other block as a suspension period of a predetermined period, and a case where an address period is in progress in one block described later. And has a role as a waiting period of the other block until the end of the synchronization period.

Subfield S in second block BL2
From the end of the erase period R0 of F1, the second block B
In L2, the address period AD0 of the subfield SF1 starts, and in the first block BL1, the sustain period S0
, The sustain discharge is started.

In particular, in this driving method, one of the first and second blocks BL1 and BL2 is in the address period AD0 and the other block BL1 or BL2 is in the sustain period S0. The “sustain period S1” is set as the sustain period S0 in the other block (setting condition (b)). Specifically, the duration of the sustain period in a predetermined subfield is constant in all subfields SF1 to SF8 without distinction of both blocks since the same number of scanning lines belong to the first and second blocks BL1 and BL2. Is shorter than the address period AD0, the sustain period S0 is equal to the sustain period S0.
It is composed of only one. For example, since the subfield SF1 has the lowest ranking among all the subfields SF1 to SF8, that is, has the shortest sustain period (supposed to be shorter than the address period AD0 of the subfield SF1). As shown in FIG.
The sustain period S1 is set as the sustain period S0 of the subfield SF1 in L1. The detailed driving method in the sustain period S1 will be described later. Embodiment 1
Now, each of the sustain periods S0 of the subfields SF1 to SF5
Is composed of a sustain period S1 and includes subfields SF6 to SF6.
Each of the sustain periods S0 of F8 will be described as being composed of two sustain periods S1 and a later-described sustain period S2, and FIG. 6 illustrates such an embodiment.

Now, as shown in FIG. 6, the first block B
Even when the sustain period S0 of the subfield SF1 in L1 ends, the second block BL2 is in the address period AD0 of the subfield SF1. At this time,
Until the address period AD0 in the second block BL2 ends, the freeze period F is set for the first block BL1 (the role of the freeze period F described above).

Then, from the end of the address period AD0 in the second block BL2, in the first block BL1, the subsequent erasing period R0 of the subfield SF2 is performed.
To start. At this time, in the second block BL2, the first block
The freeze period F is set until the end of the erasing period R0 in the block BL1, and the sustain period S0 of the subfield SF1 starts from the end of the erasing period R0. During the period from the end of the sustain period S0 in the second block BL2 to the end of the address period AD0 of the subfield SF2 in the first block BL1, a freeze period F is set for the second block BL2.

Thereafter, when the address period AD0 of the subfield SF2 in the first block BL1 ends,
In the second block BL2, the erasing period R0 of the subfield SF2 is started. During the erase period R0 in the second block BL2, a freeze period F is set for the first block BL1.

By the above-described driving method, the driving for the first and second blocks BL1 and BL2 (the discharge cells belonging to them), that is, the subfield SF1 for the entire display area is performed.
Is completed.

(Driving method in subfields SF2 to SF5) In subfields SF2 to SF5 subsequent to subfield SF1, driving is performed in the same manner as in subfield SF1. That is, as shown in FIG. 6, each period is set based on the setting conditions (a) and (b) described above.

(Driving Method in Subfields SF6 to SF8) As described above, in the driving method according to the first embodiment, the sustain period S0 of each of subfields SF6 to SF8 is equal to that of each of subfields SF6 to SF8. It is set longer than the address period AD0. Therefore, in each of the sustain periods S0 of the subfields SF6 to SF8, a driving method based on the further setting condition (c) is applied in addition to the driving method based on the above setting conditions (a) and (b). That is, as in the subfield SF6 of FIG. 6, the “sustain period S2” is set for a period in which both the first and second blocks BL1 and BL2 are in the sustain period S0 (setting condition (c)). Specifically, the time of the sustain period S0 executed in one block BL1 or BL2 is parallel to the time of the other block BL2 or BL1.
Is longer than the time of the address period AD0 executed in the two blocks BL1 and BL1 after the end of the address period AD0 of the other block BL2 or BL1.
The above-mentioned sustain period S2 is set as the sustain period of No. 2.

For example, the sustain period S of the subfield SF6
The driving method at 0 is as follows. As shown in FIG. 6, the subfield SF in the second block BL2
During the erasing period R0 of 6, the freezing period F is set for the first block BL1 based on the setting condition (a) described above. Then, in the second block BL2, simultaneously with the start of the address period AD0, the above-described setting condition (b)
, The sustain period S1 is started in the first block BL1. Here, in the subfield SF6, the time of the sustain period S0 is longer than that of the address period AD0.
Even when the address period AD0 in the second block BL2 ends, the sustain period S0 in the first block BL1 has not ended yet. Therefore, based on the above-described setting condition (c), the first and second blocks BL1 and BL1
The sustain period S2 is set for both L2. In addition,
A detailed driving method in the sustain period S1 will be described later.

Thereafter, in the first block BL1, after the end of the sustain period S0 of the subfield SF6, the erase period R0 and the address period AD0 of the next subfield SF7 are sequentially started. At this time, in the second block BL2,
According to the setting conditions (a) and (b), the respective operations in the freeze period F and the sustain period S1 (as the remaining period of the sustain period S0 in the subfield SF6) are sequentially performed.

As shown in FIG. 6, setting conditions (a),
Based on (b) and (c), subfields SF6 to SF6
Each period R0, AD0, S0, F of SF8 is set.

Next, a more specific driving method will be described with reference to the timing charts of FIGS. 8 to 10 are a series of timing charts,
They are linked by the relationship shown in FIG. A series of timing charts in FIGS. 8 to 10 show a period from one subfield SF8 to a subfield SF1 in a video display time for the next one screen (periods T1 and T1 in FIG. 6).
2). Each of (a), (b-1) and (b-2) to (e-1) and (e-2) in each of FIGS. 8 to 10 is (a) to (e) in FIG. e). That is, (a) in each of FIGS. 8 to 10 is a timing chart of the voltage applied to the address electrode Am (m: 1 to M), and (b-1) to (e-) in each of the drawings. 1)
Are the sustain electrodes X1 belonging to the first block BL1, respectively.
To XN (a voltage is commonly applied to N electrodes), and timing charts of the voltages applied to the scan electrode Y1, the scan electrode Y2, and the scan electrode YN.
(E-2) denote sustain electrodes XN + 1 to X2N (a voltage is commonly applied to N electrodes), scan electrode YN + 1, scan electrode YN + 2, and scan electrode belonging to the second block BL2. It is a timing chart of each voltage applied to the electrode Y2N.
Also, (f-1) and (f-2) in each of FIGS.
, The corresponding subfield in each of the blocks BL1 and BL2 is illustrated. Hereinafter, the present driving method in the combination of the above periods will be described in more detail with reference to the timing charts of FIGS.

(Parallel Drive in Combination of Erase Period and Freeze Period) As shown in FIG. 8, the first block BL1
During the execution of the erasing operation in the erasing period R0 (here, the erasing period RB) of the subfield SF8, the freezing period F is set in the second block BL2. That is,
The address electrodes Am and the sustain electrodes X1 to XN and the scan electrodes Y1 to YN belonging to the first block BL1 have the voltages (a) to (e) in FIG. Apply a pulse. At this time, since the address electrode Am is an electrode common to both the first and second blocks BL1 and BL2, the erasing pulse is also applied to (the discharge cells belonging to) the second block BL2 in the freeze period F. Applied. Therefore, in the present driving method, the sustain electrode XN + 1 belonging to the second block BL2 in the freeze period F is used.
To X2N and all the scanning electrodes YN + 1 to Y2N.
By applying g, no discharge is generated in the discharge cells belonging to the second block BL2. By applying the voltage Vg, the second block B
L2 is a period in the middle of the sustain period S0 of the subfield SF7 (as shown in FIG. 6, the sustain period S2 was immediately before the period T1), and from time t1 to time t2 (freezing period F). The wall charges of the discharge cells can be held as they are during the period. Therefore, in the second block BL2, the continuation of the sustain period S0 in the subfield SF7, that is, the sustain discharge in the sustain period S1 can be reliably started or restarted.

8 to 10, the erase period R
The parallel drive in the combination of 0 (RA or RB) and the freezing period F is performed in addition to the above-described period of time t1 to time t2, as well as time t3 to time t4, time t6 to time t7, and time t.
It is applied to each period from time 8 to time t9 and time t11 to time t12.

(Parallel Drive in Combination of Address Period and Sustain Period) Next, from time t2 to time t3, in the first block BL1, the write operation in the address period AD0 of the subfield SF8 is performed. In the two blocks BL2, the sustain period S0 (= S1)
And the display operation is performed. As an address period ADO in the first block BL1, FIG.
And the address period AD in FIG. 3 is applied. On the other hand, as shown in (b-2) to (e-2) in FIG. 8 (similar to the sustain period S in FIGS. 2 and 3), in the second block BL2 in the sustain period S1, A sustain pulse that changes between the voltage Vg and the voltage Vs0 is applied to the sustain electrodes XN + 1 to X2N and the scan electrodes YN + 1 to Y2N so that the sustain pulse changes between each pair of electrodes. This will be described in detail below.

In the address period AD0, the address electrode A
m is a voltage Von or a voltage Vof based on the input image data.
f is applied. On the other hand, when a sustain discharge is generated in the discharge cell in the sustain period S0, the applied voltage (electric field) of the address electrode Am has a considerable influence on the formation of the electric field in the discharge space, that is, the formation of the sustain discharge. Accordingly, the sustain electrodes XN + 1 to X2N and the scan electrodes YN + 1 of the second block BL2 are provided.
When each voltage in the sustain period S of FIGS. 2 and 3 is applied to .about.Y2N, the discharge intensity of the sustain discharge in the discharge cells belonging to the second block BL2 includes the voltage Von and the voltage Vof.
A variation depending on f (depending on the image data of the first block BL1) occurs. Therefore, the first block BL1 is in the address period AD0 (of the subfield SF8), and the second block BL2 is in the (subfield SF8).
7) (in a case where the voltage Von or the voltage Voff is applied to the address electrode Am) in the sustain period S1 (the same applies to the opposite case such as the period from the time t4 to the time t5). It is necessary to stably generate the sustain discharge in the discharge cells belonging to the second block BL2.

As described above, in the conventional driving method shown in FIGS. 2 and 3, the voltage Va is applied to the address electrode Am in the sustain period S. By applying the voltage Va, the electric field distribution in the discharge cell when the voltage or the sustain pulse Vs is applied to the sustain electrodes X1 to XS and the scan electrodes Y1 to YS changes the internal gap G between the electrodes Xn and Yn (see FIG. 4). (See FIG. 5 and FIG. 5) so as to have spatial symmetry with respect to the central axis (according to such control, a sustain discharge between the electrodes Xn and Yn can be formed most efficiently). As described above, for example, when the voltage Vs is about 180 V, the voltage Va is set to about 100 V.

By applying this driving method, the second
It is considered that the sustain discharge of the discharge cells belonging to the block BL2 can be stabilized. However, when each driving method in the sustain period S and the address period AD according to the base technology is simply applied, for example, the voltage Vs0 = 180
V, voltage Vg = 0 V, voltage Von = 50-100 V (voltage applied to address electrode Am), voltage Voff
= 0 V, in the second block BL2 in the sustain period S1, the applied voltage Va to the address electrode Am is 100V, which is a voltage that can optimize the efficiency of the sustain discharge between the electrodes Xn and Yn. In comparison, when the voltage Von is applied, the voltage is lower by 0 to 50 V, and when the voltage Voff is applied, the voltage is 100 V.
Is also low. At this time, the voltage Vo is higher than the voltage Von.
Since ff has a greater distance from the optimum voltage value of 100 V, the discharge intensity of the sustain discharge between the electrodes Xn and Yn in the sustain period S1 is the same when the voltage Voff is applied to the address electrode Am. This is considerably weaker than when the voltage Von is applied to the electrode Am.

Therefore, while applying the driving method in the sustain period S in the driving method according to the base technology, the voltage control optimized for the parallel driving in the combination of the address period AD0 and the sustain period S1 in the present driving method. Will be described.

For example, at the time of the parallel driving, the address electrodes Am
To the voltage value 前提 (Vs0
+ Vg) / 2, the symmetry of the electric field distribution at the time of the sustain discharge between the electrodes Xn and Yn is realized, and the sustain discharge can be stabilized and the efficiency can be improved. As described above, the voltage Vw is a voltage in a range of approximately −10 V to 30 V. Here, it is assumed that Vw = about 10 V. However, in the present parallel driving, since the first block BL1 is in the address period AD0, the voltage applied to the address electrode Am takes two values, the voltage Von and the voltage Voff. Therefore, it is very difficult to form a sustain discharge with optimum efficiency, regardless of whether the voltage Von or the voltage Voff is applied to the address electrode Am.

Therefore, in the present driving method, the efficiency is the same both when the voltage Von is applied to the address electrode Am and when the voltage Voff is applied, that is, whether the voltage Von or the voltage Voff is applied. Is applied so that the spatial symmetry of the electric field distribution with respect to the center axis of the internal gap G between the electrodes Xn and Yn (see FIGS. 4 and 5) is equalized even when the voltage is applied. Control the electric field distribution in the cell. The control of the electric field distribution is performed by controlling each of the voltage Von and the voltage Voff and the voltage ｛(Vs0
+ Vg) / 2 + 10 ° V so that the voltages Von, Voff, Vs0, V
This is realized by setting g. In other words, the voltages Von, Voff, and Vs satisfy the relationship of (Von + Voff) / 2 = (Vs0 + Vg) / 2 + Vw (1)
When 0 and Vg are set, the gap between each of the voltages Von and Voff and the above-mentioned optimal voltage value on the discharge efficiency is maintained regardless of whether the voltage Von or the voltage Voff is applied to the address electrode Am. Voltage ｛(Von-Vof
f) / 2}, the voltages Von, Vo
Regardless of which ff is applied, the electric field distribution in the discharge cell can be made symmetrical to each other. Therefore, the address electrode A
m regardless of the applied voltage Von, Voff to the electrode X
The discharge intensity of the sustain discharge between n and Yn can be made equal. As a result, the image display based on the image data in the block performing the sustain discharge is performed in the address period AD0.
Is not interfered with by the image data for the block located at. That is, an optimal display image can be obtained.

At this time, a margin can be given to each of the voltages Von, Voff, Vs0 and the voltage Vg depending on the extent to which the interference of the image data between the blocks is allowed. Hereinafter, such a condition of the driving voltage will be described.

As described above, the sustain period S according to the base technology is
For example, the voltage Vs0 = 180V and the voltage Vg = 0V simply corresponding to each driving method in the address period AD.
And a voltage Vo (which is a voltage applied to the address electrode Am)
When the voltage is set such that n = 50 to 100 V and the voltage Voff = 0 V, the magnitude relationship Voff <Von <{(Vs0 + Vg) / 2 + Vw} (2) holds. At this time, the voltage ｛(Vs0 +
Vg) / 2 + Vw} and the difference between the voltage Von and the voltage Voff is equal to the voltage difference between the two voltages Von and Voff. That is, for the voltage {(Vs0 + Vg) / 2 + Vw}, the voltage Von and the voltage Voff do not exist at the same distance. For this reason, the discharge intensity of the sustain discharge between the electrodes Xn and Yn greatly differs between when the voltage Von is applied and when the voltage Voff is applied. Therefore, the voltages Von, Voff are set so as to satisfy the magnitude relation of Voff <{(Vs0 + Vg) / 2 + Vw} <Von.
By setting f, Vs0, and Vg, the voltage ｛(V
s0 + Vg) / 2 + Vw} and the voltage Von or the voltage Vof
The difference of each distance from f can be reduced as compared with the above case. As a result, the interference based on the image data generated between the block performing the sustain discharge and the block in the address period AD0 is compared with the driving method in which the set voltage in the driving method according to the base technology is simply applied. Can be sufficiently suppressed.

At this time, if the voltage Von is set higher, for example, the voltage (Von-Vg) increases,
In the block in the sustain period S0 (the other block is in the address period AD0), the electrode Xn or Yn to which the voltage Vg for the sustain discharge is applied and the address to which the voltage Von for the address discharge is applied. A counter discharge may occur between the electrode and the electrode Am. When (part of) the wall charges on the surface of the cathode film 4P (see FIG. 11) disappear due to the counter discharge, a subsequent sustain discharge may not be able to be continued. Therefore, the above-described voltage setting is performed so as not to cause such a situation.

8 to 10, the parallel drive in the combination of the address period AD0 and the sustain period S1 is performed at the time t2 in addition to the period from the time t2 to the time t3.
4 to time t5, time t7 to time t8, time t9 to time t
10 and each period from time t12 to time t13.

(Driving During Sustain Period S2) Time t5
In the sustain period S2 at time t6, the first and second blocks B
Since both L1 and BL2 are in the maintenance period, both blocks B
Both L1 and BL2 can be driven in common or similarly. Therefore, it is considered that the driving method according to the base technology in the case where the display area is not divided can be applied as the driving method in the sustain period S2. At this time,
When applying the driving method according to the base technology as it is,
A steady voltage Va (see FIGS. 2 and 3) set so as to optimize the efficiency of the sustain discharge between the electrodes Xn and Yn is applied to the address electrode Am. However, the aforementioned maintenance period S
In view of the fact that the sustain discharge between the electrodes Xn and Yn in No. 1 is not performed at the optimum efficiency, the driving method in the sustain period S2 is executed with the voltage Va for optimizing the sustain discharge efficiency. Sometimes sustain pulse 1
The intensity of the sustain discharge per cycle differs between the sustain period S1 and the sustain period S2. In such a case, the subfields SF1 to SF5 in which the sustain period S0 includes only the sustain period S1, and the subfields SF6 to SF8 in which the sustain period S1 includes both the sustain period S1 and the sustain period S2.
In some cases, the intensity ratio of image display varies from a predetermined value.

In order to avoid such a situation, according to the present driving method, as shown in FIG.
From time 5 to time t6, the voltage value Voff is set as the applied voltage Va0 to the address electrode Am. By setting the voltage Va0, the electrode X per one sustain pulse is set.
The intensity of the sustain discharge between n and Yn can be the same between the sustain period S1 and the sustain period S2. At this time, it is clear that the voltage value Von may be set as the voltage Va0.

Further, as another driving method in the sustain period S2, by controlling the number of the sustain pulses in the sustain period S1 or the sustain period S2 for each subfield, the display intensity ratio between the above-described subfields is determined. A method of adjusting to the value is applicable.

(Parallel Drive in Combination of Address Period and Freeze Period) Time t10 to time t in FIG.
11, and in each period from time t13 to time t14, the operations in the address period AD0 and the freeze period F are performed in parallel. At this time, the voltage Vg is applied to all the sustain electrodes and all the scan electrodes belonging to the block in the freezing period F in each of the above periods, similarly to the parallel driving in the combination of the erasing period R0 and the freezing period F described above. Thus, a block in the frozen period F can hold a state immediately before the period F until the end of the period F, and a block in the address period AD0 can execute a write operation.

In the driving method according to the prerequisite technique (or the conventional driving method), the sustain operation is executed after the writing scan for all the scanning lines is completed in each subfield. On the other hand, according to the driving method according to the first embodiment, as soon as the writing scan on the N scanning lines belonging to each block is completed in a block unit, or immediately or for a short period (equal to the time of the erase period). Immediately after the freezing period F), the maintenance period S0 is started. In other words, as shown in FIGS. 8 to 10, when one block is in the address period AD0, the sustain period S0 is set in parallel with the other block. For this reason,
Compared with the case where the driving method according to the base technology (or the conventional driving method) is applied to a PDP having a predetermined number of scanning lines, the video display time for one screen can be effectively used. That is, there is a time margin in the video display time for one screen. Therefore, when such a time margin is used for increasing the number of subfields, it is possible to realize a high gradation of video display. On the other hand, when the time margin is used for increasing the time of the address period of each subfield, the address operation can be performed on more discharge cells. That is, higher definition of the AC type PDP can be achieved.

In other words, even if the time required for the address period in the video display time for one screen is increased with the increase in definition or the gradation, the sustain period itself or the sustain pulse in the sustain period is increased. , The number of sustain pulses can be kept equivalent to that of the driving method according to the base technology (or the conventional driving method). As a result, high definition or high gradation A
Unlike the case where the driving method according to the prerequisite technology (or the conventional driving method) is applied to a C-type PDP as it is, a decrease in luminance and instability of sustain discharge due to higher definition and higher gradation are caused. Without AC type PDP or AC type
The excellent image display performance of the plasma display device having the type PDP can be reliably exhibited.

In the above embodiment, the case where the display area or the plurality of scanning lines are divided into upper and lower blocks and driven is described for the sake of convenience of explanation. However, application of the driving method according to the present invention is not limited to such an embodiment. For example, the scanning line may be divided into even rows and odd rows. Further, the present driving method is also applicable to an AC type PDP compatible with a so-called “upper / lower block parallel addressing method” having all address electrodes Am divided into two blocks in an upper half and a lower half of a display area. . At this time, each of the upper half and the lower half of the display area corresponds to the entire display area in the above description of the driving method.

Further, the division of the display area or the scanning line is not limited to two blocks. That is, the above-described effect can be obtained by dividing the display area or the scanning line into a plurality of blocks and performing the writing operation in one block and performing the maintaining operation in the other blocks.

[0076]

According to the first aspect of the present invention, the writing operation and the maintaining operation are performed in parallel between a plurality of blocks, so that the video display time for one screen is effectively used. Can be. For this reason, compared with the conventional AC plasma display panel driving method in which the entire screen is driven without being divided into blocks, there is a time margin in the video display time for one screen. When such a time margin is used for increasing the time of the address period of each subfield, the address operation can be performed on the discharge cells of the AC type plasma display panel having more discharge cells. That is, high definition of the AC type plasma display panel can be promoted. On the other hand, when the time margin is used for increasing the number of subfields, it is possible to realize a high gradation of video display.

In other words, even if the total time of the address period in the video display time for one screen increases as the definition and gradation of the AC type plasma display panel increase, the sustain period is reduced. There is no need to reduce time quotas. For this reason, inconvenience of video display caused by the reduction of the sustain period, for example, a decrease in luminance caused by a decrease in the number of sustain pulses for the sustain discharge and a sustain pulse for securing the number of sustain discharges Does not cause the instability of the sustain discharge caused by shortening the cycle of.

(2) According to the second aspect of the present invention, even when either the voltage Von or the voltage Voff is applied to the address electrode, the sustain discharge of the discharge cells belonging to the block in the sustain period is performed. Can be controlled to the same extent. For this reason, it is possible to sufficiently suppress the video display of the block in the sustain period from being affected by (the voltage Von or the voltage Voff based on) the image data corresponding to the block in the address period. Therefore, a practically sufficient level of image display can be realized.

In particular, the voltage Δ (Vs0 + Vg) / 2 + V
w} is an intermediate voltage between the voltage Von and the voltage Voff (Vo
(n + Voff) / 2} when setting each voltage, the voltage Von or the voltage Voff is applied to the address electrode.
No matter which voltage is applied, the discharge intensity of the sustain discharge of the discharge cells belonging to the block in the sustain period can be equalized, so that more excellent display quality can be realized.

(3) According to the third aspect of the present invention, at least one or more blocks are in the sustain period, and none of the blocks belongs to the block in the sustain period in a period not in the address period. 1 in the discharge cell
The discharge intensity of the sustain discharge can be made substantially the same as the discharge intensity of the sustain discharge (see claim 1) during the period in which the address operation and the sustain operation are performed in parallel between a plurality of blocks. Therefore, the same brightness can be obtained regardless of which sustain discharge is used. That is,
The display intensity ratio or the luminance ratio between each subfield can be maintained at a predetermined value.

(4) According to the fourth aspect of the present invention, the AC plasma display panel having high definition and high gradation is provided by exhibiting any of the effects (1) to (3). A plasma display device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a subfield division mode of one screen and each period in each subfield in a driving method of an AC type PDP as a base technology of the present invention.

FIG. 2 is a timing chart showing a waveform of a voltage applied to each electrode in a subfield in a method of driving an AC PDP as a base technology of the present invention.

FIG. 3 is a timing chart showing a voltage waveform applied to each electrode in a subfield in another driving method of an AC-type PDP as a base technology of the present invention.

FIG. 4 is a diagram for explaining a form of a counter discharge between a scanning electrode and an address electrode.

FIG. 5 is a diagram for explaining a form of surface discharge between an electrode pair.

FIG. 6 is a diagram for explaining a subfield division mode of one screen and each period in each subfield in the method of driving an AC PDP according to the first embodiment.

FIG. 7 is a diagram showing a relationship between the timing charts shown in FIGS. 8 to 10;

FIG. 8 is a timing chart showing a voltage waveform applied to each electrode in a subfield in the method of driving an AC PDP according to the first embodiment.

FIG. 9 is a timing chart showing a voltage waveform applied to each electrode in a subfield in the method of driving the AC PDP according to the first embodiment.

FIG. 10 is a timing chart showing a voltage waveform applied to each electrode in a subfield in the method of driving an AC PDP according to the first embodiment.

FIG. 11 is an exploded perspective view schematically showing a structure of an AC type PDP according to the related art.

[Explanation of symbols]

1P transparent electrode, 2P bus electrode, 3P dielectric (layer), 4P cathode film, 5P front glass substrate, 6
P, Am address electrode, 7P barrier rib, 8P phosphor (layer), 9P back glass substrate, 10P overglaze layer, 51SP discharge space, AD, AD0 address period, BL1, BL2 block, F freezing period, R
0, RA, RB erase period, S, S0, S1, S2 sustain period, SF1 to SF8 subfield, Xn sustain electrode, Yn scan electrode, Va, Va0, Vg, Von,
Voff, Vs, Vs0, Vx, Vy, Vw voltage.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 623 G09G 3/20 623U 641 641E

Claims (4)

[Claims] A first substrate having a plurality of strip-shaped address electrodes arranged at least in parallel with each other; a strip-shaped sustain electrode arranged at least in a direction intersecting with the address electrodes to form a scanning line; A second substrate having a plurality of pairs of scan electrodes and a dielectric layer covering the pair of electrodes is disposed via a discharge space filled with a discharge gas, and the plurality of address electrodes and A method for driving an AC plasma display panel, comprising a display area in which a plurality of discharge cells formed at each three-dimensional intersection with the plurality of scanning lines are arranged in a matrix, comprising: After dividing time into a plurality of subfields, each of the plurality of subfields is imaged at least in a predetermined discharge cell among the plurality of discharge cells. Address period for executing an address operation for generating an address discharge based on data, and a sustain period for executing a sustain operation for generating a predetermined number of sustain discharges in the predetermined discharge cell in which the address discharge has occurred. When the display area is divided into blocks by dividing the plurality of scanning lines into a plurality of blocks, a predetermined time is selected from among the plurality of blocks during the video display time of one screen. A method for driving an AC-type plasma display panel, wherein the address operation for a discharge cell belonging to one block and the sustaining operation for a discharge cell belonging to a block other than the predetermined one block are performed in parallel. . 2. The method of driving an AC plasma display panel according to claim 1, wherein a voltage applied to the address electrode during the address period, wherein a voltage based on an ON state of the image data is represented by a symbol. Von, a voltage based on the OFF state of the image data is represented by a symbol Voff, and a voltage applied to one of the sustain electrode and the scan electrode in the sustain period is represented by a symbol Vs0. The voltage applied to the sustain electrode and the other of the sustain electrodes at that timing is represented by a symbol V
g, the potential difference between the surface of the first substrate on the side of the discharge space and the potential of the surface of the second substrate on the side of the discharge space, which is caused by the charge accumulated in the discharge cells through the address discharge. A driving method for an AC-type plasma display panel, wherein each voltage satisfies a relationship given by Voff <{(Vs0 + Vg) / 2 + Vw} <Von. 3. The method of driving an AC plasma display panel according to claim 2, wherein at least one of the blocks is in the sustain period during the video display time for one screen, and Each of the blocks further includes a period that is not included in the address period. In the period, the voltage Von is applied to the address electrode.
And driving the AC plasma display panel by applying one of the voltage Voff and the voltage Voff. 4. A plasma display device driven by the method for driving an AC plasma display panel according to claim 1.