JP2000138369A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a method of manufacturing an FET which does not employ an LDD structure, which eliminates the occurrence of asymmetry in the channel of the FET and which can easily apply a salicide technique. SOLUTION: After forming a gate electrode (3), an insulating film (1) is formed.
2) depositing and forming sidewalls (15, 16) made of the insulating film on the side surfaces of the gate electrode (3) by anisotropic etching. ), An insulating film (12) is deposited, and then the side walls (15, 1) are formed.
Anisotropic etching is performed by tilting the substrate (1) at the same angle as the ion implantation angle of the source / drain regions (5, 6) so that the source / drain regions (5, 6) become asymmetrical in the left and right directions. A thick sidewall is formed on the side of the ion implantation direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a field effect transistor which does not employ an LDD structure.

[0002]

2. Description of the Related Art Generally, a field effect transistor (Fie) is used.
ld Effect Transistor: FE
T) reduces the electric field at the drain and relaxes hot carriers, so that an LDD structure (Lightly Do
ped Drain). Here, a method of manufacturing a pMOS FET employing a conventional LDD structure will be described with reference to FIG.

First, a gate insulating film 2 is formed on an N-type Si substrate 1.
(Eg, silicon dioxide film SiO ₂ ) and gate electrode 3
(For example, Poly-Si), and a gate electrode having a predetermined length is formed by photolithography and etching (FIG. 2).
(See (a)). Next, a P− layer (LDD region) 9 is formed by implanting boron ions into the substrate 1.
(B)).

Next, after depositing an insulating film (for example, a silicon dioxide film SiO ₂ ) on the substrate 1, anisotropic etching is performed.
Sidewalls made of the insulating film 4 are formed on both sides of the gate electrode 3 (see FIG. 2C). Next, source / drain regions 5 are implanted by implanting high-concentration boron ions.
6 (see FIG. 2D).

As described above, the pMO adopting the LDD structure
An S FET is formed.

However, as the operation speed, power consumption, and power supply voltage of FETs increase, the drain electric field of FETs tends to decrease. In addition, the deterioration of FET characteristics due to hot carriers tends to be reduced. Thus, it is not always necessary to adopt the LDD structure for the low power supply voltage FET. Further, in order to form an LDD structure, in the case of CMOS, the other FET is used.
Must be masked with a resist, a photolithography process,
Since an ion implantation step, a resist removal step, and a cleaning step are required, the LDD structure is not adopted in the low power supply voltage FET even in reducing the manufacturing cost.

However, the following problems have arisen in FETs that do not employ the LDD structure.

In an FET that does not employ the LDD structure (see FIG. 3), the channel length is determined by the source and drain regions 5 and 6 because there is no LDD region. Source,
The ion implantation of the drain regions 5 and 6 is performed at a certain angle with respect to the main axis of the substrate 1 in order to prevent a channeling phenomenon. The channeling phenomenon is that the implanted ions reach deep into the substrate with little scattering by atomic nuclei or electrons depending on the crystal direction.

However, when the source and drain ions are implanted at an angle, the source and drain regions 5 and 6 are formed asymmetrically with respect to the gate electrode 3 as shown in FIG. 3 may not be able to cover the channel region, causing an offset and increasing the channel resistance.

In the LDD structure shown in FIG. 2D, the high-concentration regions of the source and drain regions 5 and 6 are offset, but the ion implantation is performed in a state where the LDD region 9 has no side wool 4. , P− and P + are activated twice, so that the end of LDD region 9 becomes gate electrode 3.
There was no problem because I went under.

In order to avoid this, for example, Japanese Patent Laid-Open No.
According to Japanese Patent No. 6165, as shown in FIG. 4, even if the source and drain regions 5 and 6 are formed asymmetrically, the gate electrode is substantially formed by forming the sidewalls 10 with a conductive film instead of an insulator. The width of 3 is increased to prevent offset.

As shown in FIG. 5, after the gate electrode 3 is formed, an insulating film 12 is formed on the entire surface (see FIG. 5A), and phosphorus ions are implanted at a predetermined angle (see FIG. 5A). As shown in FIG. 5B, asymmetric sidewalls 13 and 14 are formed by performing anisotropic etching. This is based on the relationship between the phosphorus concentration and the etching speed. In the case of the drawing, the insulating film on the right side of the gate electrode 3 having a high phosphorus concentration is rapidly etched. After the formation of the asymmetric side walls 13 and 14, ion implantation is performed at a fixed angle from the side of the thick wall 13 to form the source and drain regions 5 and 6. (See FIG. 5D). As a result, in the source / drain regions 5 and 6, the overlapping portion with the film portion is increased on the side of the thick side wall 13 and the overlapping of the film portion on the side wall 14 side of the wall is small, but the overlap of the film portion is small. Overlap is set to the same extent as the larger side to eliminate asymmetry.

[0013]

However, the above-described technique can eliminate asymmetry, but the technique of forming the conductive film 10 on the side wall of the gate electrode 3 in FIG. Since the margin with respect to the position of the gate electrode 3 decreases, it is not suitable for miniaturization. If the side of the gate electrode 3 is not an insulating film, F
Salicide, a technology essential for miniaturization of ET, cannot be applied. That is, in salicide formation, after heat treatment, unreacted titanium on the insulating film is removed by etching.
At this time, the side portion of the gate electrode 3 needs to be an insulating film.

Further, it is difficult to apply the salicide technique even in the technique described with reference to FIG. In FIG. 5, in order to make the etching rate different in the anisotropic etching step, phosphorus is injected obliquely (see FIG. 5B), but the etching rate of the right insulating film 12 containing a large amount of phosphorus is increased. This is because it becomes difficult in terms of controllability to leave the insulating film 12 on the entire side portion of the gate electrode 3.

In view of the above, the present invention provides a method of manufacturing an FET which does not employ an LDD structure, which eliminates the occurrence of asymmetry in the channel of the FET and which can easily employ a salicide technique. Aim.

[0016]

Means for Solving the Problems The invention described in claim 1 is:
A method for manufacturing a semiconductor device, comprising the steps of: depositing an insulating film after forming a gate electrode, and forming sidewalls made of the insulating film on side surfaces of the gate electrode by anisotropic etching; After depositing the source, the source
A method for manufacturing a semiconductor device, characterized in that anisotropic etching is performed by inclining a substrate at the same angle as the ion implantation angle of a drain region to form a thick sidewall on the source and drain regions on the ion implantation direction side.

The invention according to claim 2 is the method according to claim 1, wherein the ion implantation angle is 5 to 15 degrees.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, after the formation of the sidewall, a step of forming a silicide in a gate electrode, a source region, and a drain region is included. It is a manufacturing method of.

The invention according to claim 4 is the method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is a field-effect transistor that does not employ an LDD structure.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIG.

First, a substrate 1 (for example, a Si substrate, SIMO
A gate insulating film 2 (for example, a silicon dioxide film SiO ₂ ) and a gate electrode 3 (for example, Poly-Si) are deposited on an X substrate or an SOI substrate, and a gate electrode having a predetermined length is formed by photolithography and etching. (See FIG. 1A).

Next, after an insulating film 12 (for example, a silicon dioxide film SiO2) is deposited on the substrate 1 (see FIG. 1B),
By performing anisotropic etching, sidewalls made of the insulating film 12 are formed on both sides of the gate electrode 3. At this time, etching is performed by inclining the main axis of the substrate 1 at the same angle as the implantation angle θ in the ion implantation of the source region and the drain region (the angle at which the substrate 1 is perpendicular to the ion implantation direction of the source region and the drain region). (See FIG. 1 (c)). That is, the ion implantation of phosphorus is performed by tilting the substrate 1 by θ as described above, and anisotropic etching using the relationship between the phosphorus concentration and the etching speed is performed, so that the asymmetric sidewalls 15 and 16 are formed. (FIG. 1D). As a result, an asymmetric sidewall in which the side wall 15 of the source region and the drain region on the side of the ion implantation direction is thickened is formed.

Next, in order to form the source and drain regions 5 and 6, high-concentration ion implantation is performed, and heat treatment for activating the implanted ions and diffusing the source and drain ends near the gate electrode 3 is performed. (FIG. 1 (e)). The direction of this ion implantation is, as shown in FIG. 1 (e), at an angle θ in a direction facing the thick side of the sidewall.

Next, titanium 7 is formed and heat treatment is performed to form titanium silicide 8 at the contact portion between titanium and silicon (FIG. 1 (f)). Further, unreacted titanium on the insulating film (on the sidewalls 15 and 16) is removed by etching, and a second heat treatment is performed to obtain a low-resistance silicide 8 (FIG. 1G).

Hereinafter, after depositing an interlayer insulating film, a source,
A contact hole is opened on the drain regions 5 and 6, and an electrode is formed to complete the FET. As a result, an FET whose channel is symmetric with respect to the gate electrode 3 is formed.

The angle at which the anisotropic etching is performed may be 5 to 15 degrees which is usually performed to prevent the channeling phenomenon. If the angle is too large, the offset amount at the time of ion implantation becomes large, and attention must be paid to the heat treatment conditions.

As described above, according to the present invention, after the gate electrode 3 is formed, the insulating film 12 is deposited, and the sidewalls 15 and 16 composed of the insulating film are formed on the side surfaces of the gate electrode 3 by anisotropic etching. In the method for manufacturing a field effect transistor including the step of forming, after forming the gate electrode 3,
After depositing the insulating film 12, the source and drain regions 5,
Side wall 1 corresponding to the incident side during ion implantation of No. 6
The substrate 1 is made to be a source and drain region 5 so that
The sidewalls 15 and 16 are formed by performing anisotropic etching at the same angle θ as the ion implantation angle of No. 6.

The present invention relates to a FET which does not employ the LDD structure.
After the formation of the gate electrode 3, the main axis of the substrate 1 on which the insulating film 12 is deposited is aligned with the source and drain regions 5 and 6.
Anisotropic etching is performed at the same angle θ as the ion implantation angle to form sidewalls 15 and 16 which are asymmetric with respect to the gate electrode 3. This sidewall 15, 1
Since the insulating film of No. 6 does not increase the etching rate, it is easy to leave even the thin side 16 of the side wall covering or almost covering the side of the gate electrode 3.
Salicide technology can be applicable. Also,
Since the etching rate is not increased, extra ion implantation for this purpose is not required.

Although the above embodiment has been described with reference to a silicon bulk substrate, the present invention can be applied to an SOI substrate such as a SIMOX substrate.

[0030]

As described above, the present invention eliminates the asymmetry of the channel and applies the salicide technology necessary for miniaturization and high integration of FETs in the manufacture of FETs not employing the LDD structure. Can be possible.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a process of manufacturing a conventional FET.

FIG. 3 shows a conventional FET without an LDD structure.
FIG.

FIG. 4 is a cross-sectional view of a conventional FET using a conductive film for a sidewall.

FIG. 5 is a cross-sectional view illustrating a process for manufacturing another conventional FET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate insulating film 3 Gate electrode 5 Source region 6 Drain region 7 Titanium 8 Silicide 12 Insulating film 15, 16 Side wall

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of: depositing an insulating film after forming a gate electrode, and forming sidewalls made of the insulating film on side surfaces of the gate electrode by anisotropic etching. After the formation, an insulating film is deposited, and then anisotropic etching is performed by tilting the substrate at the same angle as the ion implantation angle of the source / drain regions so that the sidewalls are asymmetrical, and ion implantation of the source and drain regions is performed. A method for manufacturing a semiconductor device, comprising forming a thick sidewall on a direction side. 2. The method according to claim 1, wherein the ion implantation angle is 5 to 15 degrees. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming silicide in a gate electrode, a source region, and a drain region after forming the sidewall. 4. The method according to claim 1, wherein the semiconductor device is a field-effect transistor that does not employ an LDD structure.