JP2000124403A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be lessened in wiring resistance and improved on Q value while restraining a skin effect. SOLUTION: A semiconductor device 100 is equipped with an inductor wiring structure 20 formed on a semiconductor substrate 101, where wiring layers 106, 109, and 112 which are shaped in the form of inductors are electrically connected together along all the overall length of the layers through the intermediary of connectors 21. Wiring sections 103 and 111 connected to the outer circuit of the inductor wiring structure 20 are connected to a part of the wiring layer 112 which is shaped in the form of a plane inductor and provided as an uppermost layer out of the laminated wiring layers 106, 109, and 112 and a part of the wiring layer 112 which is shaped in the form of a plane inductor and provided as a lowermost layer out of the laminated wiring layers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an inductor with reduced wiring resistance.

[0002]

2. Description of the Related Art In recent years, with the spread of portable telephones such as PHS, cost reduction of high-frequency circuits for portable telephones has been required. A high-frequency circuit using a CMOS is used to realize the cost reduction. However, in a high-frequency circuit using CMOS, passive elements such as inductor elements, capacitors, and resistors are indispensable for impedance matching.
In order to reduce costs, it is required to mount all of them on one chip.

[0003] Among the passive elements, the resistance and the capacitance can be easily formed on a semiconductor element. Therefore, the key point is the formation of an inductor. At this time,
Circuit designers have demanded inductors having a large inductance and a large Q value (quality factor), a small loss, and a high resonance frequency. In addition, when the number of mobile phone users increases, the number of channels becomes insufficient, and it is necessary to operate the circuit at a higher frequency to secure the channel. However, when an inductor is used at a high frequency, a skin effect occurs, and a high-frequency current flowing through the inductor is generated. Does not flow uniformly in the thickness direction, but flows only on the surface of the conductor, and its depth is called a skin depth and is expressed by the following equation (1).

Δ = 1.59 (ρ / f) 1/2 (1) where δ: skin depth (μm), ρ: specific resistance of wiring (μΩ)
cm), f: Operating frequency (GHz). The Q value is represented by the following equation (2). Q = ωL / R = ωL · S / l · ρ (2) where L: inductance, R: wiring resistance, S: cross-sectional area of wiring, l: wiring length, ρ: specific resistance of wiring It is.

Accordingly, as is apparent from the above equations (1) and (2), when the operating frequency is constant and a material having a small specific resistance ρ is used to increase the Q value, the skin depth δ
And the high-frequency current flows only on the surface of the conductor, and the skin effect becomes more remarkable. As a method to improve the skin effect,
For example, Japanese Patent Application Laid-Open No. 8-288463 is known.

The related art will be described below. FIG. 13 is a view for explaining a method for improving the skin effect in the above-mentioned known example. That is, FIG. 13 (a) shows that S is formed on a semi-insulating GaAs substrate 200 having a thickness of 600 μm.
An insulating film 201 of iO ₂ or the like is deposited to a thickness of 600 nm, and the underlying metal layer for plating 202 is formed of, for example,
(m / 150 nm). Ti is used for ensuring adhesion to the insulating film 201.

Next, a resist pattern 203 corresponding to the strip line is formed by using a usual photolithography technique.
To form When exposing the photoresist, a standing wave is formed on the resist layer due to interference between the incident wave from the light source and the reflected wave from the resist lower surface 205. This is particularly remarkable when a metal layer having a high reflectance such as the plating base metal layer 202 is in contact with the resist lower surface 205.

That is, the portion of the node of the standing wave becomes underexposed, and a deviation occurs between the dimension of the photomask and the dimension of the resist in the development stage. If a positive resist is used as the resist as shown in FIG. 1, the nodes of the standing wave are likely to remain, forming the convex portions 206 of the resist pattern, and the antinodes of the standing wave become the concave portions 207 of the resist pattern.

On the other hand, when a negative type resist is used, the opposite is true. The nodes of the standing wave are easily dissolved in the developing solution, forming concave portions of the resist pattern, and the antinodes become convex portions. The light source used in photolithography is g of an ultra-high pressure mercury lamp.
Line 405 nm or i-line 365 nm. When the wavelength in the vacuum is 405 nm, the wavelength in the resist becomes 270 nm. Therefore, x = 135 × N (N = 0, 1, 2,...) With respect to the distance x from the resist lower surface 205.
·) Ie 0 nm, 135 nm, 270 nm, 405
, and nodes are formed at x = 135 (N + 1/2), that is, at 68 nm, 203 nm,.

In the case of the i-line, the spacing is slightly narrowed, but the same effect of the standing wave appears on the resist cross section. Normally, post-baking after resist development generally eliminates unevenness due to standing waves of the resist. In the above-mentioned known examples, this effect is positively utilized. FIG. 13 (b)
Then, by using the resist 203 as a mask, a current is caused to flow through the plating base metal layer 202 by an Au selective electric field plating method to form a wiring layer 204.

The wiring layer 204 has a shape in which the resist irregularities formed by the standing wave are transferred. In the case of a GaAs monolithic microwave IC operating at 30 GHz, the skin depth of the Au strip line is δ = 0.43 μm. The thickness of the strip line is selected to be three times δ, and 1.3 μm is used. In FIG. 13C, after the resist 203 is removed with a resist stripping material, unnecessary portions of the base metal film 202 for electrolytic plating are removed by ion milling using the wiring 204 as a mask. Through the above steps, the strip line 204 is formed.

The above is the method of improving the skin effect according to the prior art. In recent years, fine CMOS is changing from wiring using conventional aluminum to wiring using copper having lower layer resistance and better thermal conductivity than aluminum. In this case, an interlayer film is formed. Thereafter, a groove is formed in the interlayer film, a wiring or a plug for connecting the upper wiring and the lower wiring is deposited in the groove, and a CMP (Chemical Mechanical) is formed.
Since a technique called "damascene" for embedding wirings and plugs in the trenches using a polishing technique is used, an inductor compatible with this process was required.

In the above method, when copper is used for wiring, copper cannot enter the via hole portion or the plug portion as long as the plating method is employed, so that disconnection often occurs. There was a problem to say. In addition, Japanese Unexamined Patent Publication
Japanese Patent Application Laid-Open No. 227975 describes a high-Q integrated inductance coil. However, there is shown only an example in which a wiring portion having a projection is formed in a spiral shape in a single-layer form. There is no disclosure of a technique for laminating a wiring layer having the planar inductor shape described above.

Further, Japanese Patent Application Laid-Open No. 9-251999 discloses an example in which an uneven shape is formed on a side wall of a metal wiring provided in a semiconductor device.
Japanese Patent Publication No. 264 discloses a semiconductor device which reduces wiring resistance and improves Q value, and has a configuration in which a spiral first wiring layer and a second wiring layer are connected by a plug. In any of the conventional examples, there is no disclosure about a technique of laminating a plurality of wiring section layers having a planar inductor shape and connecting them all over the entire surface.

On the other hand, Japanese Patent Application Laid-Open No. 9-162354 discloses a semiconductor device that reduces wiring resistance and improves the Q value, and includes a plurality of spiral wiring layers as in Japanese Patent Application Laid-Open No. 9-251999. Although a configuration in which the wiring layers are stacked and connected to each other with a plug or a groove-like connecting portion is shown, a configuration in which a terminal is drawn upward from the center of the spiral wiring is employed. Does not have such a wiring drawing configuration.

[0016]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the above-mentioned disadvantages of the prior art, increase the surface area of the inductor, suppress the skin effect, and increase the cross-sectional area of the wiring. An object of the present invention is to provide a semiconductor device capable of reducing wiring resistance and improving a Q value.

[0017]

In order to achieve the above-mentioned object, the present invention employs the following basic technical structure. That is, in the semiconductor device according to the present invention, a plurality of wiring part layers having a planar inductor shape having the same planar shape are coaxial with each other on the surface and inside of the interlayer insulating film formed on the semiconductor substrate. A semiconductor device having an inductor wiring structure formed by being stacked so as to be stacked in a shape, wherein each wiring portion layer having the planar inductor shape is connected to each wiring portion layer having the planar inductor shape. A part of the wiring part layer having the planar inductor shape, which is electrically connected to each other through the connection part over the entire length of the wiring part, and constitutes the uppermost layer of the plurality of wiring part layers laminated. And a wiring part connected to an external circuit of the inductor wiring structure is connected to a part of the wiring part layer having the planar inductor shape forming the lowermost layer. .

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device according to the present invention employs the above-described technical configuration. Since a plurality of stacked wiring portions having a planar inductor shape are electrically connected, the wiring resistance of the inductor can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a specific example of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. That is, FIG. 1 is a cross-sectional view showing the configuration of a specific example of the semiconductor device according to the present invention. In FIG. 1, the same and the same surface is provided on an interlayer insulating film 2 formed on a semiconductor substrate 101. An inductor wiring structure formed by stacking a plurality of wiring part layers 106, 109, and 112 having a planar inductor shape having a planar shape of Semiconductor device 100 having
The respective wiring portion layers 106, 109, and 112 having the planar inductor shape are electrically connected to each other through the connection portion 21 over the entire length of the respective wiring portion layers having the planar inductor shape. And the plurality of wiring portion layers 106, 109, 11
2, a part of the wiring part layer 112 having the planar inductor shape constituting the uppermost layer and a part of the wiring part layer 106 having the planar inductor shape constituting the lowermost layer,
A semiconductor device to which wiring portions 103 and 111 connected to an external circuit of the inductor wiring structure 20 are connected is shown.

In the semiconductor device 100 according to the present invention, the wiring section layers 106, 109, and 11 having a plurality of planar inductor shapes arranged adjacent to each other.
.. Indicate connection portions 2 provided in the respective wiring portion layers.
It is preferable that 1 has a width smaller than the width of the wiring main body 22 constituting the upper part of the wiring section layer. Further, in the semiconductor device 100 according to the present invention, it is preferable that the connection portion 21 is formed of a projection 23 extending downward from the wiring body 22.

The shape of the projection 23 is not particularly limited, and may be, for example, a rectangular projection as shown in FIG. 1 or a projection in a curved shape, a triangular shape, or the like. May be. Further, the entire cross section of the connection portion 21 may be formed in a curved shape, or may be formed in an inverted triangular shape.

On the other hand, as the wiring portion layer having the planar inductor shape used in the semiconductor device according to the present invention, for example, a spiral formed in a planar shape as shown in FIG. It may be formed of a shape-like wiring, or a single wiring may form a closed loop, and a part thereof may have a shape formed in a discontinuous state.

In short, it is desirable that all of the wiring section layers 21 having a plurality of planar inductor shapes used in the semiconductor device 100 have the same shape. As described above, in the semiconductor device 100 according to the present invention, the wiring portion layers 21 having the plurality of planar inductor shapes are concentrically overlapped with each other in a predetermined interlayer insulating film. In the laminated structure, the connection portion 22 of the wiring portion layer 21 having one planar inductor shape is connected to another planar inductor shape laminated thereunder. Body 2 of wiring section layer 22 having
3 are directly laminated.

On the other hand, the wiring section layer 10 having the planar inductor shape and integrally laminated with each other.
6, 109, 112,..., The connection section 22 is not formed below the wiring section layer 106 having the planar inductor shape that constitutes the lowermost layer section. Section layer 106 having a typical inductor shape
In at least a part of the lower part of the semiconductor device, an independent plug-shaped connection component 24 for forming an electrical connection is formed at a part where a contact with the wiring part 103 connected to the external circuit is formed. It is desirable that it is done.

Similarly, the wiring section layer 10 having the planar inductor shape and integrally laminated with each other.
6, 109, 112,..., At least a portion of the wiring portion layer 112 having the planar inductor shape constituting the uppermost layer portion is electrically connected to the wiring portion 111 connected to the external circuit. It is desirable that the connection be formed in order to make the connection.

In the present invention, the connection portion 21 is formed by wiring portion layers 106 and 109 having the planar inductor shape.
112.. May be made of the same material as the wiring main body part 22 constituting each upper part, or may be made of different materials. Further, in the present invention, a plurality of the connection portions 21 are formed for each of the wiring portion main bodies 22 in the wiring portion layers 106, 109, 112,... Having one planar inductor shape. It is also desirable to have.

The plurality of connection portions 21 are formed by wiring portion layers 106, 109, and 112 having the planar inductor shape.
Are preferably arranged in parallel with each other in the longitudinal direction of the wiring body 22 and in parallel with each other. In the present invention, the shape and number of the connections formed in the wiring section layers 106, 109, 112,... Having the respective planar inductor shapes may be the same between the wiring section layers. Alternatively, they may be configured differently from each other.

Similarly, the cross section of the wiring portion layer having a planar inductor shape including the wiring main body portion 22 and the connection portion 21 in the wiring portion layers 106, 109, 112,. The shape may be the same between the wiring portion layers stacked on each other, or may be different from each other. The wiring section layer 10
The cross-sectional shapes of 6, 109, 112,... Are configured such that, for example, the cross-sectional area of the lower wiring layer is smaller than the cross-sectional area of the upper wiring layer. Is also preferred.

In the present invention, the connection portions 21 provided on the wiring portion layers 9, 12,... Having the planar inductor shape are connected to the interlayer insulating films 102, 104,
07, 110,... Are connected to the wiring body 22 of the wiring layers 106, 109 having another planar inductor shape disposed below through the slit-shaped groove 116 provided in the inside. Things.

Hereinafter, the semiconductor device 10 according to the present invention will be described.
The configuration of the specific example of Example 0 and the specific example of the manufacturing method thereof will be described in detail. FIG. 2A shows a characteristic portion of a planar layout of a spiral inductor which is a wiring portion layer having a planar inductor shape, and a wiring portion layer 106 having a first planar inductor shape which is a first wiring. And the upper lead-out electrode line 1 connected to a wiring portion layer having a planar inductor shape, for example, a spiral inductor 112 formed of the uppermost layer.
14 is shown.

That is, the wiring layers 106, 109, 112,... Having the planar inductor shape according to the present invention.
.. Have the same shape and are concentrically stacked with each other. FIG. 2B is an enlarged view of a portion shown by a dashed line in FIG. 2A for specifically describing FIG.
The dot-shaped first via 115 and the wiring section layer 106 having the first planar inductor shape are arranged as shown in the drawing.

Similarly, FIG. 2 (C) is an enlarged view of the portion shown by the dashed line in FIG. 2 (A) in order to specifically explain the state of lamination in FIG. 2 (A). In addition, it shows a connection state between the wiring portion layer 106 having the first planar inductor shape and the wiring portion layer 109 having the second planar inductor shape, and shows the wiring having the first planar inductor shape. A slit-shaped second via 116 is provided between the external layer 106 and the wiring section layer 109 having the second planar inductor shape, and a portion corresponding to the second via 116 according to the present invention is provided. The connection portion 21 is formed.

Incidentally, FIGS. 1A and 1B show FIGS.
(C) It is the figure which showed the cross section of AB section of the top view of a spiral inductor. From FIGS. 2A to 2C and FIG. 1, the wiring layer layers 106, 109, and 112 having the first to fourth planar inductor shapes forming the coil portion 20 of the spiral inductor are slit-shaped. Via 116
And the second wiring forming the coil portion of the spiral inductor, that is, the wiring section layer 106 having the first planar inductor shape. It can be seen that only the dots are connected by the dot-shaped first via 115.

Next, a method of manufacturing the semiconductor device 100 shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. First, as shown in FIG. 3A, a first interlayer insulating film 102 of 1000 to 1600 nm is formed on a P-type semiconductor substrate 101, and aluminum of 500 to 1000 nm is formed.
A first wiring 103 of copper or the like is formed, and then a second interlayer insulating film 104 is grown. On the first wiring 103, the thickness of the interlayer insulating film 104 becomes 1000 to 2000 nm. As described above, the surface is made flat using a known technique such as CMP and etch back.

Next, as shown in FIG. 3B, a first mask 1 for forming a via on the second interlayer insulating film 104 is formed.
17 is formed, and then a second mask 118 for forming a wiring is formed. Next, as shown in FIG.
2 is formed in a portion where both the mask 117 and the second mask 118 are opened and the second interlayer insulating film 104 is exposed.
As shown in FIG. 3B, the first via 115 in a dot shape is etched by a known anisotropic etching technique.

In the etching, the first wiring 1
03, the second interlayer insulating film 104 has a thickness of 200 to 700 nm.
It is desirable to stop the etching so as to remain to the extent. Next, as shown in FIG. 4D, the first mask 117 exposed at the opening of the second mask 118 is removed from the second interlayer insulating film 1.
04 is selectively etched to form an opening by the second mask 118 for forming a wiring in the second interlayer insulating film 10.
4 is formed.

Next, as shown in FIG. 4E, the surface of the second interlayer insulating film 104 exposed in FIG. 4D is etched by 500 to 1000 nm by a known anisotropic etching technique. After forming a groove 119 for forming a second wiring corresponding to the wiring section layer 106 having one planar inductor shape, the first mask 117 and the second mask 118 are removed.

At this time, the first via 115 is also etched at the same time, and the first wiring 10 is formed at the bottom of the first via 115.
The surface of No. 3 is exposed. Next, as shown in FIG. 4F, after forming a first barrier metal 105 having a thickness of 10 to 300 nm, a second wiring 106 made of aluminum, copper, or the like having a thickness of 800 to 2000 nm is formed by a CVD technique. Via 11
5 and the trench 119 for forming the wiring are completely buried.

Next, as shown in FIG. 5G, the second interlayer insulating film 1 is formed by using a well-known technique such as CMP and etch back.
04 is flattened to form a wiring layer 106 having a first planar inductor shape as a second wiring. Next, as shown in FIG. 5H, FIG.
After the step (G) is repeated to form the third interlayer insulating film 107, the second via 116 and the trench 119 for forming the wiring are formed.
Is formed, and a second barrier metal 10 of 10 to 300 nm is formed.
8, 800-2000 nm aluminum, copper, etc. are formed by CVD technique, and the second via 116 and the trench 119 for forming wiring are completely buried. Then, the third interlayer insulating film is formed by CMP, etching or the like. The surface of the film 107 is flattened to form a wiring portion layer 109 having a second planar inductor shape as a third wiring.

As shown in FIGS. 2A and 2B, the first via 115 is dot-shaped and the second via 11
6 is formed in a slit shape. Further, in this specific example, the above-described steps of FIGS. 4A to 5G are repeated to form a fourth interlayer insulating film 110 and a third barrier metal 111 of 10 to 300 nm. 8 by CVD technology
Aluminum, copper, or the like having a thickness of 00 to 2000 nm is formed, and a via 11 is formed.
6 and the trench 119 for forming the wiring are completely buried, and then the fourth interlayer insulating film 11 is formed by CMP, etching or the like.
The surface of No. 0 is flattened to form a wiring portion layer 112 having a third planar inductor shape as a fourth wiring.

In the above embodiment according to the present invention,
The wiring portion layer having the planar inductor shape has three layers 10
6, 109 and 112, but the present invention is not limited to this specific example, and the wiring portion layer having the planar inductor shape is formed in four layers or four or more layers. Needless to say, it may be something.

The semiconductor device 100 according to the present invention has, in addition to the above-described structure, a connection portion including a projection below a wiring portion of an inductor formed on a semiconductor substrate via an insulating film, and The connection part 21 formed below the wiring body part 22 of the wiring part layer having the planar inductor shape is made of the same material as the wiring body part 22, and in another specific example, The two may be made of different materials.

A specific example of the semiconductor device 100 according to the present invention will be described with reference to FIGS. The method of manufacturing the semiconductor device 100 in this specific example is basically similar to that of FIG.
5 to FIG. 5, but a plurality of connection portions 21 are arranged in parallel with each other with respect to the wiring main body portion 22 constituting each layer of the wiring portion layer having the planar inductor shape. The points are different.

FIG. 6A shows a characteristic portion of the planar layout of the spiral inductor, and the fourth wiring 312
A wiring portion layer having a planar inductor shape, which is composed of an upper lead electrode 314 and a third wiring 309 connected to the wiring layer 312, and a second wiring 306. The wiring portion layer having a planar inductor shape and the lower extraction electrode 313 connected to the wiring portion layer 306 having the planar inductor shape are shown as overlapping.

FIG. 6B is an enlarged view of a portion indicated by a dashed line in FIG. 6A in order to explain in detail the characteristics of the cross-sectional structure of the spiral inductor in this embodiment. 6A, only a part 319 of the wiring layer 306 having the planar inductor shape of the lowermost layer in FIG. 6A is extracted, and this spiral inductor is a first wiring which is a second wiring.
The wiring portion layer 306 has a planar inductor shape, and a plurality of slit-shaped protrusions 320 arranged in parallel to each other, and has a planar layout shown in the figure.

Similarly, FIG. 6C shows the wiring section layer 30 having the planar inductor shape of the lowermost layer shown in FIG. 6B.
In order to specifically explain the structure of the part 319 in the wiring layer 6, the wiring layer 3 having the planar inductor shape of the lowermost layer
12 shows a cross-sectional structure of an EF section of No. 06. First,
A characteristic portion of the cross-sectional structure of the inductor according to this example will be described with reference to FIG.

Portion 3 constituting a part of wiring portion layer 306 having the planar inductor shape of the lowermost layer in this embodiment.
Reference numeral 19 denotes the wiring layer 3 having the planar inductor shape.
06, a connecting portion 21 comprising a wiring main body 22 and a slit-shaped protrusion 320 protruding downward from the wiring main body 22
It can be seen that it is composed of Of course, in this specific example, the wiring body portion 22 of the wiring portion layer 306 having the planar inductor shape and the connection portion 21 including the slit-shaped protrusion 320 protruding downward from the wiring body portion 22 are formed. Are made of the same material.

Next, FIG. 7 is a diagram showing a cross section taken along the line CD of the spiral inductor shown in FIG. 6A. From FIG. 6C and FIG. 7, the first wiring which is the second wiring forming the coil part of the spiral inductor is shown.
Wiring portion layer 306 having a planar inductor shape and a third
As shown in FIG. 6C, the wiring section layer 309 having the second planar inductor shape has a plurality of protrusions 320 below each wiring, and the third wiring which is the third wiring. A projection 320 formed under the wiring portion layer 309 having the two planar inductor shapes serves as a plurality of slit-shaped vias and is connected to the second wiring 306.

Further, it can be seen that the fourth wiring 312 is connected to the upper part of the wiring portion layer 309 having the second planar inductor shape to form the extraction electrode 314. Hereinafter, specific examples of the semiconductor device according to the present invention will be described with reference to FIGS. In particular,
In FIGS. 8A to 9E, a wiring portion layer 306 having the first planar inductor shape, which is a second wiring, and a slit-like protrusion below the second wiring 306 are shown. The method of forming the connection portion 21 made of the object 320 will be described in detail.

First, as shown in FIG. 8A, a first interlayer insulating film 302 of 1000 to 1600 nm is formed on a P-type semiconductor substrate 301, and a barrier metal 321 of 10 to 1000 nm and a first interlayer insulating film 302 of 500 to 1000 nm are formed. 1 wiring 303
This first wiring is used for wiring of active elements such as NMOS and PMOS formed on a silicon substrate.

Next, a second interlayer insulating film 304 made of, for example, an oxide film and a BPSG film is grown, and a first wiring 303 is formed.
After the upper surface is formed to have a thickness of 100 to 500 nm using a known technique such as CMP or etch back so as to have a flat surface, the second interlayer insulating film 304 is different in film quality, for example, nitrided. A third interlayer insulating film 307 made of a film is formed, and a fourth interlayer insulating film 310 made of the same film as the second interlayer insulating film 304 is formed.

Next, as shown in FIG. 8B, a first mask 3 for forming wiring on the fourth interlayer insulating film 310 is formed.
17 for forming a wiring portion layer 306 having a first planar inductor shape as a second wiring.
6a, 306b and 306c are formed respectively.
Next, as shown in FIG. 8C, a second mask 318 made of, for example, a photoresist is formed, and a second mask 318 for connecting to the first wiring 303 is formed by a known anisotropic etching technique. One via 315a and a groove-like via 315b for forming the connecting portion 21 made of a protrusion below the wiring portion layer 306 having the planar inductor shape are formed.

At this time, strictly speaking, 315a and 315
Compared with the depth of the first wiring 3b, the depth of the first wiring 3b is larger than that of the first wiring 3b.
This difference can be almost eliminated by making the thickness of the third interlayer insulating film 310 sufficiently larger than the thickness of the second interlayer insulating film on the substrate 03. Next, as shown in FIG.
After removing the mask 317 and the second mask 318, a first barrier metal 305 of 10 to 300 nm is formed, and then 800 to 200 nm by a technique such as sputtering or CVD.
A wiring section layer 306 having a first planar inductor shape, which is a second wiring of aluminum, copper, or the like having a thickness of 0 nm, is formed.
Vias 315a, 315b and grooves 306a, 306b, 306c for forming the second wiring are completely buried.

Next, as shown in FIG. 9E, the second interlayer insulating film 3 is formed by using a known technique such as CMP and etch back.
10 has a flattened surface, and a second wiring 306 is formed. Further, the steps of FIGS. 8A to 9E are repeated to form a wiring portion layer 309 having a second planar inductor shape, and then an upper lead electrode 314 formed of a fourth wiring 312 is formed. FIG. 7 shows the result.

In the above description, the wiring body part 2 of the wiring part layers 309 having the planar inductor shape has been described.
Although an example is shown in which one connecting portion 22 is formed for two, actually, as shown in the drawing, a plurality of such connecting portions 22 are formed for one wiring main body 22. It is. As described above, in order to further improve the skin effect at high frequencies, it is effective to increase the surface area of the spiral inductor. One method of implementing this is to place the spiral inductor under the wiring body 22 under the spiral inductor. It is possible to increase the surface area by further reducing the width and interval of the formed projections.

In the above specific example, the wiring body 22 and the connecting part 2 of the wiring part layer having the planar inductor shape are used.
1 and the same material are formed at the same time. However, when this method is used, the aspect ratio of the projection (via) becomes large, so that the projection (via) can be completely embedded. It becomes difficult. In order to avoid this, the following specific example is used.

Next, another specific example according to the present invention will be described.
The manufacturing method according to the second embodiment will be described with reference to FIGS.
This will be described with reference to FIG. That is, in the present embodiment, the wiring body 22 and the connecting member 2 in the wiring layer having a planar inductor shape are different from the above-described embodiment.
1 is formed of a different material.

Particularly, in FIGS. 11 (A) to 12 (E),
The wiring body 22 of the wiring layer 306 having the first planar inductor shape as the second wiring and the wiring body 2
2 and 21 ′, which are composed of plug-like or groove-like slits underneath, and correspond to the connection portions 21.
The method for forming the layer will be described in detail. First, FIG.
As shown in FIG.
Forming a first interlayer insulating film 302 having a thickness of
0 to 1000 nm barrier metal 321 and 500 to 1
A first wiring 303 of 000 nm is formed.

The first wiring 303 is used for wiring active elements such as NMOS and PMOS formed on a silicon substrate. Next, for example, an oxide film,
Growing a second interlayer insulating film 304 made of a BPSG film;
The surface is flattened by a known technique such as CMP or etch-back so that the thickness of the second interlayer insulating film 304 formed on the first wiring 303 is 100 to 500 nm. It is formed as follows.

Next, as shown in FIG. 11B, a mask made of, for example, a photoresist is formed on the second interlayer insulating film 304, and is formed by a known anisotropic etching technique.
A via 116 for forming a connection portion 21 ′ for making a connection with the first wiring 303, and a projection corresponding to the connection portion 21 below the wiring portion layer 319 having the first planar inductor shape. Forming a via 116 for forming
After forming a fourth barrier metal 305a of ~ 300 nm,
800 to 200 by techniques such as CVD or sputtering
Fifth wiring 306a of 0 nm aluminum, tungsten, etc.
Is formed, and the inside of the via is completely buried.

Next, as shown in FIG.
By using a technique such as etch back, the second interlayer insulating film 304 is exposed, and the fourth barrier metal 305a and the fifth wiring 306a are completely buried only inside the via to form a plug. Next, as shown in FIG.
After growing the third interlayer film 308 having a thickness of 00 to 2000 nm, a groove for forming a wiring portion layer 306 having a first planar inductor shape as a second wiring is formed by a known anisotropic etching technique. Then, a first barrier metal 305 having a thickness of 10 to 300 nm is formed, and 800 to 2 nm is formed by a technique such as sputtering, plating, or a combination of sputtering and plating.
It is assumed that a second wiring 306 of 000 nm copper, gold, or the like is formed and the inside of the groove is completely buried.

Next, as shown in FIG.
The third interlayer film 31 is formed by using a known technique such as etch back.
8 is flattened to form a wiring layer 306 having a first planar inductor shape as a second wiring. Further, the steps of FIGS. 11A to 12E are repeated to form the wiring layer 30 having the second planar inductor shape.
After the formation of No. 9, the semiconductor device 100 of the present invention shown in FIG.

In the above specific example, an example of a method of forming one connection portion 21 with respect to the wiring body portion 22 of the wiring portion layer having one planar inductor shape has been described for convenience. Each connection part 21 is connected to one wiring body part 22.
However, it is desirable to arrange a plurality as shown in FIG. As can be seen from the above description of the specific example, in the spiral inductor according to another specific example of the present invention, the wiring material layer having a planar inductor shape, for example, the constituent material of the wiring main body portion 22 forming the wiring portion layer 306 and the wiring main body portion 22 The slit-shaped projections 305a and 306a forming the connection portion 21 connected to the projections are formed of different materials, and the material and the method of the embedding property are used. Since the number can be increased, the surface area of the spiral inductor can be increased, and the skin effect in a high frequency region is improved.

Next, another embodiment according to the present invention will be described below. In this specific example, the cross-sectional shape of the wiring portion layer is configured such that the cross-sectional area of the lower wiring portion layer is smaller than the cross-sectional area of the upper wiring portion layer. More specifically, a wiring section having a plurality of planar inductor shapes formed in each of the above specific examples formed on a semiconductor substrate via an insulating film. The inductor forming the layer has a structure in which an upper layer wiring is formed so as to cover a lower layer wiring in a laminated structure.

First, another specific example of the present invention will be described with reference to FIGS. FIG. 14A shows a characteristic portion of the planar layout of the spiral inductor, and FIG.
As shown in FIG. 7, an upper extraction electrode 314 composed of a fourth wiring 312, a wiring part layer 309 having a second planar inductor shape as a third wiring, and a first planar electrode being a second wiring. The wiring portion layer 306 having an inductor shape and the lower extraction electrode 313 drawn from the lower portion of the wiring portion layer 306 are shown overlapping.

FIG. 14B is an enlarged view of the portion indicated by the dashed line in FIG. 14A in order to explain the characteristics of the cross-sectional structure of the spiral inductor of this example in detail.
Only the lowermost wiring portion layer 306 having a planar inductor shape in FIG. 14A is extracted, and this spiral inductor is the second wiring portion in the wiring portion layer 306 having a planar inductor shape. Constituting the wiring body 22 and the connecting portion 21 connected to the wiring body 22;
It is composed of a slit-shaped projection 320.

Similarly, FIG. 14C shows a plan view of the lowermost layer in order to specifically explain the structure of the wiring section layer 306 having the lowermost planar inductor shape shown in FIG. 14B. 9 shows a cross-sectional structure of an EF section of a wiring section layer 306 having an inductor shape. First, a characteristic portion of the cross-sectional structure of the inductor of this example will be described with reference to FIG.

That is, the wiring layer 306 having the first planar inductor shape of the lowermost layer in the present specific example is formed by the wiring body 22 of the wiring layer 306 and the slit-shaped portion provided in the wiring body 22. The wiring portion layer 309 having the planar inductor shape of the uppermost layer is composed of the wiring portion 22 having the second planar inductor shape and the wiring body portion 22 of the wiring portion layer having the second planar inductor shape. The spiral inductor 309 in the uppermost layer is wider than the spiral inductor 306 in the lowermost layer, and the spiral inductor 309 in the uppermost layer. It can be seen that a part of the slit-like projection 320b below is not connected to the lowermost spiral inductor 306.

Incidentally, in the spiral inductor which is a wiring layer having a planar inductor shape in this embodiment,
The material for the wiring forming the inductor and the material for forming the slit-shaped protrusion may be made of the same material or may be different. Next, FIG.
FIG. 15 is a diagram illustrating a cross-section taken along line C-D of the plan view of the spiral inductor illustrated in FIG.

From FIG. 14C and FIG. 15, the wiring layer 3 having the first planar inductor shape, which is the second wiring forming the coil portion of the spiral inductor.
As shown in FIG. 14 (C), the wiring section layer 309 having the second planar inductor shape, which is the third wiring 06 and the third wiring, includes a plurality of protrusions 32 forming the connection section 21 below each wiring.
0, and the plurality of protrusions 3 as connection portions 21 formed below the wiring main body portion 22 of the wiring portion layer 309 having the second planar inductor shape as the third wiring.
20 is a wiring portion layer 3 having a first planar inductor shape, which is a second wiring, serving as a plurality of slit-shaped vias.
06 is connected to the wiring body 22.

Further, a part of the projection 320 formed under the wiring portion layer 309 having the second planar inductor shape, which is the third wiring, is a part of the first wiring which is the second wiring. It can be seen that it is not connected to the wiring section layer 306 having a typical inductor shape. Further, the fourth wiring 312 is formed on the wiring portion layer 30 having the second planar inductor shape.
It can be seen that 9 upper extraction electrodes 314 are configured.

Next, a specific example of a method of manufacturing the semiconductor device 100 according to another embodiment of the present invention will be described in detail. That is, a manufacturing method of another specific example according to the present invention described above will be described with reference to FIGS. In particular, in FIGS. 16A to 17E, a wiring section layer 306 having a first planar inductor shape, which is a lowermost second wiring, and a slit below the second wiring 306. The method for forming the protrusions 320 will be described in detail.

First, as shown in FIG. 16A, a first interlayer insulating film 302 of 1000 to 1600 nm is formed on a P-type semiconductor substrate 301, and a first barrier metal 321 and 500 to 1000 nm of 1000 to 1600 nm is formed. A first wiring 303 of 1000 nm is formed. The first wiring 303 is formed on a silicon substrate and is used for wiring of active elements such as NMOS and PMOS.

Next, a second interlayer insulating film 304 made of, for example, an oxide film and a BPSG film is grown, and a first wiring 303 is formed.
The interlayer insulating film 304 has a thickness of 100 to 500 n
After forming the surface to be flat using a known technique such as CMP and etch back so as to have a film thickness of m, the second
A third interlayer insulating film 307 made of, for example, a nitride film having a different film quality from that of the second interlayer insulating film is formed, and a fourth interlayer insulating film 310 made of the same film as the second interlayer insulating film is formed.

Next, as shown in FIG. 16B, a first mask 317 for forming a wiring is formed on the fourth interlayer insulating film 310, and a first plane which is a second wiring is formed. 3 for forming wiring portion layer 306 having a typical inductor shape
06a, 306b, and 306c are respectively formed. Next, as shown in FIG. 16C, for example, a second mask 318 made of a photoresist is formed, and a second mask 318 for connecting to the first wiring 303 is formed by a known anisotropic etching technique. 1 via 315a and a connection portion 2 under the wiring portion layer 306 having the first planar inductor shape.
1 for forming, for example, a groove 31 for forming a projection
5b.

At this time, strictly speaking, 315a and 315a
Compared with the depth of the first wiring 1b, the depth of the first wiring 1
This difference can be almost eliminated by making the thickness of the third interlayer insulating film sufficiently larger than the thickness of the second interlayer insulating film on the substrate 03. Next, as shown in FIG. 17D, after the first mask 317 and the second mask 318 are removed,
After forming the first barrier metal 305 of 0 to 300 nm,
800-2000nm by techniques such as sputtering and CVD
A second wiring 306 made of aluminum, copper, or the like is formed, and first vias 315a and 315b and a groove for forming a wiring portion layer 306 having the first planar inductor shape as the second wiring are formed. 306a, 306b and 306c are completely embedded.

Next, FIG. 17E shows a state where the surface of the second interlayer insulating film 104 is flattened by using a known technique such as CMP or etch back to form a second wiring 106. Further, the steps of FIGS. 16 (A) to 17 (E) are repeated to form an upper extraction electrode 314 including a wiring portion layer 309 having a second planar inductor shape and a fourth wiring 312. The completed semiconductor device 100 is shown in FIG.

In this specific example, as described above, the second
When the wiring portion layer 309 having the planar inductor shape is formed, the width or length of the wiring main body portion 22 is changed to the wiring portion layer 306 having the first planar inductor shape.
It is necessary to be configured to be longer than the width or length of the wiring portion layer 309 having the second planar inductor shape. It is necessary that the number of the connecting portions 21 provided on the wiring body 22 of the wiring portion layer 306 having the first planar inductor shape be larger than the number of the connecting portions 21.

In the above specific example, for convenience, an example of a method of forming one connection portion 21 with respect to the wiring body portion 22 of the wiring portion layer having one planar inductor shape has been described. Each connection part 21 is connected to one wiring body part 22.
However, it is desirable to arrange a plurality as shown in FIG. In this specific example, in the spiral inductor which is a wiring portion layer having a planar inductor shape, a case where a material of a wiring forming the inductor and a material forming a slit-shaped protrusion are formed of the same material is described. Although described, in this specific example, the material of the wiring forming the inductor and the material forming the slit-shaped protrusion may be formed of different materials,
In this case, the method described with reference to FIGS. 11 and 12 can be used as the manufacturing method.

The semiconductor device 100 according to the present invention
In any of the specific examples, the wiring layer 106 or 306 having the first planar inductor shape is used.
Connection portion 21 formed below the wiring body portion 22
Is formed with a columnar projection at a portion connected to the lead line 103 or 303.
The wiring body 22 on the side where 03 or 303 is arranged
In order to prevent short-circuiting, it is preferable that the projections forming the connection portion 21 are not formed.

The other wiring body 22 has a groove shape over the entire length of the wiring layer having the planar inductor shape.
A projection such as a curved shape is formed. Next, FIG.
Still another specific example of the present invention will be described with reference to FIGS. That is, FIG. 21 shows a semiconductor device 100 obtained according to still another embodiment of the present invention, which is characterized in that both upper and lower portions of the wiring main body portion 22 of the wiring portion layer having a planar inductor shape are provided. In addition, a projection that constitutes the connection portion 21 is provided. Needless to say, by employing such a configuration, the skin effect of the inductor can be further improved.

Next, FIG. 21 and FIGS.
The manufacturing method of this example will be described with reference to FIG. That is,
Each of the manufacturing steps shown in FIGS.
Since it is the same as the manufacturing process of FIGS. 11A to 12E in the above specific example, detailed description thereof will be omitted.

After the semiconductor device having the structure shown in FIG. 20E is formed, the method shown in FIGS. 19B and 19C is repeated to form a wiring layer having the first planar inductor shape. A fourth interlayer insulating film 310 is formed on the wiring layer 306, and a slit-shaped via 117 is opened on the wiring section layer 306 having the planar inductor shape.
08a and the sixth wiring 309a are completely buried, and thereafter, a flattening process is performed to form the projection 21 ″.

[0084]

Since the semiconductor device according to the present invention employs the above-described technical configuration, the wiring is formed below or above the wiring of the inductor composed of the wiring section layer having the planar inductor shape. By forming a projection made of a plug made of the same material as that used, the surface area of the inductor can be increased and the skin effect can be suppressed.

Further, below or above the wiring of the inductor comprising the wiring section layer having the planar inductor shape,
By forming the projections made of a material different from the material used for the wiring, the metal wiring material is reliably embedded in the narrow groove, and the yield of the semiconductor device is improved. Further, by increasing the cross-sectional area of the wiring portion layer having the planar inductor shape, the wiring resistance can be reduced and the Q value can be improved.

Further, in the present invention, since the width of the wiring constituting the inductor increases as the layer becomes higher, the parasitic capacitance between the substrate and the wiring of the inductor can be reduced. on the other hand,
In the semiconductor device according to the present invention, the lower-layer inductor and the upper-layer inductor are connected to each other via a slit-shaped via having the same planar layout as the inductor, thereby reducing the wiring resistance of the inductor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a specific example of a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a specific example of a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing main steps in a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view showing main steps in a manufacturing method in one embodiment of the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing main steps in a manufacturing method in one embodiment of the semiconductor device of the present invention.

FIG. 6 is a diagram illustrating a configuration of another specific example of the semiconductor device of the present invention.

FIG. 7 is a sectional view showing main steps in a method of manufacturing a semiconductor device according to another specific example of the present invention.

FIG. 8 is a sectional view showing main steps in a manufacturing method in another specific example of the semiconductor device of the present invention.

FIG. 9 is a sectional view showing main steps in a method of manufacturing a semiconductor device according to another specific example of the present invention.

FIG. 10 is a sectional view showing a configuration of another specific example of the semiconductor device of the present invention.

FIG. 11 is a diagram illustrating a configuration of another specific example of the semiconductor device according to the present invention.

FIG. 12 is a cross-sectional view showing main steps in a manufacturing method in another specific example of the semiconductor device of the present invention.

FIG. 13 is a cross-sectional view showing a main step in one example of a conventional method for manufacturing a semiconductor device.

FIG. 14 is a diagram illustrating a configuration of still another specific example of the semiconductor device according to the present invention.

FIG. 15 is a sectional view showing the configuration of still another specific example of the semiconductor device of the present invention.

FIG. 16 is a cross-sectional view showing main steps in a manufacturing method in still another specific example of the semiconductor device of the present invention.

FIG. 17 is a cross-sectional view showing main steps in a manufacturing method in still another specific example of the semiconductor device of the present invention.

FIG. 18 is a cross-sectional view showing the configuration of still another specific example of the semiconductor device of the present invention.

FIG. 19 is a cross-sectional view showing main steps in a manufacturing method in still another specific example of the semiconductor device of the present invention.

FIG. 20 is a cross-sectional view showing main steps in a manufacturing method in still another specific example of the semiconductor device of the present invention.

FIG. 21 is a sectional view showing the configuration of still another specific example of the semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 20 ... Inductor and coil structure 21 ... Connection part 22 ... Wiring main body part 23, 320 ... Protrusion thing 24 ... Connection constitution part, via hole 100 ... Semiconductor device 101, 301 ... Substrate 102, 302, 104, 304, 107, 307 , 1
10, 318 ... interlayer insulating film 103, 303 ... lead wire 105, 108, 111, 308 ... barrier metal 106, 306 ... wiring part layer having the first planar inductor shape 109, 309 ... second planar inductor Wiring portion layer having a shape 112 ... Wiring portion layer having a third planar inductor shape 114, 312, 314 ... Lead wire 115 ... Dot-shaped via 116 ... Slit-like via 117, 118 ... Mask 119 ... Wiring main body Forming groove

Claims (13)

[Claims] A plurality of wiring layers having a planar inductor shape having the same planar shape are laminated concentrically on the surface and inside of an interlayer insulating film formed on a semiconductor substrate. A semiconductor device having an inductor wiring structure formed by depositing in the same manner as described above, wherein each wiring portion layer having the planar inductor shape is formed over the entire length of each wiring portion layer having the planar inductor shape. Are electrically connected to each other via a connection portion,
Part of the wiring part layer having the planar inductor shape constituting the uppermost layer of the plurality of laminated wiring part layers and part of the wiring part layer having the planar inductor shape constituting the lowermost layer A wiring portion connected to an external circuit of the inductor wiring structure. 2. The wiring part layer having a plurality of planar inductor shapes arranged adjacent to each other, wherein the connection part provided in each wiring part layer has a wiring forming an upper part of the wiring part layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a width smaller than a width of the main body. 3. The semiconductor device according to claim 2, wherein said connection portion is formed of a projection extending downward from said wiring body. 4. The connecting portion having a planar inductor shape, which constitutes a lowermost layer portion, of a plurality of interconnect portion layers having the planar inductor shape which are integrally laminated with each other. Wherein an independent connection component for forming an electrical connection is formed in a portion where a contact with a wiring portion for connecting the external circuit is formed. 4. The semiconductor device according to any one of 1 to 3. 5. The connection part is made of the same material as a wiring body part forming an upper part of the wiring part layer having the planar inductor shape.
The semiconductor device according to any one of the above. 6. The connection part according to claim 1, wherein the connection part is made of a material different from that of a wiring body part forming an upper part of the wiring part layer having the planar inductor shape. 3. The semiconductor device according to claim 1. 7. The semiconductor device according to claim 1, wherein a plurality of said connection portions are formed for a wiring portion layer having one planar inductor shape. 8. The wiring section according to claim 7, wherein the plurality of connecting sections are arranged in parallel with a longitudinal direction of the wiring body section of the wiring section layer having the planar inductor shape.
13. The semiconductor device according to claim 1. 9. A wiring section layer having a planar inductor shape including the wiring main body section and the connection section, wherein a cross-sectional shape of the wiring section layer in the stacked layers is the same. Item 9. The semiconductor device according to any one of Items 1 to 8. 10. A cross-sectional shape of a wiring portion layer having a planar inductor shape including the wiring main body portion and the connection portion is different between the wiring portion layers in each of the stacked layers. The semiconductor device according to claim 1. 11. The cross-sectional shape of the wiring portion layer is such that the cross-sectional area of the lower wiring portion layer is smaller than the cross-sectional area of the upper wiring portion layer. The semiconductor device according to claim 10, wherein: 12. The connecting portion provided on the wiring portion layer having the planar inductor shape, wherein the connecting portion is provided below another via a slit-like groove provided in the interlayer insulating film. 12. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a wiring body of a wiring portion layer having a planar inductor shape. 13. The connection portion provided on the wiring body portion of the wiring portion layer having the planar inductor shape is formed on both upper and lower surfaces of the wiring body portion. Item 13. The semiconductor device according to any one of Items 1 to 12.