JP2000121678A - Comparison device - Google Patents

Abstract

(57) Abstract: Provided is a comparison device that can widen a range of input signal voltages that can perform a comparison operation as compared with a comparison device including a single comparator (comparator). SOLUTION: An inverter 60 generates an inverted signal / Sin of the input signal Sin. The first comparator CMP1 is
The input transistor is constituted by a P-type MOS transistor, the + input terminal is connected to the signal input terminal T40A via the N-type MOS transistor 61N, and the first reference signal Sref1 is supplied to the-input terminal. In the second comparator CMP2, the input transistor is formed of an N-type MOS transistor, the + input terminal is connected to the signal input terminal T40A via the P-type MOS transistor 62P,
The second reference signal Sref2 is supplied to the negative input terminal.
The selection circuit 66 includes a first comparator CMP and a second comparator CMP.
1, one of the output signals Vc1 and Vc2 of CMP2 is selected and output to the signal output terminal T40Z.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparison device for comparing an input signal with a reference signal.

[0002]

2. Description of the Related Art FIG. 1 is a circuit diagram showing an example of a differential input type (differential amplification type) comparator. The comparator 100 includes an amplifier circuit 1 of an input stage (input amplification stage), a feedback circuit 2, and an output buffer circuit 3
And One input terminal T1 of the comparator 100
A is supplied with an input signal V +, and the input signal V + is input to a non-inverting input terminal (+ input terminal) of the amplifier circuit 1. A reference signal V- is supplied to the other input terminal T1B of the comparator 100, and the reference signal V-
Are input to the inverted input terminal (− side input terminal). The amplifier circuit 1 includes a differential amplifier having a load transistor. The feedback circuit 2 forms a positive feedback circuit. A non-inverting input terminal of the feedback circuit 2 is supplied with a positive-phase output signal io + from one output terminal of the amplifier circuit 1, and an inverting input terminal is supplied with a negative-phase output signal io− from the other output terminal of the amplifier circuit 1. Is supplied. A non-inverting input terminal of the output buffer circuit 3 is supplied with a positive-phase output signal vo + from one output terminal of the feedback circuit 2, and an inverting input terminal is supplied with a negative-phase output signal from the other output terminal of the feedback circuit 2. vo- is supplied. The output buffer circuit 3 supplies an output signal Vout corresponding to a difference voltage between the signal vo + and the signal vo− to the output terminal T1Z of the comparator 100. As an input transistor of the comparator 100, an N-channel MOS transistor (N-type MOS transistor) which is an example of an N-channel insulated gate field effect transistor is used.
Although an S transistor is often used, a P-channel MOS transistor (P-type MOS transistor) which is an example of a P-channel insulated gate field effect transistor may be used.

FIG. 2 shows a comparator in which an input transistor is constituted by a differential pair of P-type MOS transistors.
FIG. 3 is a circuit diagram showing an example of the embodiment. In this comparator 200, P-type MOS transistors 21P to 26P and N-type M
OS transistors 21N to 24N and DC constant current source 25
C. P-type MOS transistors 21P, 22P
Is an input transistor. The power supply terminal T20V is a supply terminal for the power supply voltage Vdd, and the ground terminal T20G is grounded to a ground voltage (ground potential) GND. The input signal Tin is supplied to the input terminal T20A,
Reference signal Sref for comparison is supplied to 20B, and output signal Sout is output to output terminal T20Z. The input terminal T20A is a positive input terminal, and the input terminal T20B is a negative input terminal.
Side input terminal. Nodes n1 to n3 are connected to a power supply terminal T
Connected to 20V. Node n5 is nodes n4, n
6, the node n7 is connected to the node n8, and the node n11 is connected to the node n12. Node n
14 to n17 are connected to the ground terminal T20G. In the comparator 200, even when the terminal voltage of the input terminal T20A is Vdd / 2, or when the terminal voltage of the input terminal T20A is equal to or higher than Vdd / 2 and is close to Vdd / 2, the input signal Sin and the reference signal Sref are used. Can be performed.

In the P-type MOS transistor 21P, the source is connected to the node n10, and the gate is connected to the input terminal T21.
a, and the drain is connected to the node n11. In the P-type MOS transistor 22P, the source is connected to the node n10, the gate is connected to the input terminal T22b, and the drain is connected to the node n13. In the P-type MOS transistor 23P, the source is connected to the node n1, the gate is connected to the node n5, and the drain is connected to the node n10. In the P-type MOS transistor 24P, the source is connected to the node n2, the gate is connected to the node n4, and the drain is connected to the node n7. In the P-type MOS transistor 25P, the source is connected to the node n3, the gate is connected to the node n4, and the drain is connected to the node n6. P type M
In the OS transistor 26P, the source is connected to the node n3, the gate is connected to the node n8, and the drain is connected to the node n9.

In the N-type MOS transistor 21N, the drain is connected to the node n11, and the gate is connected to the node n12.
, And the source is connected to the node n14.
In the N-type MOS transistor 22N, the drain is connected to the node n13, the gate is connected to the node n12,
The source is connected to the node n15. In the N-type MOS transistor 23N, the drain is connected to the node n7, the gate is connected to the node n13, and the source is connected to the node n16. N-type MOS transistor 24
At N, the drain is connected to node n9, the gate is connected to node n8, and the source is connected to node n17. A DC constant current source 25C for flowing a DC current from the node n6 to the node n17 is connected between the node n6 and the node n17.

The P-type MOS transistors 23P to 25P are field-effect transistors having the same characteristics and constitute a current mirror circuit.
25P is equal to the drive current of the constant current source 25C. During the comparison operation of the comparator 200,
P-type MOS transistor 23P corresponds to a constant current source that outputs a constant current to node n10. The N-type MOS transistors 21N and 22N are field effect transistors having the same characteristics and constitute a current mirror circuit. The P-type MOS transistors 21P and 22P of the differential pair have a two-input configuration, and a signal corresponding to the difference between the input signal Sin and the reference signal Sref is extracted from the node n13.

FIG. 3 is a circuit diagram showing an example of a comparator in which an input transistor is constituted by an N-type MOS transistor. This comparator 300 has P-type MOS transistors 31P to 34P and N-type MOS transistors 31N to 36N. The N-type MOS transistors 31N and 32N are input transistors. The power supply terminal T30V is a supply terminal for the power supply voltage Vdd, and the ground terminal T30G is grounded to a ground voltage (ground potential) GN.
D. The input signal Tin is supplied to the input terminal T30A, and the reference signal Sre for comparison is supplied to the input terminal T30B.
f is supplied, and an output signal Sout is output to the output terminal T30Z. The input terminal T30A is a positive input terminal,
The input terminal T30B is a negative input terminal. Node n31
To n34 are connected to a power supply terminal T30V. Node n35 is connected to node n36, node n37 is connected to node n38, and node n39 is connected to node n4.
0, n47. Nodes n41 to n43 are connected to ground terminal T30G.

In the P-type MOS transistor 31P, the source is connected to the node n31, the gate is connected to the node n35, and the drain is connected to the node n36.
In the P-type MOS transistor 32P, the source is the node n.
32, the gate is connected to the node n35, and the drain is connected to the node n44. In the P-type MOS transistor 33P, the source is connected to the node n33, the gate is connected to the node n44, and the drain is connected to the node n37. P-type MOS transistor 3
In 4P, the source is connected to node n34, the gate is connected to node n38, and the drain is connected to node n45.

In the N-type MOS transistor 31N, the drain is connected to the node n36, and the gate is connected to the input terminal T3.
0A, and the source is connected to node n46. In the N-type MOS transistor 32N, the drain is connected to the node n44, and the gate is a reference signal Sre for comparison.
f is connected to the input terminal T30B, and the source is the node n4
6 is connected. In the N-type MOS transistor 33N, the drain is connected to the node n46, the gate is connected to the node n47, and the source is connected to the node n41. In the N-type MOS transistor 34N, the drain is connected to the node n37, the gate is connected to the node n40, and the source is connected to the node n42. In the N-type MOS transistor 35N, the drain is the node n3
9, the gate is connected to the node n40, and the source is connected to the node n43. In the N-type MOS transistor 36N, the drain is connected to the node n45, the gate is connected to the node n38, and the source is connected to the node n43. Node n34 and Node n39
Is connected to a DC constant current source 35C for flowing a DC current from the node n34 to the node n39.

The P-type MOS transistors 31P and 32P are field effect transistors having the same characteristics, and constitute a current mirror circuit. N-type MOS transistor 33N
To 35N are field-effect transistors having the same characteristics and constitute a current mirror circuit. The drain currents of the N-type MOS transistors 33N to 35N are equal to the drain current of the P-type MOS transistor 33P.
Equivalent to 5C drive current. During the comparison operation of comparator 300, N-type MOS transistor 33N corresponds to a constant current source that inputs a constant current from node n46.
The N-type MOS transistors 31N and 32N of the differential pair have a two-input configuration, and a signal corresponding to the difference between the input signal Sin and the reference signal Sref is extracted from the node n44.

[0011]

In the comparator 300, in order for the N-type MOS transistors 33N to 35N to operate in the saturation region, the following equation (1) must be satisfied under the condition of Vgsn> Vthn. . Vdsn> Vgsn-Vthn (1) Here, Vdsn is the drain-source voltage of the N-type MOS transistor 33N, Vgsn is the gate-source voltage (gate voltage), and Vthn is the threshold voltage (threshold). Voltage). Similarly, the N-type MOS transistors 34N and 35N need to satisfy the above expression (1).

For example, when the power supply voltage Vdd of the comparator decreases, the terminal voltages of the input terminals T30A and T30B are restricted to satisfy the above equation (1). In order to satisfy the above equation (1), the input terminals T30A, T30
The terminal voltage of B needs to be equal to or higher than the value of Vdsn + Vthn1. Here, Vthn1 is a threshold voltage of the N-type MOS transistor 31N. Thus, the input signal Sin
Has a lower limit in order to operate the N-type MOS transistor 33N corresponding to the current source in a saturated state, and thus to cause the comparator 300 to perform a comparison operation.
A signal voltage near the ground potential GND is not preferable as a signal voltage of the input signal Sin.

On the other hand, the P-type M of the comparator 200 shown in FIG.
The OS transistors 23P and 25P correspond to the N-type MOS transistors 33N and 35N of the comparator 300 in FIG. 3, respectively. Similarly to the comparator 300 of FIG.
In the comparator 200 shown in FIG. 2, the signal voltage of the input signal Sin is used to operate the P-type MOS transistor 23P corresponding to the current source in a saturated state.
00 has an upper limit for the comparison operation, and the power supply voltage V
The signal voltage near dd is not preferable as the signal voltage of the input signal Sin. An object of the present invention is to compare with a comparison device including a single comparator (comparator) as shown in FIGS.
An object of the present invention is to provide a comparison device capable of widening a range of an input signal voltage that can perform a comparison operation.

[0014]

A comparison device according to the present invention assigns a divided range obtained by dividing a voltage range that can be taken by an input signal to a plurality of output terminals in advance, and assigns the input signal to the output corresponding to the signal voltage. A switching circuit for supplying a reference signal to each of the plurality of output terminals; a plurality of comparison circuits respectively connected to the plurality of output terminals for comparing the input signal from the output terminal with the reference signal; Vessels,
A selection circuit that selects an output signal of the comparator to which the input signal is supplied from the switching circuit among output signals of the plurality of comparators, wherein the plurality of comparators The sum of the input voltage ranges that can be compared is
Each of the comparators is larger than the input voltage range in which comparison operation is possible.

In the comparison device according to the present invention, preferably, the comparator supplied with the input signal from the switching circuit among the plurality of comparators includes the reference signal supplied to the comparator. And the input signal is compared with the reference signal supplied to the comparator among the plurality of comparators other than the comparator to which the input signal is supplied from the switching circuit. The comparison operation between the signal and the input signal is stopped.

In the comparison device according to the present invention, preferably, the plurality of comparators include first and second comparators, and the switching circuit includes first and second insulated gate field effect transistors. Wherein the first and second insulated gate field effect transistors are controlled in accordance with the input signal such that one is in an on state and the other is in an off state. The input signal is supplied from an input terminal of the comparison device via the first insulated gate field effect transistor, and the second comparator is supplied with the input signal via the second insulated gate field effect transistor. The input signal is supplied from an input terminal of the comparison device.

In the comparison device of the present invention, more preferably, the input transistor of the first comparator is constituted by a differential pair of P-channel insulated gate field effect transistors, and the first comparator has a low level. The input signal having a constant level is supplied between a connection point of a P-channel insulated gate field effect transistor of the differential pair and a supply terminal of a power supply voltage, and a first constant current for outputting a constant current to the connection point is provided. A current source is connected, the input transistor of the second comparator is constituted by a differential pair of N-channel insulated gate field effect transistors, and the second comparator is supplied with the input signal at a high level. A second constant current source that inputs a constant current from the connection point is connected between the connection point of the N-channel insulated gate field effect transistor of the differential pair and the ground terminal.

The comparison device has a switching circuit, a plurality of comparators, and a selection circuit. The switching circuit has a plurality of output terminals. The switching circuit previously assigns a divided range obtained by dividing a voltage range that can be taken by an input signal to a plurality of output terminals, and supplies the input signal to the output terminal corresponding to the signal voltage. Each of the plurality of comparators is supplied with a reference signal for comparison. The plurality of comparators are respectively connected to correspond to the plurality of output terminals of the switching circuit. The plurality of comparators compare the input signal from the output terminal with the reference signal. The selection circuit selects an output signal of the comparator to which the input signal is supplied from the switching circuit among output signals of the plurality of comparators. The input signal is supplied to a comparator that compares the input signal with a reference signal according to the signal voltage, and an output signal of the comparator is selected by a selection circuit. The sum of the input voltage ranges in which the plurality of comparators can perform the comparison operation is larger than the input voltage range in which the individual comparators can perform the comparison operation. An input voltage range can be obtained.

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 4 is a circuit diagram of an example of the comparison device according to the present invention.

The comparison device 400 includes a signal input terminal T40A to which an input signal Sin is supplied and a divided range obtained by dividing a voltage range that the input signal Sin can take.
1A, 61B, and supplies the input signal Sin to the output terminal corresponding to the signal voltage.
1 and a plurality of comparators (comparators) CMP1 and CMP2 respectively supplied with reference signals Sref1 and Sref2 for comparison and connected to the plurality of output terminals 61A and 61B, respectively. Comparator CMP
1, a selection circuit 66 for selecting an output signal of the comparator to which the input signal Sin is supplied from the switching circuit 61 among output signals Vc1 and Vc2 of the CMP2, and a selection circuit 6
Signal output terminal T40Z to which the output signal Sout of No. 6 is supplied.
And The first comparator CMP1 compares the low-level input signal Sin with the reference signal Sref1, and the second comparator CMP2 compares the high-level input signal Sin with the reference signal Sref2.

The switching circuit 61 includes an inverter 60 for generating an inverted signal / Sin of the input signal Sin, and an inverted signal / Sin.
N-type MOS transistor 61 which is an example of a first insulated gate field effect transistor using in as a gate control signal
N and a P-type MO which is an example of a second insulated gate type field effect transistor using an inverted signal / Sin as a gate control signal.
And an S transistor 62P. In the first comparator CMP1, the input transistor is formed of a P-type MOS transistor which is an example of a P-channel insulated gate field effect transistor, and a non-inverting input terminal (+ side input terminal) is a signal via an N-type MOS transistor 61N. Input terminal T
40A, and a first reference signal Sref1 is supplied to an inverting input terminal (− side input terminal). Input signal Sin
Ranges from ground voltage GND to power supply voltage V
The range is up to dd. An output terminal 61A of the switching circuit 61 is assigned in advance a low-level input signal voltage among signal voltages that can be taken by the input signal Sin. Switching circuit 6
A high-level input signal voltage among signal voltages that can be taken by the input signal Sin is assigned to the first output terminal 61B in advance.

The comparison device 400 includes a P-type MOS transistor 61P as an example of a third insulated gate field effect transistor and an N-type MOS transistor 62N as an example of a fourth insulated gate field effect transistor. Have. The P-type MOS transistor 61P outputs the inverted signal /
Sin as a gate control signal, and a first comparator CMP
1 non-inverting input terminal (+ input terminal) and power supply terminal T
40V. Second comparator C
MP2 has an N-type MOS transistor whose input transistor is an example of an N-channel insulated gate field effect transistor, and has a non-inverting input terminal (+ side input terminal) of P
The signal input terminal T4 via the type MOS transistor 62P
0A, and a second reference signal Sref2 is supplied to the inverting input terminal (− side input terminal). The N-type MOS transistor 62N uses the inverted signal / Sin as a gate control signal, and uses the non-inverted input terminal (+
Side input terminal) and the ground terminal T40G.

The comparison device 400 includes a constant voltage source 61
V, 62V. The constant voltage source 61V generates a first reference signal Sref1 and supplies the first reference signal Sref1 to an inverting input terminal (− side input terminal) of the comparator CMP1. The constant voltage source 62V generates a second reference signal Sref2 and supplies the second reference signal Sref2 to the inverting input terminal (− side input terminal) of the comparator CMP2. Each signal voltage of the first reference signal Sref1 and the second reference signal Sref2 is a constant DC voltage that is higher than the ground voltage (ground potential) GND and lower than the power supply voltage Vdd. First reference signal Sref1
And the second reference signal Sref2 may have the same value. First
The second power supply voltage Vdd and the ground voltage (ground potential) GND are supplied to the second comparators CMP1 and CMP2.

The selection circuit 66 includes a first comparator CM
A first transmission gate 66 for receiving the output signal Vc1 of P1
A, and a second transmission gate 66B for receiving the output signal Vc2 of the second comparator CMP2. The first transmission gate 66A and the second transmission gate 66B are connected to the input signal Sin such that one is on and the other is off.
It is controlled according to. When the input signal Sin is at a low level, that is, when the inverted signal / Sin is at a high level (H level)
In the case of, the first transmission gate 66A is in the ON state,
The second transmission gate 66B is off, and the output signal V
c1 is selected by the selection circuit 66 and output to the signal output terminal T40Z as an output signal Sout. When the input signal Sin is at a high level, that is, when the inverted signal / Sin is at a low level (L level), the first transmission gate 66A is off, the second transmission gate 66B is on, and the output is off. The signal Vc2 is selected by the selection circuit 66 and output to the signal output terminal T40Z as the output signal Sout.

In the selection circuit 66, the first transmission gate 66A is a P-channel insulated gate type field effect transistor which uses the input signal Sin as a gate control signal.
And a N-type MOS transistor 64N which is an example of an N-channel insulated-gate field-effect transistor using the inverted signal / Sin as a gate control signal. In the selection circuit 66, the second transmission gate 6
6B shows an N-type MOS transistor 65N which is an example of an N-channel insulated gate field effect transistor using the input signal Sin as a gate control signal, and a P-channel insulated gate field effect transistor using the inverted signal / Sin as a gate control signal. And a P-type MOS transistor 65P as an example.

The input transistor of the first comparator CMP1 is composed of a differential pair of P-type MOS transistors, and is connected between the connection point of the differential pair of P-type MOS transistors and the power supply terminal T40V. A constant current source that outputs a constant current is connected to the connection point. For example, a P-type MO that is an example of a P-channel insulated gate field-effect transistor that outputs a constant drain current to the connection point
The S transistor is connected. The input transistor of the second comparator CMP2 is composed of a differential pair of N-type MOS transistors, and a connection point between the N-type MOS transistor of the differential pair and the ground terminal T40G is connected from the connection point. A constant current source for inputting a constant current is connected, and for example, an N-type MOS transistor which is an example of an N-channel insulated gate field effect transistor for inputting a constant drain current from the connection point is connected. First and second comparators CMP1 and CMP2
The input transistors are each composed of a P-type MOS transistor and an N-type MOS transistor, and the sum of the input voltage ranges in which the plurality of comparators CMP1 and CMP2 can perform the comparison operation is the sum of the individual comparators CM.
P1 and CMP2 are larger than the input voltage range in which the comparison operation can be performed. The inverter 60 includes a P-type MOS transistor 60 which is an example of a P-channel insulated gate field effect transistor between a power supply terminal T40A and a ground terminal T40G.
It is composed of a CMOS inverter in which P and an N-type MOS transistor 60N, which is an example of an N-channel insulated gate field effect transistor, are complementarily connected.

Next, the circuit configuration of the comparison device 400 will be described in detail. The power supply terminal T40V is a supply terminal for the power supply voltage Vdd. The power supply terminal T40V has a node n69.
Is connected. The ground terminal T40G is grounded to the ground potential GND. Nodes n74 and n75 are connected to the ground terminal T40G. Signal input terminal T4
The node n61 is connected to 0A. The node n67 is connected to the signal output terminal T40Z. Node n61 is connected to nodes n62, n68, and n73. Node n63 includes nodes n64, n65, and n6.
6 is connected. The node n67 is a node n72,
n78.

The CMOS inverter 60 has a P-type MOS transistor 60P and an N-type MOS transistor 60N. In the P-type MOS transistor 60P, the source is connected to the node n69, the gate is connected to the node n62, and the drain is connected to the node n63. N type M
In the OS transistor 60N, the source is connected to the node n74, the gate is connected to the node n62, and the drain is connected to the node n63.

In the N-type MOS transistor 61N, the source is connected to the node n70 via the output terminal 61A.
The gate is connected to the node 64, and the drain is the node n6.
8 is connected. In the P-type MOS transistor 61P, the source is connected to the node n69, the gate is connected to the node 65, and the drain is connected to the node n70. The node n70 is connected to the non-inverting input terminal (+ input terminal) of the first comparator CMP1. P
In the type MOS transistor 62P, the source is the node n7.
3, the gate is connected to the node 64, and the drain is connected to the node n76 via the output terminal 61B. In the N-type MOS transistor 62N, the source is connected to the node n75, the gate is connected to the node 65, and the drain is connected to the node n76. The node n76 is connected to a non-inverting input terminal (+ input terminal) of the second comparator CMP2.

The first CMOS transmission gate 66A includes a P-type MOS transistor 64P and an N-type MOS transistor 6
4N. In P-type MOS transistor 64P, the source is connected to node n71, and the gate is connected to node n68.
, And the drain is connected to the node n72. In the N-type MOS transistor 64N, the source is connected to the node n72, the gate is connected to the node n66, and the drain is connected to the node n71. The second CMOS transmission gate 66B has a P-type MOS transistor 65P and an N-type MOS transistor 65N. In the P-type MOS transistor 65P, the source is the node n77.
, The gate is connected to the node n66, and the drain is connected to the node n78. In the N-type MOS transistor 65N, the source is connected to the node n78,
The gate is connected to the node n73, and the drain is
77.

The first comparator CMP1 has a configuration in which the input transistor is a P-type MOS transistor as shown in FIG. The second comparator CMP2 has a configuration in which the input transistor is an N-type MOS transistor as shown in FIG. The first and second comparators CMP1 and CMP2 input reference signals Sref1 and Sref2 corresponding to respective circuit configurations and circuit functions to inverted input terminals (− side input terminals), and input signals S to be compared.
Input in to the non-inverting input terminal (+ side input terminal).

The input signal Sin is supplied to the CMOS inverter 60
The signal is converted into an inverted signal / Sin and output. The inverted signal / Sin is input as a gate control signal to the gate of a P-type MOS transistor 61P for pulling up the + input terminal (non-inverted input terminal) of the first comparator CMP1. The inverted signal / Sin is input as a gate control signal to the gate of an N-type MOS transistor 62N for pulling down the + input terminal (non-inverted input terminal) of the second comparator CMP2. The inverted signal / Sin is obtained by converting the input signal Sin to the first comparator C
The gate control signal is input to the gate of an N-type MOS transistor 61N that determines whether to propagate the signal to MP1. The inverted signal / Sin is input as a gate control signal to the gate of a P-type MOS transistor 62P that determines whether to propagate the input signal Sin to the second comparator CMP2.

First and second comparators CMP1,
The output signals Vc1 and Vc2 of the CMP2 are selected by the selection circuit 66 according to the input signal Sin. In the selection circuit 66, one of the first and second transmission gates 66A and 66B is turned on (on) and the other is turned off (off), so that one of the output signals Vc1 and Vc2 is turned on. It is supplied to the signal output terminal T40Z.

When the input signal Sin is at L level, the signal input terminal T40A and the node n connected to this terminal T40A
61, n62, n68 and n73 are at the L level. In addition, the nodes n63 to n66 attain the H level according to the output signal of the CMOS inverter 60. Then, N-type MOS
The transistors 61N and 62N are turned on, and the P-type M
The OS transistors 61P and 62P are turned off.

Since the N-type MOS transistor 61N is on, the input signal Sin is propagated to the node n70,
To the + input terminal (non-inverting input terminal) of the comparator CMP1. From the signal input terminal T40A to the node n
Since the N-type MOS transistor 61N is used to propagate the input signal Sin to 70, the signal loss due to the voltage drop can be suppressed for the L-level input signal Sin. Since the P-type MOS transistor 62P is off,
The input signal Sin is not propagated to the node n76 and is not supplied to the + input terminal (non-inverting input terminal) of the second comparator CMP2. Since the N-type MOS transistor 62N is on, the node n76 is pulled down to the ground potential G.
ND, the + input terminal of the second comparator CMP2 becomes the ground potential GND, and the second comparator CMP2
2 stops the comparison operation and does not perform the comparison operation. Thereby, the power consumption of the second comparator CMP2 can be reduced.

In the first comparator CMP1, the input signal Sin is input to the positive input terminal, and the first reference signal Sref1 is input to the negative input terminal (inverted input terminal).
The first comparator CMP1 outputs the output signal Vc1 obtained by the comparison operation to the node n71. The first CMOS transmission gate 66A is in a conductive state (ON state), the second CMOS transmission gate 66B is in a non-conductive state (OFF state), and an output signal is provided to a signal output terminal T40Z via nodes n72 and n67. Vc1 is supplied.

When the input signal Sin is at H level, the signal input terminal T40A and the node n connected to this terminal T40A
61, n62, n68, and n73 are at the H level. Also, the CMOS inverter 60 allows the nodes n63 to n
66 is at the L level. Then, the N-type MOS transistors 61N and 62N are turned off, and the P-type MOS transistors 61P and 62P are turned on.

Since the P-type MOS transistor 62P is on, the input signal Sin is propagated to the node n76,
Is supplied to the + input terminal (non-inverting input terminal) of the comparator CMP2. From the signal input terminal T40A to the node n
Since the P-type MOS transistor 62P is used to propagate the input signal Sin to the signal 76, the signal loss due to the voltage drop can be suppressed for the H-level input signal Sin. Since the N-type MOS transistor 61N is off,
The input signal Sin is not propagated to the node n70 and is not supplied to the + input terminal (non-inverting input terminal) of the first comparator CMP1. Since the P-type MOS transistor 61P is on, the node n70 is pulled up and the power supply voltage V
dd, the + input terminal of the first comparator CMP1 becomes the power supply voltage Vdd, and the first comparator CMP1 stops the comparison operation and does not perform the comparison operation. This allows
The power consumption of the first comparator CMP1 can be reduced.

In the second comparator CMP2, the input signal Sin is input to the + input terminal, and the second reference signal Sref2 is input to the − input terminal (inverted input terminal).
The second comparator CMP2 outputs the output signal Vc2 obtained by the comparison operation to the node n77. The second CMOS transmission gate 66B is in a conductive state (ON state), the first CMOS transmission gate 66A is in a non-conductive state (OFF state), and an output signal is connected to a signal output terminal T40Z via nodes n78 and n67. Vc2 will be supplied.

Instead of the N-type MOS transistor 61N or the N-type MOS transistor 62N, an analog switch (CMOS transmission gate) 80 as shown in FIG. 5 may be used. This analog switch 80 includes an inverter 81
And a P-type MOS transistor 80P and an N-type MOS transistor 80N. When an H level control signal is input to the control terminal T80B, a MOS (Metal Oxide Semi
conductor) The transistors 80P and 80N are turned on, and the signal input to the input terminal T80A is output to the output terminal T
80Z. When an L-level control signal is input to control terminal T80B, MOS transistors 80P, 8P
0N is turned off, and the signal input to the input terminal T80A is not supplied to the output terminal T80Z. Inverter 8
1 may be a CMOS inverter.

Instead of the P-type MOS transistor 61P or the P-type MOS transistor 62P, an analog switch (CMOS transmission gate) 90 as shown in FIG. 6 may be used. The analog switch 90 includes an inverter 91
And a P-type MOS transistor 90P and an N-type MOS transistor 90N. When an L-level control signal is input to the control terminal T90B, the MOS transistor 90
P and 90N are turned on, and the signal input to the input terminal T90A is supplied to the output terminal T90Z. When an H-level control signal is input to the control terminal T90B, the MOS
The transistors 90P and 90N are turned off, and the signal input to the input terminal T90A is not supplied to the output terminal T90Z. Inverter 91 may be a CMOS inverter.

FIG. 7 is an explanatory diagram showing the relationship of power supply voltage allocation in the input stages of the first and second comparators. In the first comparator CMP1, the power supply voltage Vdd
Is the gate-source voltage Vgsp and the current source drop voltage V
It can be divided into satp and terminal voltage Vswp. The gate-source voltage Vgsp is a gate-source voltage of a differential pair of P-type MOS transistors that are input transistors. The voltage drop Vsatp of the current source is the P-type M of the differential pair.
This is a drop voltage of a P-type MOS transistor corresponding to a current source that outputs a constant drain current to a connection point of the OS transistor. The terminal voltage Vswp is a terminal voltage of the + input terminal (between the ground terminal). First comparator CMP1
Is supplied with a low-level input signal Sin.
≤Vswp <Vdd / 2, and the terminal voltage Vswp is Vdd / 2.
The case in the vicinity is shown. First comparator CM
At P1, Vswp = Vdd- (Vgsp + Vsatp), and the terminal voltage Vswp drops from the power supply voltage Vdd.
A low-level (L-level) signal is suitable as the input signal Sin input to the + input terminal of the first comparator CMP1. Further, in the first comparator CMP1, even when the terminal voltage Vswp is Vdd / 2, or when the terminal voltage Vswp is equal to or higher than Vdd / 2 and near Vdd / 2, the operation of comparing the input signal Sin with the reference signal Sref1 is performed. And the signal voltage of the low-level input signal Sin is included in the input voltage range in which the first comparator CMP1 can perform the comparison operation.

On the other hand, in the second comparator CMP2,
The power supply voltage Vdd is divided into a gate-source voltage Vgsn, a voltage drop Vsatn of the current source, and a terminal voltage Vswn. The gate-source voltage Vgsn is a gate-source voltage of an N-type MOS transistor of a differential pair which is an input transistor. The voltage drop Vsatn of the current source is a voltage drop of an N-type MOS transistor corresponding to a current source that inputs a constant drain current from a connection point of the N-type MOS transistors of the differential pair. The terminal voltage Vswn is a terminal voltage of the + input terminal (between the ground terminal). Since the high-level input signal Sin is supplied to the second comparator CMP2, Vdd / 2 <Vswn ≦ Vdd, and the terminal voltage Vswn
Is near Vdd / 2. In the second comparator CMP2, Vswn = Vgsn + Vsatn, and the terminal voltage Vswn becomes higher than the ground voltage GND.
A high-level (H-level) signal is suitable as the input signal Sin input to the + input terminal of the second comparator CMP2. Further, in the second comparator CMP2, even when the terminal voltage Vswn is Vdd / 2 or when the terminal voltage Vswn is equal to or lower than Vdd / 2 and is close to Vdd / 2, the comparison operation between the input signal Sin and the reference signal Sref2 is performed. Is performed, and the signal voltage of the high-level input signal Sin is included in the input voltage range in which the second comparator CMP2 can perform the comparison operation. As described above, in the voltage range (GND to Vdd) that the input voltage Sin can take, the sum of the input voltage ranges in which the plurality of comparators CMP1 and CMP2 can perform the comparison operation is the sum of the individual comparators CM.
P1 and CMP2 are larger than the input voltage range in which the comparison operation can be performed.

In the comparator 400, an L-level input signal Sin is supplied to the + input terminal of the first comparator CMP1. The first comparator CMP1 uses a differential pair of P-type MOS transistors as input transistors, and inputs a lower input signal voltage as compared with the case where a differential pair of N-type MOS transistors is used as input transistors. (Comparison operation). In the comparison device 400, the second comparator CM
An H-level input signal Sin is supplied to the + input terminal of P2. The second comparator CMP2 uses a differential pair of N-type MOS transistors as input transistors.
Compared to a case where a P-type MOS transistor of a differential pair is used as an input transistor, a higher input signal voltage can be input to perform comparison (comparison operation). As described above, in the comparison device 400, the first and second comparators CMP1 and CMP2 are selected and operated according to the level of the input signal Sin, so that the comparison is performed using only one comparator. As compared with the case, the input signal Sin in a wider voltage range can be input and compared, and the dynamic range of the input voltage can be substantially widened.

The first and second comparators CM
The input signal Sin is propagated to one of the comparators P1 and CMP2, and the input signal Sin is transmitted to the other comparator.
Is not propagated. The + input terminal of the other comparator is pulled up or pulled down, and the comparison operation of the other comparator is stopped.
The output signal of the one comparator is selected by the selection circuit 66 according to the inverted signal, and is output to the signal output terminal T40Z without colliding with the output signal of the other comparator. The operation of selecting the comparator according to the voltage level of the input signal Sin is performed using the inverted signal / Sin, and the operation of the selection circuit 66 selecting the output of the comparator is performed using the input signal Sin and the inverted signal / Sin. Has correlation.

A comparator 200 shown in FIG. 2 may be used as the first comparator CMP1. As the first comparator CMP1, a comparator having a configuration in which the P-type MOS transistor and the N-type MOS transistor of the comparator 300 shown in FIG. 3 are replaced with each other and the current driving direction of the current source 35C is reversed may be used. Second
The comparator 300 shown in FIG. 3 may be used as the comparator CMP2. Second comparator CMP
2 is a P-type MO of the comparator 200 shown in FIG.
A comparator having a configuration in which the S transistor and the N-type MOS transistor are replaced with each other and the current driving direction of the current source 25C is reversed may be used. In the comparison device 400,
It is possible to input an input signal Sin from the vicinity of the ground potential GND to the vicinity of the power supply voltage Vdd and compare it with a reference signal. The above embodiment is an example of the present invention, and the present invention is not limited to the above embodiment.

[0047]

According to the comparison device of the present invention, a plurality of comparators (comparators) are used for comparing the input signal with the reference signal. Range can be expanded.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an example of a differential input type comparator.

FIG. 2 is a circuit diagram showing an example of a comparator in which an input transistor is constituted by a differential pair of P-type MOS transistors.

FIG. 3 is a circuit diagram showing an example of a comparator in which an input transistor is constituted by a differential pair of N-type MOS transistors.

FIG. 4 is a circuit diagram showing an example of a comparison device according to the present invention.

FIG. 5 is a circuit diagram showing an example of an analog switch that can be substituted for an N-type MOS transistor.

FIG. 6 is a circuit diagram showing an example of an analog switch that can be substituted for a P-type MOS transistor.

FIG. 7 is an explanatory diagram showing a relationship between allocation of power supply voltages in input stages of first and second comparators.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Amplification circuit, 2 ... Feedback circuit, 3 ... Output buffer circuit, 21P-26P, 31P-34P, 60P,
64P, 65P ... P-type MOS transistor, 21N-2
4N, 31N to 36N, 60N, 64N, 65N: N-type MOS transistor, 25C, 35C: constant current source, 60
... Inverter, 61V, 62V ... Constant voltage source, 61N ... First insulated gate field effect transistor (N-type MOS transistor), 61P ... Third insulated gate field effect transistor (P-type MOS transistor), 62N ... 4
Insulated gate field effect transistor (N-type MOS transistor), 62P... Second insulated gate field effect transistor (P-type MOS transistor), 66... Selection circuit, 66A... First transmission gate, 66B. Transmission gates, 80, 90 analog switches, 81, 91 inverters, 100, 200, 300 comparators (comparators), 400 comparators, CMP1 first comparator (first comparator), CMP2 ... 2, a comparator (second comparator), GND... Ground voltage (ground potential),
Sin: input signal, Sout: output signal, T1A, T1B,
T20A, T20B, T30A, T30B ... input terminals,
T1Z, T20Z, T30Z ... output terminals, T20G, T
30G, T40G: Ground terminal, T20V, T30V, T
40V: power supply voltage supply terminal (power supply terminal), T40
A: signal input terminal, T40Z: signal output terminal, Vdd: power supply voltage.

Claims (23)

[Claims] A switching circuit for previously assigning a divided range obtained by dividing a voltage range that can be taken by an input signal to a plurality of output terminals, and supplying the input signal to the output terminal corresponding to the signal voltage; A plurality of comparators respectively supplied and connected corresponding to the plurality of output terminals, for comparing the input signal from the output terminal with the reference signal, and outputs of the plurality of comparators A selection circuit that selects an output signal of the comparator to which the input signal is supplied from the switching circuit among signals, wherein the plurality of comparators have an input voltage range in which comparison operation is possible. A comparison device in which the sum is greater than an input voltage range in which each of the comparators can perform a comparison operation. 2. The comparator, to which the input signal is supplied from the switching circuit among the plurality of comparators, performs a comparison operation between the reference signal supplied to the comparator and the input signal. The comparator other than the comparator to which the input signal is supplied from the switching circuit among the plurality of comparators performs a comparison operation between the reference signal and the input signal supplied to the comparator. 2. The comparison device according to claim 1, wherein the comparison is stopped. 3. The plurality of comparators include first and second comparators, wherein the switching circuit has first and second insulated gate type field effect transistors, The second insulated gate field effect transistor is controlled in accordance with the input signal such that one is turned on and the other is turned off, and the first comparator includes the first insulated gate field effect transistor. The input signal is supplied from an input terminal of the comparison device via an effect transistor, and the input signal is supplied to the second comparator from an input terminal of the comparison device via the second insulated gate field effect transistor. 2. The comparison device according to claim 1, wherein a signal is provided. 4. The selection circuit includes: a first transmission gate for receiving an output signal of the first comparator; and a second transmission gate for receiving an output signal of the second comparator. The comparison device according to claim 3, wherein the first transmission gate and the second transmission gate are controlled in accordance with the input signal such that one of the first transmission gate and the second transmission gate is turned on and the other is turned off. 5. The first comparator, wherein the input transistor comprises a P-channel insulated gate field effect transistor, and a non-inverting input terminal has a low level through the first insulated gate field effect transistor. The input signal is supplied, a reference signal is supplied to an inverting input terminal, the second comparator has an input transistor formed of an N-channel insulated gate field effect transistor, and the second comparator has a non-inverting input terminal. 4. The comparison device according to claim 3, wherein the input signal at a high level is supplied via the insulated gate field effect transistor, and a reference signal is supplied to an inverting input terminal. 6. An input transistor of the first comparator is constituted by a differential pair of P-channel insulated gate field effect transistors, and the first comparator is supplied with the low-level input signal. A first constant current source that outputs a constant current to the connection point is connected between the connection point of the P-channel insulated gate field effect transistor of the differential pair and the supply terminal of the power supply voltage. The input transistor of the second comparator is composed of a differential pair of N-channel insulated gate field effect transistors, and the second comparator is supplied with the input signal at a high level. 4. The comparison device according to claim 3, wherein a second constant current source that inputs a constant current from the connection point is connected between the connection point of the gate type field effect transistor and the ground terminal. 7. An input transistor of the first comparator is constituted by a differential pair of P-channel insulated gate field effect transistors, and the first comparator is supplied with the low-level input signal. A P-channel insulated-gate field-effect transistor that outputs a constant drain current is connected to the connection point between the connection point of the P-channel insulated-gate field-effect transistor of the differential pair and the supply voltage supply terminal. Wherein the input transistor of the second comparator is constituted by a differential pair of N-channel insulated gate field effect transistors; the second comparator is supplied with the input signal at a high level; Between the connection point of the N-channel insulated-gate field-effect transistor and the ground terminal, a constant drain current is input from the connection point. Comparison apparatus according to claim 3, wherein the effect transistors are connected. 8. A third terminal controlled in accordance with the input signal between a connection point between the first insulated gate field effect transistor and the first comparator and a power supply voltage supply terminal.
The third insulated gate field effect transistor is turned off when the input signal is supplied to the first comparator, and the third insulated gate field effect transistor is turned off. 4. The comparison device according to claim 3, wherein when the input signal is not supplied to the comparator, the comparator is turned on and the first comparator is supplied with the power supply voltage instead of the input signal. 9. The switching circuit has an inverter for generating an inverted signal of the input signal, and the first insulated gate field effect transistor is an N-channel insulated gate type transistor using the inverted signal as a gate control signal. 9. The comparison device according to claim 8, wherein the comparison device is a field-effect transistor, and wherein the second and third insulated-gate field-effect transistors are P-channel insulated-gate field-effect transistors that use the inverted signal as a gate control signal. 10. The inverter according to claim 1, wherein a P-channel insulated gate field-effect transistor and an N-channel insulated gate field-effect transistor are complementarily connected between a power supply voltage supply terminal and a ground terminal. 9. The comparison device according to 9. 11. A fourth insulated gate controlled according to the input signal between a connection point between the second insulated gate field effect transistor and the second comparator and a ground terminal. A second field-effect transistor is connected, and the fourth insulated gate field-effect transistor is turned off when the input signal is supplied to the second comparator. 4. The comparison device according to claim 3, wherein when the input signal is not supplied, the second comparator is turned on and a ground voltage is supplied to the second comparator instead of the input signal. 12. The switching circuit has an inverter for generating an inverted signal of the input signal, and the first and fourth insulated gate field effect transistors use the inverted signal as a gate control signal. The comparison device according to claim 11, wherein the comparison device is an insulated gate type field effect transistor, and the second insulated gate type field effect transistor is a P-channel insulated gate type field effect transistor using the inverted signal as a gate control signal. 13. The inverter according to claim 1, wherein a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor are complementarily connected between a power supply voltage supply terminal and a ground terminal. 13. The comparison device according to 12. 14. A third terminal controlled according to the input signal between a connection point between the first insulated gate field effect transistor and the first comparator and a supply terminal of a power supply voltage. The third insulated gate field effect transistor is turned off when the input signal is supplied to the first comparator, and the third insulated gate field effect transistor is turned off. When the input signal is not supplied to the comparator, the comparator is turned on, and a power supply voltage is supplied to the first comparator instead of the input signal. The second insulated gate field effect transistor and the second A fourth insulated gate field effect transistor controlled in accordance with the input signal is connected between a connection point with the second comparator and the ground terminal; Effect transition The second comparator is turned off when the input signal is supplied to the second comparator, and is turned on when the input signal is not supplied to the second comparator. 4. The comparison device according to claim 3, wherein a ground voltage is supplied to the switch instead of the input signal. 15. The switching circuit has an inverter that generates an inverted signal of the input signal, and the first and fourth insulated gate field effect transistors use the inverted signal as a gate control signal for an N-channel. The comparison device according to claim 14, wherein the comparison device is an insulated gate type field effect transistor, and wherein the second and third insulated gate type field effect transistors are P-channel insulated gate type field effect transistors using the inverted signal as a gate control signal. . 16. The inverter according to claim 1, wherein a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor are complementarily connected between a power supply voltage supply terminal and a ground terminal. 15. The comparison device according to 15. 17. The switching circuit has an inverter that generates an inverted signal of the input signal, and the first insulated gate field effect transistor has an N-channel insulated gate type that uses the inverted signal as a gate control signal. 4. The comparison device according to claim 3, wherein the comparison device is a field effect transistor, and wherein the second insulated gate type field effect transistor is a P-channel insulated gate type field effect transistor using the inverted signal as a gate control signal. 5. 18. The inverter according to claim 1, wherein a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor are complementarily connected between a power supply voltage supply terminal and a ground terminal. 18. The comparison device according to 17. 19. The switching circuit has an inverter that generates an inverted signal of the input signal, and the first insulated gate field effect transistor has an N-channel insulated gate type that uses the inverted signal as a gate control signal. A field effect transistor, wherein the second insulated gate type field effect transistor is a P-channel insulated gate type field effect transistor using the inverted signal as a gate control signal, and wherein the first transmission gate transmits the inverted signal. An N-channel insulated-gate field-effect transistor serving as a gate control signal; and a P-channel insulated-gate field-effect transistor using the input signal as a gate control signal. P-channel insulated-gate field-effect transistor having a gate control signal of: Comparison device according to claim 4 having an N-channel insulated gate field effect transistor to control signals. 20. The inverter according to claim 20, wherein a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor are complementarily connected between a power supply voltage supply terminal and a ground terminal. 20. The comparison device according to 19. 21. The first transmission gate includes a P-channel insulated gate field effect transistor that uses the input signal as a gate control signal, and the second transmission gate outputs the input signal as a gate control signal. 5. The comparison device according to claim 4, further comprising an N-channel insulated gate field effect transistor. 22. The comparison device according to claim 1, wherein a voltage range that can be taken by the input signal is a range from a ground voltage to a power supply voltage. 23. The comparison device according to claim 1, wherein the divided range assigned to each of the output terminals is included in an input voltage range in which the comparator connected to the output terminal can perform a comparison operation.