JP2000115259A - Input correction circuit for cmos circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a CMOS circuit from getting a fault when differential signals are in-phase. SOLUTION: The input correction circuit is provided with a 1st differential amplifier circuit 2, an input state detection circuit 3a that provides an output of a detection signal when detecting digital signals IN, INB are in the same state, and an output confirmation circuit 4a that provides an output of a signal OUT based on an output of the 1st differential amplifier circuit 2 when the circuit 4a receives no detection signal from the circuit 3a or provides an output of a signal OUT denoting any state of an output signal S2 of the 1st differential amplifier circuit 2 when the circuit 4a receives the detection signal from the circuit 3a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit for receiving a differential signal and outputting the signal to a CMOS circuit, and more particularly to a receiving circuit for receiving a voltage signal between an H state and an L state when an in-phase signal is input. The present invention relates to an input correction circuit for a CMOS circuit for preventing output to a CMOS circuit.

[0002]

2. Description of the Related Art A differential signal refers to two digital signals having phases opposite to each other, that is, a signal comprising a non-inverted signal and an inverted signal. Conventionally, a differential amplifier circuit has been used as the differential signal receiving circuit. The differential amplifier circuit outputs a signal based on a potential difference between a non-inverted signal and an inverted signal, which are input signals. By taking the potential difference between the two signals by the differential amplifier circuit, noise on both of the two signals is canceled and removed. For this reason, digital communication using differential signals has a feature of being resistant to noise.

[0003]

Here, a problem that occurs when a CMOS circuit is connected to the output side of the differential amplifier circuit will be described. FIG. 10 shows the differential amplifier circuit and C
FIG. 3 is a block diagram illustrating a connection relationship with a MOS circuit. 11A and 11B are time charts showing the operation of the differential amplifier circuit 102. FIG. 11A shows a non-inverted signal IN, FIG. 11B shows an inverted signal INB, and FIG. 11C shows an output signal S102 of the differential amplifier circuit 102. Are respectively shown.

The periods T1, T2, T4, T in FIG.
In No. 6, the non-inverted signal IN and the inverted signal INB have opposite phases,
That is, the signals IN and INB are in different states. At this time, since the potential difference between the signals IN and INB is sufficiently large, the output signal S102 of the differential amplifier circuit 102 is
The circuit 105 recognizes the state of “H” or “L” as a determined signal. Here, the H state is logic “1”.
, And the L state is a state indicating logic “0”.

However, the non-inverted signal IN and the inverted signal I
When the noise is applied to only one of the NBs, the non-inverted signal IN and the inverted signal INB have the same phase as in the periods T3 and T5.
That is, the signals IN and INB may be in the same state. Similarly, the signals IN and INB are in the same state even in the initial state or at the time of disconnection. At this time, since the potential difference between the signals IN and INB is small, the output signal S1 of the differential amplifier circuit 102 is
02 is a voltage signal between the H state and the L state. CM
When an intermediate voltage between the H state and the L state is applied to the OS circuit 105, both the P-channel MOS transistor 151 and the N-channel MOS transistor 152 constituting the CMOS circuit 105 are simultaneously turned on, and the power supply VDD is supplied.
Through the power supply VSS. When a large through current flows through each of the transistors 151 and 152, the CM
There is a problem that the OS circuit 105 breaks down.

The present invention has been made to solve such a problem, and an object of the present invention is to prevent a failure of a CMOS circuit when differential signals have the same phase.

[0007]

In order to achieve the above object, the present invention has two input terminals and outputs a signal based on the potential difference between digital signals input to these input terminals. A first differential amplifier circuit, and an input state detection circuit that outputs a detection signal when at least each digital signal input to the first differential amplifier circuit is detected and each digital signal is detected to be in the same state And outputting a signal based on the output of the first differential amplifier circuit when the detection signal is not input and connected to the output side of each of the first differential amplifier circuit and the input state detection circuit, and inputting the detection signal. An output determination circuit for outputting a signal in any state of the output signal of the first differential amplifier circuit when the signal is output, and a CMOS circuit is connected to an output side of the output determination circuit. According to a second aspect of the present invention, in the first aspect of the present invention, the input state detection circuit further includes a reference signal whose voltage is set to a threshold level of each digital signal input to the first differential amplifier circuit. Means for comparing each of the input digital signals with the reference signal to detect that each digital signal is in the same state and outputting a detection signal. According to a third aspect of the present invention, in the second aspect of the present invention, the means included in the input state detection circuit is configured to output the signal obtained by amplifying a voltage difference between one of the digital signals and the reference signal. A dynamic amplifier circuit, a third differential amplifier circuit that outputs a signal obtained by amplifying a voltage difference between the other digital signal and the reference signal, and an output side of each of the second and third differential amplifier circuits; Second and third
And a logic circuit for outputting a detection signal when the output signals of the differential amplifier circuits are in the same state. According to a fourth aspect of the present invention, in the first aspect of the present invention, the output determining circuit is configured to supply a voltage in any state of the output signal of the first differential amplifier circuit. An input terminal is connected to the output side of the input state detection circuit, one output terminal is connected to the output side of the first differential amplifier circuit and the input side of the CMOS circuit, and the other output terminal is connected to the power supply and detected. And a transistor that conducts between two output terminals when a signal is input. The invention according to claim 5 is the invention according to any one of claims 1 to 3,
The output determination circuit includes means for continuing to output the signal output by the output determination circuit immediately before the detection signal is input. According to a sixth aspect of the present invention, in the fifth aspect, the means included in the output determination circuit is connected to a signal holding circuit for holding and outputting an input signal and an output side of the input state detection circuit. When the detection signal is not input, the first differential amplifier circuit and the signal holding circuit are connected. When the detection signal is input, the first differential amplifier circuit and the signal holding circuit are opened. And a switching circuit. The invention according to claim 7 is the invention according to claim 6, wherein the second switch circuit is a clocked inverter circuit having a clock terminal connected to the output side of the input state detection circuit. According to an eighth aspect of the present invention, in the sixth or seventh aspect, the signal holding circuit includes two inverter circuits forming a loop.

When two digital signals input to the first differential amplifier circuit are in the same state, the output signal of the first differential amplifier circuit is converted to one of digital signal states to form a CMOS circuit. , The intermediate voltage between the H state and the L state can be prevented from being applied to the CMOS circuit.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing the configuration of a first embodiment of an input correction circuit for a CMOS circuit according to the present invention. As shown in FIG. 1, the input correction circuit 1a for a CMOS circuit includes a first differential amplifier circuit 2, an input state detection circuit 3a, and an output determination circuit 4a.

[0010] The first differential amplifier circuit 2 has a non-inverting input terminal (+) and an inverting input terminal (-). The non-inverting input terminal (+) has a non-inverting signal IN which is one of the differential signals.
And the inverted signal INB, which is the other of the differential signals, is input to the inverted input terminal (−). The non-inverted signal I
N and the inverted signal INB are digital signals. The differential amplifier circuit 2 amplifies and outputs the potential difference between the non-inverted signal IN and the inverted signal INB. The non-inverted signal IN and the inverted signal INB input to the first differential amplifier circuit 2 are:
It is also input to the input state detection circuit 3a. The input state detection circuit 3a determines whether or not the signals IN and INB are in the same state, and outputs a detection signal when detecting that they are in the same state.

The output determination circuit 4a is connected to the output side of each of the first differential amplifier circuit 2 and the input state detection circuit 3a. The output side of the output determination circuit 4a has C
The MOS circuit 5 is connected. When the detection signal is not input from the input state detection circuit 3a, the output circuit 4a outputs a signal based on the output signal S2 of the first differential amplifier circuit 2 to the CMOS circuit 5 as the output signal OUT.
When a detection signal is input from the input state detection circuit 3a, a signal in an H state or an L state is output as an output signal OUT.
Output to MOS circuit 5.

When the non-inverted signal IN and the inverted signal INB are in the same state, the first differential amplifier circuit 2 outputs an intermediate voltage between the H state and the L state. However, it is determined that the signals IN and INB are in the same state by the input state detection circuit 3a.
Is detected and the detection signal is output to the output determination circuit 4a, the output determination circuit 4a outputs an H state or L state signal to the CMOS circuit 5 as the output signal OUT. As a result, the signal OUT whose state is determined is input to the CMOS circuit 5, so that the P-channel M
Both the OS transistor 51 and the N-channel MOS transistor 52 are not simultaneously turned on. Therefore, since no through current flows through the CMOS circuit 5, the failure of the CMOS circuit 5 when the non-inverted signal IN and the inverted signal INB have the same phase can be avoided.

Next, the input correction circuit 1a shown in FIG. 1 will be described in more detail. FIG. 2 is a circuit diagram showing a configuration of the input correction circuit 1a shown in FIG. As shown in FIG. 2, the input state detection circuit 3a includes a second differential amplifier circuit 31, a third differential amplifier circuit 32, and a logic circuit 33.

Second and third differential amplifier circuits 31, 32
Similarly, the first differential amplifier circuit 2 has a non-inverting input terminal (+) and an inverting input terminal (-). The non-inverting signal IN is input to the non-inverting input terminal (+) of the second differential amplifier circuit 31, and the reference signal REF is input to the inverting input terminal (-). The non-inverting input terminal (+) of the third differential amplifier circuit 32 receives an inverted signal INB,
The reference signal REF is input to the inverting input terminal (-).
Here, the reference signal REF is a signal whose voltage is set to an average value of the H state and the L state of the signals IN and INB. However, the voltage value of the reference signal REF is determined by the signals IN and INB.
The threshold level may be any value.

The second differential amplifier circuit 31 outputs the non-inverted signal I
It amplifies and outputs the voltage difference between N and the reference signal REF. When the voltage value of the non-inverted signal IN is higher than the reference signal REF, a signal in the H state is output as the output signal S31.
If it is lower than F, a signal in the L state is output as the output signal S31. Similarly, the third differential amplifier circuit 32
Is for amplifying and outputting the voltage difference between the inverted signal INB and the reference signal REF. When the voltage value of the inverted signal INB is higher than the reference signal REF, a signal in the H state is output as the output signal S32. Conversely, when the voltage value of the inverted signal INB is lower than the reference signal REF, the output signal is output. S3
As L, a signal in the L state is output.

The logic circuit 33 is connected to each output side of the differential amplifier circuits 31 and 32. The logic circuit 33 performs an exclusive OR operation on the output signals S31 and S32 of the differential amplifier circuits 31 and 32. Therefore, the logic circuit 3
3 outputs a signal in the H state as the output signal S33 when the signals S31 and S32 are in different states, and outputs each signal S33.
When the signals 31 and S32 are in the same state, a signal in the L state is output as the output signal S33. The signal in the L state output from the logic circuit 33 includes a non-inverted signal IN and an inverted signal IN.
B is a signal indicating that it is in the same state, and is called a detection signal.

Generally, the voltage values of the non-inverted signal IN and the inverted signal INB are small, and the threshold levels of the signals IN and INB are lower than the threshold level that is the basis for the logic judgment of the logic circuit 33. In such a case, in order for the logic circuit 33 to make a logical determination, it is necessary to amplify the threshold levels of the signals IN and INB to the threshold level of the logic circuit 33, and the differential amplifier circuits 31 and 32 are required. However, the signals IN, INB
If the logic circuit 34 having a threshold level equivalent to the threshold level is used, the input state detection circuit 3b can be configured without using the differential amplifier circuits 31 and 32 as shown in FIG. The logic circuit 34 in FIG. 3 is the same as the logic circuit 33 in FIG. 2 except for the threshold level.

As shown in FIG. 2, the output determination circuit 4a
It comprises a P-channel MOS transistor 41 and a power supply VDD. Further, the output side of the first differential amplifier circuit 2 and the input side of the CMOS circuit 5 are connected by a contact 42 in the output determination circuit 4a. The power supply VDD supplies a voltage VDD corresponding to the H state of the output signal of the first differential amplifier circuit 2.

The transistor 41 has a gate terminal (input terminal) connected to the output side of the logic circuit 33, a drain terminal (one output terminal) connected to the contact 42, and a source terminal (the other output terminal) connected to the power supply VDD. It is connected to the. When the output signal S33 of the logic circuit 33 is in the H state and no detection signal is applied, the transistor 41
The connection between the drains becomes non-conductive, and the connection between the contact 42 and the power supply VDD is opened. When the signal S33 is in the L state and the detection signal is applied, the source and the drain are brought into a conductive state, and the contact 42 and the power supply VDD are connected. As described above, the transistor 41 has a function as a switch circuit for opening and closing between the contact 42 and the power supply VDD. Note that P
The output determination circuit 4a may be configured using an N-channel MOS transistor instead of the channel MOS transistor 41. It is also possible to use a bipolar transistor.

Next, the operation of the input correction circuit 1a shown in FIG. 2 will be described. FIG. 4 is a time chart showing the operation of the input correction circuit 1a when an anti-phase signal is input. FIG. 5 is a time chart showing the operation of the input correction circuit 1a when the in-phase signal is input. In each of FIGS. 4 and 5, (a) shows the non-inverted signal IN, and (b) shows the inverted signal I.
NB, (c) is the output signal S2 of the first differential amplifier circuit 2,
(D) is an output signal S31 of the second differential amplifier circuit 31,
(E) is an output signal S32 of the third differential amplifier circuit 32,
(F) shows the output signal S33 of the logic circuit 33, and (g) shows the output signal OUT of the output determination circuit 4a.

First, the operation of the input correction circuit 1a when an anti-phase signal is input will be described with reference to FIG. As shown in FIGS. 4A and 4B, when the non-inverted signal IN and the inverted signal INB having phases opposite to each other are input to each input terminal (+,-) of the first differential amplifier circuit 2, Each signal IN,
Since INB is always in a different state, the first differential amplifier circuit 2 outputs an output signal S2 whose state has been determined.
This output signal S2 is a signal obtained by amplifying the non-inverted signal IN, as shown in FIG.

The non-inverted signal IN shown in FIG. 2A is applied to each input terminal (+,-) of the second differential amplifier circuit 31.
And the reference signal REF which is a constant voltage signal, the output signal S31 of the differential second dynamic amplifier circuit 31 is
The non-inverted signal IN as shown in (d) is an amplified signal. Similarly, the output signal S32 of the third differential amplifier circuit 32
Is a signal obtained by amplifying the inverted signal INB as shown in FIG. Therefore, the signals S31 and S32 input to the logic circuit 33 have opposite phases and are always in different states, so that the output signal S33 of the logic circuit 33 is shown in FIG.
As shown in FIG.

The signal S33 in the H state is a P-channel MO
When the voltage is applied to the gate terminal of the S transistor 41, the source and the drain of the transistor 41 are turned off. As a result, the power supply VDD is not connected to the contact 42 between the first differential amplifier circuit 2 and the CMOS circuit 5, so that the contact 4
No voltage corresponding to the H state is applied to 2. Therefore, as shown in FIG. 4 (g), the output determination circuit 4a outputs the output signal S of the first differential amplifier circuit 2 as the output signal OUT.
2 is output as it is.

Next, the operation of the input correction circuit 1a when the in-phase signal is input for a predetermined period will be described with reference to FIG. As shown in FIGS. 5A and 5B, in the periods T3 and T5, each input terminal (+,
-), The non-inverted signal IN and the inverted signal IN having the same phase
B is input. At this time, since the signals IN and INB are in the same state, the first differential amplifier circuit 2 outputs the signal from FIG.
The output signal S2 whose state is undefined is output as shown in FIG.

In the period T3, both the non-inverted signal IN and the inverted signal INB are in the H state. These signals IN, I
NB denotes second and third differential amplifier circuits 31, 32, respectively.
Is input to Then, since each of the differential amplifier circuits 31, 32 compares with the reference signal REF, each of the differential amplifier circuits 31, 3
2 output output signals S31 and S32 whose states have been determined. The output signals S31 and S32 are as shown in FIG.
As shown in (d) and (e), the non-inverted signal IN and the inverted signal INB are amplified signals, that is, H-state signals. On the other hand, in the period T5, both the signals IN and INB are in the L state, and the differential amplifier circuits 31 and 32 output the L state output signals S31 and S32 whose states have been determined.

As described above, in the periods T3 and T5, the signals S31 and S32 in the same state are input to the logic circuit 33. For this reason, the logic circuit 33 detects that both the non-inverted signal IN and the inverted signal INB are in the same state, and the output signal S33 of the logic circuit 33 becomes L state as shown in FIG. 33 outputs a detection signal. When the signal S33 in the L state is applied to the gate terminal of the P-channel MOS transistor 41, the source-drain of the transistor 41 becomes conductive. As a result, the power supply VDD is connected to the contact 42, so that a voltage corresponding to the H state is applied to the contact 42. Therefore, the output determination circuit 4a outputs the output signal OUT in the H state as shown in FIG. 5 (g).

As described above, the input correction circuit 1a shown in FIG.
, The non-inverted signal IN and the inverted signal IN
Even if B has the same phase, it is possible to prevent a voltage signal between the H state and the L state from being output to the CMOS circuit 5. Although the power supply VDD in FIG. 2 supplies a voltage corresponding to the H state of the output signal S2 of the first differential amplifier circuit 2, it supplies a voltage corresponding to the L state of the signal S2. It may be something. In this case, when the non-inverted signal IN and the inverted signal INB have the same phase, a signal in the L state is output as the output signal OUT.

(Second Embodiment) FIG. 6 is a circuit diagram showing the configuration of an input correction circuit for a CMOS circuit according to a second embodiment of the present invention. 6, the same or corresponding parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The input correction circuit 1b shown in FIG. 6 differs from the input correction circuit 1a shown in FIG. 2 in the configuration of the output determination circuit 4b.
The output determination circuit 4b of the input correction circuit 1b shown in FIG.
It is composed of a clocked inverter circuit 43 and two inverter circuits 44 and 45.

The clocked inverter circuit 43 is connected to the output side of the first differential amplifier circuit 2. The clocked inverter circuit 43 has a clock terminal CK, and the clock terminal CK is connected to the output side of the logic circuit 33. FIG. 7 is a circuit diagram showing a configuration of the clocked inverter circuit 43. As shown in FIG. 7, the clocked inverter circuit 43 includes two P-channel MOs.
S transistors 61 and 62 and two N-channel MOSs
It is composed of transistors 63 and 64, an inverter circuit 65, and a clock terminal CK.

The gate terminal of the transistor 61 is connected to the clock terminal CK via the inverter circuit 65, and the gate terminal of the transistor 63 is directly connected to the clock terminal CK. The drain terminals of the transistors 61 and 63 are commonly connected to the inverter circuit 44. Further, the gate terminals of the transistors 62 and 64 are commonly connected to the first differential amplifier circuit 2. The drain terminal and the source terminal of the transistor 62 are connected to the source terminal of the transistor 61 and a power supply (high-potential power supply) VDD, respectively. The drain terminal and the source terminal of the transistor 64 are connected to the source terminal of the transistor 63 and the power supply (low-potential power supply) VSS, respectively.

Logic circuit 3 input to clock terminal CK
When the output signal S33 of No. 3 is in the H state and the detection signal is not input, both the P-channel MOS transistor 61 and the N-channel MOS transistor 63 are turned on. At this time, the clocked inverter circuit 43
It functions as an inverter including a channel MOS transistor 62 and an N-channel MOS transistor 64.
That is, the output signal S2 of the first differential amplifier circuit 2 is inverted and output to the inverter circuit 44 as the output signal S43.

When the output signal S33 of the logic circuit 33 input to the clock terminal CK is in the L state and the detection signal is input, the P-channel MOS transistor 6
Both 1 and N-channel MOS transistor 63 are turned off. At this time, the output signal S2 of the first differential amplifier circuit 2 is not output to the inverter circuit 44. Therefore, the clocked inverter circuit 43 determines whether or not the preceding stage circuit (the first differential amplifier circuit 2) depends on whether or not the detection signal is input.
It has a function as a switch circuit that opens and closes between a circuit and a subsequent circuit (a signal holding circuit described later).

The inverter circuits 44 and 45 are connected between the output side of the clocked inverter circuit 43 and the input side of the CMOS circuit 5 so as to form a loop.
Here, one inverter circuit 44 is connected between the clocked inverter circuit 43 and the CMOS circuit 5 in the forward direction,
The other inverter circuit 45 is connected in the opposite direction.

The inverter circuit 44 inverts the output signal S43 of the clocked inverter circuit 43 and outputs the output signal O
A signal in a state different from the signal S43 is output to the CMOS circuit 5 as the UT. The inverter circuit 45 inverts the output signal OUT of the inverter circuit 44 and supplies a signal in a state different from the signal OUT to the inverter circuit 44. Even if the output of the clocked inverter circuit 43 stops, the output signal S43 of the clocked inverter circuit 43 immediately before it stops.
Is supplied to the inverter circuit 44, so that the state of the output signal OUT of the inverter circuit 44 is maintained. Therefore, inverter circuits 44 and 45 function as signal holding circuits.

Next, the operation of the input correction circuit 1b shown in FIG. 6 will be described. First, the operation of the receiving circuit when an anti-phase signal is input will be described. In this case, since each signal changes state in the same manner as in FIG. 4, the description of the time chart is omitted. When the non-inverted signal IN and the inverted signal INB having opposite phases are input to each input terminal (+,-) of the first differential amplifier circuit 2, the input correction circuit 1 shown in FIG.
Similarly to a, the output signal S2 whose state is determined is output from the first differential amplifier circuit 2, and the detection signal is not output from the logic circuit 33 (that is, the output signal S33 of the logic circuit 33 is set to the H state). Become).

At this time, since no detection signal is input to the clocked inverter circuit 43, the clocked inverter circuit 43 is always in an operating state, and inverts and outputs the output signal S2 of the first differential amplifier circuit 2. Therefore, the output signal S43 of the clocked inverter circuit 43 becomes a signal in a state different from the signal S2. Since the output signal S43 of the clocked inverter circuit 43 is inverted again by the inverter circuit 44, a signal in the same state as the output signal S2 of the first differential amplifier circuit 2 is output from the inverter circuit 44 as the output signal OUT.

Next, the operation of the input correction circuit 1b when the in-phase signal is input for a predetermined period will be described with reference to FIGS. FIG. 8 is a time chart showing the operation of the input correction circuit 1b when the in-phase signal is input. FIG.
Is a time chart showing the operation of the input correction circuit 1b when the in-phase signal is input only for a short time. 8 and 9, (a) shows the non-inverted signal IN, (b) shows the inverted signal INB, (c) shows the output signal S2 of the first differential amplifier circuit 2, and (d) shows the second differential signal. Output signal S3 of amplifier circuit 31
1, (e) shows the output signal S3 of the third differential amplifier circuit 32
2, (f) shows the output signal S33 of the logic circuit 33, and (g) shows the output signal OUT of the output determination circuit 4b.

As shown in FIGS. 8A and 8B, during periods T3 and T5, the non-inverted signals IN and IN having the same phase with each other are input to the input terminals (+,-) of the first differential amplifier circuit 2. The inverted signal INB is input. At this time, similarly to the input correction circuit 1a shown in FIG.
8C, an output signal S2 whose state is undefined is output, and a detection signal is output from the logic circuit 33 as shown in FIG. 8F (that is, the output signal S of the logic circuit 33).
33 is in the L state).

At this time, since the detection signal is input to the clocked inverter circuit 43, the clocked inverter circuit 43 is stopped and the clocked inverter circuit 43 is stopped.
Output stops. As described above, the inverter circuit 4
Since the signal holding circuit is constituted by the signals 4 and 45, the output signal OUT of the inverter circuit 44 is held in a state immediately before the detection signal is input to the clocked inverter circuit 43. As shown in FIG. 8 (g), the periods T2 and T4
Since the output signal OUT of the inverter circuit 44 is in the L state, the output signal OUT is also kept in the L state in the periods T3 and T5.

As described above, the input correction circuit 1b shown in FIG.
Then, while the non-inverted signal IN and the inverted INB have the same phase, the output determination circuit 4b continues to output the signal OUT immediately before the signals IN and INB have the same phase. Therefore, similarly to the input correction circuit 1a shown in FIG. 2, it is possible to prevent a voltage signal between the H state and the L state from being output to the CMOS circuit 5.

In particular, as shown in a period T2 in FIG. 9, if the abnormal inverted signal INB recovers to normal before the state of the normal non-inverted signal IN changes, the signal immediately before the inverted signal INB becomes abnormal is restored. Since the output signal OUT is held, the effect of this is completely eliminated. The same applies to the period T4. Therefore, if the output signal OUT of the input correction circuit 1b shown in FIG. 6 is used as a clock signal of the CMOS circuit 5, malfunction of the CMOS circuit 5 can be suppressed.
The reliability of the MOS circuit 5 can be improved. Note that the input state detection circuit 3b shown in FIG. 3 can also be used for the input correction circuit 1b shown in FIG.

[0042]

As described above, according to the present invention, the first
If two digital signals input to the differential amplifier circuit are in the same state, this is detected by the input state detection circuit, and the output signal of the first differential amplifier circuit is converted to the digital signal by the output determination circuit. The signal is converted into one of the states and output to the CMOS circuit. Thus, application of an intermediate voltage between the H state and the L state to the CMOS circuit can be prevented. Therefore, according to the present invention, the failure of the CMOS circuit when the differential signals have the same phase can be suppressed. Claim 3
According to the invention described above, the voltage difference between each digital signal and the reference signal is amplified by the second and third differential amplifier circuits and output to the logic circuit, and the logic circuit uses the second and third differential amplifier circuits. It is determined whether the output states are the same. Generally, the voltage value of the differential signal is small, but by amplifying the voltage difference from the reference signal using the second and third differential amplifier circuits, it is possible to make a determination in a logic circuit.

According to the fourth aspect of the present invention, an output determining circuit can be realized with a simple configuration using a transistor and a power supply. According to the present invention, when two digital signals input to the first differential amplifier circuit are in the same state, the signal output from the output determination circuit immediately before that is output to the CMOS circuit. Keep doing. Therefore,
If the abnormal digital signal recovers normally before the state of the normal digital signal changes, the influence of this will be completely eliminated. Therefore, if the output signal of the input correction circuit is used as the clock signal of the CMOS circuit, the CMO
Since the malfunction of the S circuit can be suppressed, the reliability of the CMOS circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an input correction circuit for a CMOS circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of the input correction circuit shown in FIG.

FIG. 3 is a circuit diagram showing another configuration of the input state detection circuit.

FIG. 4 is a time chart showing an operation of the input correction circuit shown in FIG. 2 when an anti-phase signal is input.

5 is a time chart showing an operation of the input correction circuit shown in FIG. 2 when the same phase signal is input.

FIG. 6 is a circuit diagram showing a configuration of a second embodiment of an input correction circuit for a CMOS circuit according to the present invention.

FIG. 7 is a circuit diagram showing a configuration of a clocked inverter circuit.

8 is a time chart showing an operation of the input correction circuit shown in FIG. 6 when the same phase signal is input.

9 is a time chart showing the operation of the input correction circuit shown in FIG. 6 when the in-phase signal is input only for a short time.

FIG. 10 is a block diagram showing a connection relationship between a differential amplifier circuit and a CMOS circuit.

FIG. 11 is a time chart illustrating an operation of the differential amplifier circuit.

[Explanation of symbols]

1a, 1b: input correction circuit, 2, 31, 32: differential amplifier circuit, 3a, 3b: input state detection circuit, 4a, 4b: output determination circuit, 5: CMOS circuit, 33, 34: logic circuit, 41, 51, 52, 61 to 64: transistor, 4
2 contact, 43 clocked inverter circuit, 44, 4
5, 65: inverter circuit, CK: clock terminal, I
N, INB, OUT, REF, S2, S31 to S33,
S43: signal, T1 to T6: period, VDD, VSS: power supply.

Claims (8)

[Claims] 1. A first differential amplifier circuit having two input terminals and outputting a signal based on a potential difference between digital signals input to these input terminals, and at least the first differential amplifier circuit An input state detection circuit that outputs a detection signal when the digital signals are input to a circuit and detects that the digital signals are in the same state; a first differential amplifier circuit and the input state detection Connected to the output side of each circuit and output the signal based on the output of the first differential amplifier circuit when the detection signal is not input, and output the first differential signal when the detection signal is input. An output determining circuit for outputting a signal in any state of the output signal of the amplifier circuit, wherein a CMOS circuit is connected to an output side of the output determining circuit. Input correction circuit for S circuit. 2. The input state detection circuit according to claim 1, further comprising: a reference signal set to a threshold level of each of the digital signals input to the first differential amplifier circuit; An input correction circuit for a CMOS circuit, comprising means for comparing each digital signal with the reference signal to detect that each digital signal is in the same state and to output the detection signal. 3. The circuit according to claim 2, wherein the means included in the input state detection circuit includes: a second differential amplifier circuit that outputs a signal obtained by amplifying a voltage difference between one of the digital signal and the reference signal; A third differential amplifier circuit for outputting a signal obtained by amplifying a voltage difference between the other digital signal and the reference signal; and a third differential amplifier circuit connected to an output side of each of the second and third differential amplifier circuits, A logic circuit for outputting the detection signal when the output signals of the second and third differential amplifier circuits are in the same state, respectively. 4. The output determination circuit according to claim 1, wherein the output determination circuit comprises: a power supply for supplying a voltage in any state of an output signal of the first differential amplifier circuit; One output terminal connected to the output side of the input state detection circuit, one output terminal connected to the output side of the first differential amplifier circuit and the input side of the CMOS circuit, the other output terminal connected to the power supply, and the detection signal And a transistor that conducts between the two output terminals when is input. 5. The output determination circuit according to claim 1, wherein, when the detection signal is input, the output determination circuit continues outputting the signal output immediately before the detection signal. An input correction circuit for a CMOS circuit, comprising: 6. The device according to claim 5, wherein the means included in the output determination circuit includes: a signal holding circuit that holds and outputs an input signal; and a signal holding circuit that is connected to an output side of the input state detection circuit and the detection signal is When the detection signal is not input, the connection between the first differential amplifier circuit and the signal holding circuit is made, and when the detection signal is input, the connection between the first differential amplifier circuit and the signal holding circuit is made. An input correction circuit for a CMOS circuit, comprising: a switch circuit that opens. 7. The input for a CMOS circuit according to claim 6, wherein the second switch circuit is a clocked inverter circuit having a clock terminal connected to an output side of the input state detection circuit. Correction circuit. 8. The input correction circuit for a CMOS circuit according to claim 6, wherein the signal holding circuit includes two inverter circuits forming a loop.