JP2000114371A - Multi-layer interconnection structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce defects due to interference between the upper and lower wirings by decreasing the line thickness area of an upper layer wiring. SOLUTION: A first inter-layer insulating film 8 comprising a TEOS(tetraethyl orthosilicate) film covering a first wiring 7 formed on a semiconductor substrate 1, a second wiring 9 contacting the first wiring 7 with the first inter-layer insulating film 8 in between, a second inter-layer insulating film 10 comprising the TEOS film which converts the second wiring 9, a third wiring 11 contacting the second wiring 9 with the second inter-layer insulating film 10 in between, and a passivation film 12 comprising a polymide insulating film 14 and a silicon nitride film 13 which covers the third wiring 11 are provided, and in the third wiring 11, a chroma signal, synchronization signal, and serial control signal, etc., used for an image signal which tends to cause mutual interference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure of a semiconductor device, and more particularly, to a technique for reducing problems caused by mutual interference between a lower wiring and an upper wiring.

[0002]

2. Description of the Related Art With the recent miniaturization of large-scale integrated circuits, particularly the miniaturization of elements constituting circuits, the area of wiring in the entire large-scale integrated circuit tends to relatively increase.
Multilayer wiring structures have been adopted.

FIG. 2 is a sectional view showing a conventional multilayer wiring structure. 21 is a semiconductor substrate; 22 is a diffusion region;
Is a silicon oxide film covering the surface of the substrate, which comprises a CVD oxide film, a thermal oxide film, or the like. The oxide film 23 has a diffusion region 2
A contact hole exposing a part of the surface is provided, and a first wiring extending over the oxide film makes ohmic contact with the surface of the diffusion region via the contact hole.

The upper part of the first wiring 24 is covered with a first interlayer insulating film 25. The first interlayer insulating film 25 is made of TEOS as a CVD oxide film having a thickness of about 10000 °.
The first interlayer insulating film 25 is provided with a contact hole for exposing the surface of the first wiring 24, and the first interlayer insulating film 2
The second wiring 26 extending over the first wiring 5 is in contact with the first wiring 24 via the contact hole.

The upper portion of the second wiring 26 is covered with a second interlayer insulating film 29. The second interlayer insulating film 29
A silicon nitride film 27 having a thickness of about 5000
The second interlayer insulating film 29 is provided with a contact hole exposing the surface of the second wiring 26 and extends over the second interlayer insulating film 29. The third wiring 30 is in contact with the second wiring 26 through the contact hole.

Then, a passivation film 31 is formed so as to cover the upper part of the third wiring 30.
The passivation film 31 is formed of a polyimide-based insulating film having a thickness of about 20,000 °, and the passivation film 31 is provided with an opening in a bonding pad portion, and is resin-molded to form a semiconductor device.

[0007]

Here, the polyimide-based insulating film used as the base of the upper wiring is a high-quality insulator having both high insulating properties and a low dielectric constant, and the material cost is low. Widely used as an interlayer insulating film of a multilayer wiring structure. However, when the upper wiring is formed by patterning, the underlying layer is a polyimide-based insulating film that cannot withstand dry etching, and is etched by a wet method. For this reason, because of the wet method, the line width is wider than necessary than the lower layer wiring. For this reason, the cross-sectional area between the upper and lower wirings is widened, and a problem such as an increase in coupling capacitance due to mutual interference between the upper and lower wirings has occurred.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multilayer wiring structure in which the line width area of the upper wiring is reduced to reduce the problems caused by mutual interference between the upper and lower wirings.

[0009]

SUMMARY OF THE INVENTION The multilayer wiring structure of the present invention has been made in view of the above-mentioned problems, and has a semiconductor substrate 1;
A first interlayer insulating film 8 made of a TEOS film covering the first wiring 7 formed thereon, and a second wiring 9 contacting the first wiring 7 with the first interlayer insulating film 8 interposed therebetween. A second interlayer insulating film 10 made of a TEOS film covering the second wiring 9, a third wiring 11 contacting the second wiring 9 with the second interlayer insulating film 10 interposed therebetween, The third wiring 11 includes a silicon nitride film 13 covering the third wiring 11 and a passivation film 12 made of a polyimide-based insulating film 14. The third wiring 11 has a chroma signal used for a video signal which is likely to cause mutual interference. A system signal, a synchronization signal, a serial control signal, and the like are flowing. Further, since a hard CVD oxide film is used as a base interlayer insulating film instead of a soft polyimide-based insulating film, etching by a dry method can be performed at the time of patterning the third wiring 11 instead of the conventional wet method. This makes it possible to optimize the wiring line width, reduce the cross-sectional area between the upper and lower wirings, and reduce the coupling capacitance.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multilayer wiring structure according to the present invention will be described below with reference to the drawings.

The feature of the present embodiment is that the line width of the upper layer wiring can be optimized by using an interlayer insulating film that does not include a polyimide insulating film that cannot withstand dry etching at the time of wiring patterning. The purpose of the present invention is to reduce the area of intersection and reduce problems caused by mutual interference between upper and lower wiring. Also, such optimized upper layer wiring includes:
The chroma signal (3.58 MH) used for the video signal
By passing a signal having a relatively high frequency (e.g., z, 4.43 MHz), deterioration of characteristics due to leakage of the high frequency is suppressed.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate of one conductivity type, for example, a P type, 2 denotes an N type epitaxial layer formed on the surface of the semiconductor substrate 1, 3 denotes an N + buried layer, 4 denotes a P + isolation region, Is a P-type or N-type diffusion region. A circuit element such as a transistor is formed in each of the epitaxial layers 2 surrounded by the isolation region 4.

Reference numeral 6 denotes a silicon oxide film covering the surface of the epitaxial layer 2, and is composed of a CVD oxide film, a thermal oxide film, or the like. The oxide film 6 is provided with a contact hole exposing a part of the surface of the diffusion region 5, and the first wiring 7 extending on the oxide film 6 makes an ohmic contact with the surface of the diffusion region 5 through the contact hole. I do.

An upper portion of the first wiring 7 is covered with a first interlayer insulating film 8. The first interlayer insulating film 8 has a thickness of 1
TEOS (Tetr
The first interlayer insulating film 8 is provided with a contact hole exposing the surface of the first wiring 7, and the second interlayer insulating film 8 extends over the first interlayer insulating film 8. Wiring 9 is in contact with the first wiring 7 through the contact hole.

The upper part of the second wiring 9 is covered with a second interlayer insulating film 10. The second interlayer insulating film 10
A contact hole exposing the surface of the second wiring 9 is provided in the second interlayer insulating film 10.
The third wiring 11 extending upward is in contact with the second wiring 9 via the contact hole.

Then, a passivation film 12 is formed so as to cover the upper part of the third wiring 11.
The passivation film 12 is composed of a silicon nitride film 13 having a thickness of about 5000 ° and a polyimide-based insulating film 14 having a thickness of about 20000 °. Is completed.

Here, since the interlayer insulating film 10 as a base film of the third wiring 11 is not a polyimide insulating film that cannot withstand dry etching, but a hard TEOS film, the patterning of the third wiring 11 can be performed. Since it can withstand dry etching, it is easier to optimize the line width after patterning than the wet method corresponding to the conventional polyimide insulating film, so the cross-sectional area between the upper and lower wiring can be reduced, The problem caused by mutual interference can be reduced.

A signal having a relatively high frequency such as a chroma signal (3.58 MHz, 4.43 MHz) used for a video signal flows through the optimized third wiring 11. Thus, it is possible to suppress the characteristic deterioration due to the leakage of the high frequency.

Further, a pulse signal containing a large amount of high-frequency components such as a video synchronization signal or serial control may be supplied to the third wiring 11.

[0020]

As described above, according to the present invention, an interlayer insulating film structure made of a CVD oxide film without using a soft polyimide insulating film as a base makes it possible to perform patterning formation of upper layer wiring from wet to dry etching. Therefore, the line width of the upper layer wiring can be optimized, the intersection area with the lower layer wiring can be reduced, and the problem due to mutual interference can be reduced. Then, a relatively high-frequency signal such as a chroma signal, a synchronization signal, and a serial control signal used for a video signal is supplied to the optimized upper layer wiring, so that the high-frequency signal is transmitted. Characteristic deterioration due to the leakage of water can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a multilayer wiring structure of the present invention.

FIG. 2 is a sectional view of a conventional multilayer wiring structure.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C020 AA33 AA40 5F033 QQ08 QQ11 RR04 SS04 SS11 XX24 5F058 BA20 BD01 BD04 BD09 BF25 BJ02 5F110 NN02 NN23 NN28 NN35

Claims (2)

[Claims] 1. A CV for covering a lower wiring on a semiconductor substrate
A lower interlayer insulating film made of a D oxide film, an upper wiring that contacts the lower wiring with the lower interlayer insulating film interposed therebetween, a passivation film made of a silicon nitride film and a polyimide-based insulating film that covers the upper wiring. The multilayer wiring structure according to claim 1, wherein a signal of a relatively high frequency such as a chroma signal used for a video signal flows in the upper wiring. 2. A CV covering a lower wiring on a semiconductor substrate.
A lower interlayer insulating film made of a D oxide film, an upper wiring that contacts the lower wiring with the lower interlayer insulating film interposed therebetween, a passivation film made of a silicon nitride film and a polyimide-based insulating film that covers the upper wiring. Wherein a pulse signal including a high-frequency component such as a video synchronization signal or a serial control signal flows through the upper wiring.