JP2000113699A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To replace a memory bank that cannot be repaired with a memory bank that operates in all bits, and to greatly improve the repair efficiency. SOLUTION: An irreparable bank of a memory array 2 is replaced with a normal bank B0 by a switching control circuit 3 provided in each of the banks B0 to B7, and a bank uppermost address TURE (first signal) side (BA).
Set to operate only 3). For example, the switching circuit 3b of the defective bank B0 turns off all the switches.
In the bank B4 switched to the bank B0, only the switch to which the bank address signal BA0 is input is turned ON.
Is set in the storage circuit 3a so that

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory rescue technique, and more particularly, to a synchronous DRAM (Dynamic DRAM).
The present invention relates to a technology effective when applied to defective bank relief in a memory having a bank configuration such as Random Access Memory.

[0002]

2. Description of the Related Art According to studies made by the present inventor, in a semiconductor integrated circuit device such as a synchronous DRAM, when a defective row or column or a memory cell exists in a memory array in each memory bank. A defect relieving circuit for selecting a spare row or column when an address signal corresponding to a defective portion is input is provided.

[0003] An example of this type of semiconductor integrated circuit device is described in detail in November 5, 1994.
Published by Baifukan Co., Ltd., Kiyoo Ito (author), "Advanced Electronics I-9 Ultra LSI Memory" P34
4 to P347. In this document, the synchronous DR
A circuit configuration in AM is described.

[0004]

However, the present inventor has found that the defect remedy technique for a semiconductor integrated circuit device as described above has the following problems.

With the recent increase in memory capacity and integration, the number of defects to be rescued tends to increase. However, it is difficult to increase the number of rescue sets due to a reduction in the area of a semiconductor chip.

For example, in a memory having a multi-bank configuration of 1 Gbit level, there is a possibility that a sufficient number of repair sets cannot be mounted, and a memory having such a bank that cannot be repaired does not become a product, and the yield is greatly reduced. There is a problem of doing it.

Further, as a countermeasure for a memory having a bank which cannot be repaired, there is a partial system in which a memory capacity for ignoring an I / O partial or a row system highest address in the bank is half.

[0008] However, the I / O partial has a problem that the number of semiconductor chips operating at the time of module mounting is large, and the current becomes large. Further, in the partial method with half the memory capacity, if a defect is present simultaneously in a region divided by the highest address in the same bank, it becomes a defective product, and an attempt is made to achieve a normal capacity by mounting a two-chip module. In such a case, there is a problem that the operating current is doubled.

An object of the present invention is to provide a semiconductor integrated circuit device capable of greatly improving the rescue efficiency by replacing a memory bank that cannot be relieved with a memory bank that operates in all bits.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit device of the present invention, in a plurality of memory banks divided for each predetermined bit, a memory bank that cannot be repaired and a memory bank that operates on all bits are replaced. Switching control means for relieving half of the memory banks is provided.

Further, in the semiconductor integrated circuit device according to the present invention, the switching control means stores a preset data and outputs the data as a switching control signal, and an output from the switching control unit. And a switching unit that outputs a bank address signal output from the bank select based on the set switching control signal to a preset memory bank that operates on all bits.

[0014] Thereby, it can be used as a product having half the memory capacity.

Further, the semiconductor integrated circuit device according to the present invention
The first signal and the second signal, which are complementary signals of the highest address of the bank, are monitored, and when either one of the first signal and the second signal is input, half of the signals rescued by the switching control means are reset. A bank enable control means for operating a memory bank is provided.

The semiconductor integrated circuit device according to the present invention has
A normal memory capacity is formed by the two rescued half memory banks, and the bank enable control means is configured to select one of the two rescued half memory banks based on a first signal or a second signal. A semiconductor integrated circuit device selectively operating one half of the memory banks.

Thus, it can be used as a regular memory capacity product, and an increase in operating current can be suppressed.

Furthermore, the semiconductor integrated circuit device of the present invention
A precharge potential supply means for supplying a bit line precharge potential to only half of the memory banks is provided.

As a result, it is possible to prevent a current leak or the like in a defective memory bank, and to stably supply a precharge potential.

Further, the semiconductor integrated circuit device of the present invention is provided with bank information monitoring means for outputting bank switching information of the memory bank switched by the switching control means to a predetermined external input / output terminal.

Thus, even when the memory bank is switched, failure analysis, reliability evaluation, and the like can be easily performed.

As described above, even a semiconductor chip having a memory bank which cannot be repaired can be commercialized, so that the yield of the semiconductor integrated circuit device can be greatly improved.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is an explanatory diagram of a connection state of a memory according to Embodiment 1 of the present invention, FIG. 2 is a block diagram of the memory according to Embodiment 1 of the present invention, and FIG.
FIG. 4 is an explanatory diagram of a switching control circuit provided in the memory according to the first embodiment of the present invention, FIG. 4 is a circuit diagram of a bank select provided in the memory according to the first embodiment of the present invention, and FIGS. FIG. 7 is an explanatory diagram of a bank switched by the switching control circuit according to the first embodiment of the present invention. FIG. 7 is a timing chart in the memory according to the first embodiment of the present invention.

In the first embodiment, the synchronous D
A memory (semiconductor integrated circuit device) 1 which is a RAM is shown in FIG.
As shown in the figure, the semiconductor chip is composed of two semiconductor chips CH1 and CH2.

The memory arrays 2 and 2a provided in the semiconductor chips CH1 and CH2 are provided with two memory arrays 2 and 2a in which memory cells, which are minimum storage units, are regularly arranged in an array. Each of the memory arrays 2 and 2a has an eight-bank configuration in which eight banks (memory banks) B0 to B7 are provided.

Further, the semiconductor chips CH1 and CH2 have a clock signal CLK input from the outside, a clock enable signal CKE which is a permission signal for receiving the clock signal, and a chip select signal / C for selecting a chip.
S, a row address strobe signal / R which is a control signal for reading an address in the row direction at an appropriate timing.
AS, an external input such as a column address strobe signal / CAS as a control signal for reading an address in a column direction at an appropriate timing, a write enable signal / WE as a write enable signal, an address signal Ai, and a bank address signal BAi. Are connected so that various signals to be input and output are commonly input and output.

In the memory 1, in each of the memory arrays 2 and 2a, irreparable banks are replaced to form a 4-bank configuration, and the total of the two memory arrays 2a and 2b forms an 8-bank configuration. ing.

The memory 1 has a general circuit configuration, and as shown in FIG.
1, CH2, switching control circuit (switching control means)
3, bank select (bank enable control means) 4,
Row decoder 6, row control 7, column decoder 8, column control 9, row / column address buffer 10, address input buffer 11, bank address input buffer 12, clock input buffer 13, internal clock generation circuit 14, sense amplifier, column address A counter, a control circuit, an input buffer, an output buffer, and the like are provided.

The switching control circuit 3 includes a bank select 4
And outputs the bank address signals BA0 to BA7 output from the bank to a preset bank. The bank select 4 decodes a bank address input from the outside via the bank address input buffer 12, and outputs bank address signals BA0 to BA7.

The row decoder 6 selects a word line in the row (row) direction of the memory array 2 (FIG. 1), and the row control 7 controls the timing of the row decoder and the like. The column decoder 8 selects a bit line in a column (column) direction, and the column control 9 controls the timing of the column decoder. The row decoder 6, row control 7, column decoder 8, and column control 9 are provided in the memory array 2 area.

The row / column address buffer 10 receives the row / column direction address signal based on the input address signal.
It generates each internal address signal and outputs it to the row decoder 6 and the column decoder 8, respectively.

The control circuit includes a clock signal CLK, a clock enable signal CKE, a chip select signal / CS, and a row address strobe signal / RA.
Input signals and command signals such as S, column address strobe signal / CAS, write enable signal / WE, address signal Ai, and bank address signal BAi are input through input terminals, and various control signals and command signals are input. Output the decoded control signal.

Further, the control circuit is provided with an internal clock generation circuit 14 for generating a signal synchronized with the above-mentioned clock signal CLK and supplying the signal as a clock signal which is a basic operation of the memory 1. The clock signal generated by the clock generation circuit 14 is supplied via an internal clock bus.

The sense amplifier amplifies bit line data activated by the word line selected by the row decoder 6. The column address counter generates a burst mode address based on an address signal input from the column address buffer.

The address input buffer takes in the input address signal at a predetermined timing. The input buffer takes in the input data at a predetermined timing, and the output buffer temporarily stores the output data. The refresh counter counts a refresh operation.

The switching control circuit 3 is connected to each of the banks B0 to B7 of the memory array 2 (, 2a) as shown in FIG. This switching control circuit 3
Is composed of a storage circuit (switching control unit) 3a and a switching circuit (switching unit) 3b.

The storage circuit 3a stores preset data and outputs the data as a switching control signal. The storage circuit 3a is configured by, for example, a fuse, a semiconductor memory, or the like.

The switching circuit 3b is composed of eight (the same number as the banks B0 to B7) switch circuits. Each switch in the switching circuit 3b is
The bank control signal is switched based on a switching control signal input to a control terminal provided in the switch.

The storage circuit 3a is connected to a control terminal provided for each switch in the switching circuit 3b, and switches ON / OFF based on the switching control signal.
Turn off. One connection of each switch is connected to each of the banks B0 to B7, and the other connection is connected to a bank select 4.

Bank select 4 is, as shown in FIG.
NOR circuit NR1 to NR8 and NAND circuit N
It is composed of a combination of logic circuits D1 to ND8.

The bank address signals PBS0 to PBS7 are respectively input to one input of the NOR circuits NR1 to NR8 via a bank address input buffer, and the other input sections of the NOR circuits NR1 to NR8 are provided. Includes a selection signal SC for selecting an operation bank of a chip output from a selection signal control unit provided in the bank select 4.
H1 and SCH2 are connected so as to be input.

The selection signal control section is composed of, for example, fuses, and arbitrarily cuts these fuses to set signal levels (Hi signal, Lo signal) of the selection signals SCH1 and SCH2.

The other inputs of the NAND circuits ND1 to ND8 are connected to the outputs of the NOR circuits NR1 to NR8, respectively. , And a bank active command BC. The signals output from the output units of the NAND circuits ND1 to ND8 are the bank select signals BS0 to BS7.

Next, the operation of this embodiment will be described with reference to FIG.
This will be described with reference to FIGS.

For example, as shown in FIG. 5, when the banks B1 to B4 of the banks B0 to B7 of the memory array 2 are irreparable banks, the respective banks B0 to B7
The switching control circuit 3 (FIG. 3) provided in B7 replaces the bank B4 with the normal bank B0, and sets so that only the TURE (first signal) side (BA3) of the highest address of the bank operates.

In the memory array 2a, FIG.
As shown in FIG.
If B5 is a bank that cannot be repaired, the switching control circuit 3 (FIG. 3) provided in each of the banks B0 to B7 replaces the bank B3 with a normal bank B7, and replaces the BAR (the second bank address) of the highest bank address. Signal) side (/ BA
Set to operate only 3).

To replace these banks, a switching control signal is set in the storage circuit 3a of the switching control circuit 3 provided in each of the banks B0 to B7. To replace the banks B0 and B4 in the memory array 2, the storage circuit 3a is set so that the switch of the switching circuit 3b of the bank B0 is connected to B4 so that the bank B0 is not operated. Or, all switches are OF
F, and the switch may be fixed at a power supply so that the input of the bank B4 is not operated.

The storage circuit 3a is set so that only the switch to which the bank address signal BA0 is input in the switching circuit 3b of the switching control circuit 3 provided in the bank B4 is turned on.

When this switch is turned on, bank B4 is selected when a signal for selecting bank B0, that is, when bank address signal BA0 is output from bank select 4, bank B0 and bank B0 are selected. This means that B4 has been replaced.

With the above setting, a synchronous DRAM having a 4-bank configuration can be provided. For example, if the memory capacity is 1 Gbit in an 8-bank configuration, each of the semiconductor chips CH1 and CH2 has a 4-bank configuration and 512M.
It can be operated with a memory capacity of 2 bits.

In the bank select 4, for example, the selection signal SCH1 is a Hi signal (power supply voltage V _CC ) and the selection signal SCH2 is a Lo signal (reference potential V _SS ), so that the banks B0 to B3 in the semiconductor chip CH1. Does not operate, and in the semiconductor chip CH2, the bank B4
To B7 do not operate.

Further, these two semiconductor chips CH
The refresh control in the memory 1 constituted by 1 and CH2 may be a refresh operation by all-bank active similarly to the normal refresh.

FIG. 7 shows a timing chart of the memory 1. FIG. 7 shows the signal timing of the clock signal CLK, the bank active command BC, and the bank top address BA3 from the top to the bottom.

The bank select 4 monitors TURE and BAR at the highest bank address BA3. For example, when the BAR side of the highest bank address BA3 is selected, the semiconductor chip CH2 is enabled.

Actually, the internal clock generation circuit 14 and the row / column address buffer 10 operate irrespective of the bank highest address BA3. In the case of the present embodiment, however, most of the operation current Since the array system and the column system occupying the above do not operate extra, the current hardly increases.

Thus, in the first embodiment,
Even a memory having an irreparable bank can be used as a regular memory capacity product, and the bank select 4 allows the highest address TURE, BA of the bank to be used.
Since only one semiconductor chip is operated by R, an increase in operating current can be suppressed.

(Embodiment 2) FIG. 8 is an explanatory diagram of a switching control circuit and an I / O buffer provided in a memory according to Embodiment 2 of the present invention, and FIG. 9 is a diagram according to Embodiment 2 of the present invention. FIG. 3 is a circuit diagram of an I / O buffer.

In the second embodiment, the memory 1
As shown in FIG. 8, there are provided I / O buffers BF0 to BF7 which can output bank information switched by the switching control circuit 3 from predetermined I / O pins.

The I / O buffers BF0 to BF7 are connected to receive the test mode control circuit T and the bank address signals BA0 to BA7.

As shown in FIG. 9, the I / O buffer BF0 (〜BF7) is composed of NAND circuits ND9〜ND11 and inverters Iv1 and Iv2. One input of the NAND circuit ND9 has an I / O
Internal data, which is data, is input, and the output of the inverter Iv1 is connected to the other input.

The input of the inverter Iv1 and one input of the NAND circuit ND10 are connected to receive the test signal TEST output from the test mode control circuit T, and the other input is connected to the other input. It is connected so that the bank address signal BAi is input.

The output sections of the NAND circuits ND9 and ND10 are connected to one input section and the other input section of the NAND circuit ND11, respectively. NAND circuit ND1
The output unit 1 is connected to the input unit of the inverter Iv2.

When the memory 1 is tested, the test signal TEST of the test mode control circuit T becomes a Hi signal. Therefore, even if the internal data changes to either the Hi signal or the Lo signal, the output result is obtained by the bank address signal BAi. Will change.

For example, when bank B0 is rescued by bank B4, when bank address signal BA0 is input, "0" is output to I / O buffer BF4, and the other I / O buffers BF0-BF3, BF5- '1' is output to BF7.

When the bank address signal BA4 is input, "0" is output to the I / O buffer BF0, and "1" is output to the other I / O buffers BF1 to BF7.

Therefore, according to the second embodiment, I / O
Since the buffers BF0 to BF7 can arbitrarily output bank information to predetermined I / O pins, failure analysis, reliability evaluation, and the like can be easily performed.

(Embodiment 3) FIG. 10 is an explanatory diagram of a switching control circuit and a reduction circuit provided in a memory according to a third embodiment of the present invention. FIG. 11 is a diagram illustrating a reduction control circuit according to a third embodiment of the present invention. It is a circuit diagram of a circuit.

In the third embodiment, as shown in FIG. 10, the memory (semiconductor integrated circuit device) 1 outputs the bank information switched by the switching control circuit 3 from a predetermined I / O pin to an I / O pin. O buffer BF8 to BF
10 and a reduction circuit 15 are provided.

The reduction circuit 15 includes a bank address signal B
A0 to BA7 are connected so as to be input, and three reduced signals TBak and TB output from the reduction circuit 15 are connected.
Kj and TBKi are connected to be input to the I / O buffers BF8 to BF10, respectively. Also, I / O
The test mode control circuit T is connected to the buffers BF8 to BF10.

As shown in FIG. 11, reduction circuit 15 includes inverters Iv3 to Iv9 and NAND circuit ND1.
2 to ND14. Inverter Iv3 ~
The input section of Iv9 has bank address signals BA0 to BA
7, respectively.

The NAND circuits ND12 to ND14 have 4
The output is an input, and the output of the inverter Iv3 is connected to the input of each of the NAND circuits ND12 to ND14.

The output of the inverter Iv4 is connected to the inputs of the NAND circuits ND13 and ND14, respectively, and the output of the inverter Iv5 is connected to the NAND circuits ND12 and ND14.
D14 is connected to the input unit.

The output of the inverter Iv6 is connected to the inputs of the NAND circuits ND12 and ND13, respectively, and the output of the inverter Iv7 is connected to the NAND circuit ND1.
2 input sections.

The output of the inverter Iv8 is connected to the input of the NAND circuit ND13, and the output of the inverter Iv9 is connected to the input of the NAND circuit ND14.

Then, the NAND circuits ND12 to ND1
4, the reduced signals TBak, TBKj, TB
Ki are respectively input to the I / O buffers BF8 to BF10.

The I / O buffers BF8 to BF10 are shown in FIG.
Is the same as that of the second embodiment described above, and is configured by NAND circuits ND9 to ND11 and inverters Iv1 and Iv2. The contraction signal is input to the other input of the NAND circuit ND10.

For example, when bank B0 is rescued by bank B4, inputting bank address signal BA4 outputs "0" to all I / O buffers BF8 to BF10.

When the bank address signal BA0 is input, 'φ' is output to the I / O buffer BF8,
'0' for O-buffer B9 and '0' for I / O-buffer B10
1 'will be output.

Therefore, in the third embodiment, reduction circuit 1
5 to transfer the bank information to three I / O buffers BF8 to
Since the output can be performed by the BF 10, the bank information can be easily output even in the case of a memory configured with a small number of I / O pins of 4 bits or less.

(Embodiment 4) FIG. 12 is an explanatory diagram of banks which are switched by a switching control circuit provided in a memory according to Embodiment 4 of the present invention.

In the fourth embodiment, the memory (semiconductor integrated circuit device) 1 repairs four banks of the memory array 2 having the eight banks of the banks B0 to B7,
It is a synchronous DRAM having a bank configuration.

For example, if the memory capacity is 1 Gbit in an eight-bank configuration, a five-bank
It can be operated as a memory capacity of 12 Mbits. Each of the banks B0 to B7 is provided with a switching control circuit 3 (FIG. 3) including a storage circuit 3a and a switching circuit 3b, as in the first to third embodiments.
The switching control circuit 3 performs bank replacement.

For example, as shown in FIG.
0, B3, and B7 (banks shaded) are non-recoverable banks. In this case, the defective bank B0 is replaced with the bank B
4 (portion indicated by hatching), similarly defective bank B
3 is replaced by a bank B6 (portion indicated by hatching), and a half bank group (here, banks B0 to B3) determined by the highest order of the bank control address is rescued. Note that the hatching in FIG. 12 indicates a bank to be replaced, and does not indicate a cross section.

For the replacement of these banks, a switching control signal is set in the storage circuit 3a of the switching control circuit 3 provided in each of the banks B0 to B7. Bank B0
In order to replace the bank B4, the storage circuit 3a is set so that all the switches of the switching circuit 3b of the bank B0 are turned off so that the bank B0 is not operated, and the input signal to the bank is disabled via the switch. The power supply is fixed so that it operates. Alternatively, the storage circuit 3a is set so that only the switch to which the bank address signal BA4 is input in the switching circuit 3 of the switching control circuit 3 provided in the bank B0 is turned on.

The storage circuit 3a is set so that only the switch to which the bank address signal BA0 is input in the switching circuit 3b of the switching control circuit 3 provided in the bank B4 is turned on.

When this switch is turned on, when a signal for selecting bank B0, that is, when bank address signal BA0 is output from bank select 4, bank B4 is selected and bank B0 and bank B0 are selected. This means that B4 has been replaced.

Similarly, by setting the storage circuit 3a of the switching control circuit 3 provided in each bank, a synchronous DRAM having a 4-bank configuration can be provided. For example, a 1-Gbit memory having an 8-bank configuration can be provided. With capacity, 512M
It can operate as a bit memory capacity.

Here, half of the bank group determined by the highest order of the bank control address is rescued. However, when the operation or other evaluation is performed as a system, only the bank highest address is set to "DON". This is because the memory can be easily used as a memory having half the number of banks of half the capacity simply by setting it to T CARE ′, and when it is used, storage and checking of the address of the defective bank can be eliminated.

Thus, in the fourth embodiment,
By using the switching control circuit 3 to form a bank configuration in which all four bits operate, it can be used as a product with half the memory capacity.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first to fourth embodiments, switching control circuit 3 is provided for each of banks B0 to B7.
However, as shown in FIG. 13, the switching circuit 3b may have a switch configuration in which the connection destination can be arbitrarily switched by the storage circuit 3a in addition to ON / OFF. Here, although not described in detail, the switch configuration of the switching circuit 3b may be a switch using ON / OFF of a MOS transistor or a switching circuit for logic synthesis.

Thus, 1 is applied to banks B0 to B7.
Since only one switching control circuit 3 is required, the circuit configuration can be simplified and the layout area of the semiconductor chip can be reduced.

In the first to fourth embodiments, an eight-bank configuration has been described, but it goes without saying that the present invention is used in a configuration having two or more banks.

Further, a precharge supply control circuit (precharge potential supply means) 16 for controlling the supply of the bit line precharge potential is provided in the memory 1 provided with the switching control circuit 3 in the first to fourth embodiments. You may.

In this case, the precharge supply control circuit 16
Are turned on / off based on a storage circuit 16a and a control signal of the storage circuit 16a, as shown in FIGS.
Is performed by a switching circuit 16b which is a switch for performing the operation.

The banks B0 to B7 in the memory 1 include:
One of the switches of the switching circuit 16b is connected to one of the switches, and the other connection is connected to the bit line precharge potential generating circuit 17.

By turning off the switch of the defective bank and stopping the supply of the precharge potential to the defective bank, it is possible to prevent the leakage current of the defective bank. Stable supply is possible, and current consumption can be reduced.

[0099]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the switching control means replaces a memory bank that cannot be relieved with a memory bank that operates on all bits, so that it can be used as a product having half the memory capacity.

(2) Further, according to the present invention, the bank enable means can be used as a regular memory capacity product using two rescued half memory banks.
In addition, an increase in operating current can be suppressed.

(3) Further, in the present invention, the precharge potential supply means for supplying the bit line precharge potential to only half of the memory banks operating all bits is provided.
A current leak or the like in a defective memory bank can be prevented, and a precharge potential can be stably supplied.

(4) Further, according to the present invention, the bank information monitoring means outputs the bank switching information of the switched memory bank to a predetermined external input / output terminal, so that failure analysis, reliability evaluation and the like can be easily performed. Can be done.

(5) In the present invention, the above (1) to (5)
According to (4), even a semiconductor chip having a memory bank that cannot be repaired can be commercialized, so that the yield of the semiconductor integrated circuit device can be greatly improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a connection state of a memory according to a first embodiment of the present invention;

FIG. 2 is a block diagram of a memory according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a switching control circuit provided in the memory according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a bank select provided in the memory according to the first embodiment of the present invention;

FIG. 5 is an explanatory diagram of a bank in one semiconductor chip that is switched by the switching control circuit according to the first embodiment of the present invention;

FIG. 6 is an explanatory diagram of a bank in the other semiconductor chip which is switched by the switching control circuit according to the first embodiment of the present invention;

FIG. 7 is a timing chart in the memory according to the first embodiment of the present invention.

FIG. 8 is an explanatory diagram of a switching control circuit and an I / O buffer provided in a memory according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram of an I / O buffer according to a second embodiment of the present invention.

FIG. 10 is an explanatory diagram of a switching control circuit and a reduction circuit provided in a memory according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram of a reduction circuit according to a third embodiment of the present invention.

FIG. 12 is an explanatory diagram of banks switched by a switching control circuit provided in a memory according to a fourth embodiment of the present invention.

FIG. 13 is an explanatory diagram of a switching control circuit provided in a memory according to another embodiment of the present invention.

FIG. 14 is an explanatory diagram of a precharge supply control circuit provided in a memory according to another embodiment of the present invention.

FIG. 15 is an explanatory diagram of a precharge supply control circuit provided in a memory according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 memory (semiconductor integrated circuit device) 2, 2a memory array 3 switching control circuit (switching control unit) 3a storage circuit (switching control unit) 3b switching circuit (switching unit) 4 bank select (bank enable control unit) 5 bank address input Buffer 6 Row decoder 7 Row control 8 Column decoder 9 Column control 10 Row / column address buffer 11 Address input buffer 12 Bank address input buffer 13 Clock input buffer 14 Internal clock generation circuit 15 Reduction circuit 16 Precharge supply control circuit (Precharge) Potential supply means) 16a storage circuit 16b switching circuit 17 bit line precharge potential generation circuit CH1, CH2 semiconductor chip T test mode control circuit BF0-BF10 I / Buffer B0~B7 banks (memory banks) NR1～NR8 NOR circuit ND1~ND8 NAND circuit ND9~ND11 NAND circuit Iv1~Iv9 inverter ND12~ND14 NAND circuit

Claims (6)

[Claims] In a semiconductor integrated circuit device provided with a plurality of memory banks divided for each predetermined bit, a memory bank that cannot be repaired and a memory bank that operates on all bits are replaced. A semiconductor integrated circuit device comprising switching control means for relieving half of memory banks. 2. The semiconductor integrated circuit device according to claim 1, wherein the switching control unit stores preset data and outputs the data as a switching control signal, and the switching control unit. And a switching unit that outputs a bank address signal output from a bank select based on a switching control signal output from the memory bank to a preset memory bank that operates on all bits. 3. The semiconductor integrated circuit device according to claim 1, wherein the first signal and the second signal, which are complementary signals of the highest address of the bank, are monitored and any one of the first signal and the second signal is monitored. A semiconductor integrated circuit device comprising: bank enable control means for operating the half of the memory banks rescued by the switching control means when either one of them is input. 4. The semiconductor integrated circuit device according to claim 3, wherein a normal memory capacity is formed by two rescued half memory banks, and said bank enable is performed based on a first signal or a second signal. A semiconductor integrated circuit device, wherein the control means selectively operates one of the half of the two rescued memory banks. 5. The semiconductor integrated circuit device according to claim 1, further comprising precharge potential supply means for supplying a bit line precharge potential to only half of said memory banks. Semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 1, wherein bank switching information of said memory bank switched by said switching control means is output to a predetermined external input / output terminal. A semiconductor integrated circuit device comprising information monitoring means.